From 651d6a283f39c9cabf46e8305424ca192c2d0289 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 3 Jul 2026 14:38:00 +0800 Subject: [PATCH] refactor(esp_common): centralize ALIGN_UP/ALIGN_DOWN into esp_macros.h Remove ~50 duplicate local definitions of ALIGN_UP/ALIGN_DOWN/ALIGN_UP_BY/ ALIGN_DOWN_BY across the codebase and replace them with canonical ESP_ALIGN_UP/ESP_ALIGN_DOWN from esp_macros.h. --- components/app_update/esp_ota_ops.c | 6 ++-- .../src/bootloader_common_loader.c | 4 +-- .../bootloader_support/src/esp_image_format.c | 9 +++-- .../src/secure_boot_v2/secure_boot.c | 4 +-- .../secure_boot_signatures_app.c | 6 ++-- .../secure_boot_signatures_bootloader.c | 5 ++- components/esp_common/include/esp_macros.h | 14 ++++++++ .../test_apps/esp_common/main/test_attr.c | 5 ++- .../dvp/src/esp_cam_ctlr_dvp_cam.c | 9 ++--- .../dvp/src/esp_cam_ctlr_dvp_gdma.c | 5 ++- components/esp_driver_dma/src/dw_gdma.c | 2 -- components/esp_driver_dma/src/esp_dma_utils.c | 2 -- components/esp_driver_dma/src/gdma_link.c | 12 +++---- .../test_apps/dma/main/test_gdma.c | 6 ++-- .../test_apps/dma2d/main/test_dma2d.c | 7 ++-- components/esp_driver_jpeg/jpeg_decode.c | 4 +-- components/esp_driver_jpeg/jpeg_encode.c | 6 ++-- components/esp_driver_jpeg/jpeg_private.h | 5 ++- components/esp_driver_parlio/src/parlio_rx.c | 2 -- .../test_apps/parlio/main/test_parlio_rx.c | 17 ++++------ .../test_apps/main/test_ppa.cpp | 25 +++++++------- components/esp_driver_rmt/src/rmt_private.h | 4 +-- components/esp_driver_rmt/src/rmt_rx.c | 12 +++---- components/esp_driver_rmt/src/rmt_tx.c | 2 +- .../lowpower/port/esp32s3/sleep_cpu.c | 9 ++--- .../port/esp32c5/cpu_region_protect.c | 8 ++--- .../port/esp32c6/cpu_region_protect.c | 5 +-- .../port/esp32c61/cpu_region_protect.c | 8 ++--- .../port/esp32h2/cpu_region_protect.c | 5 +-- .../port/esp32h21/cpu_region_protect.c | 5 +-- .../port/esp32p4/cpu_region_protect.c | 16 ++++----- .../port/esp32s31/cpu_region_protect.c | 6 ++-- .../mipi_dsi_lcd/main/test_mipi_dsi_panel.c | 14 ++++---- components/esp_mm/esp_cache_msync.c | 2 -- components/esp_mm/esp_cache_utils.c | 2 -- components/esp_mm/esp_mmu_map.c | 18 ++++------ .../esp_mm/test_apps/mm/main/test_mmap.c | 4 +-- components/esp_partition/partition.c | 5 ++- components/esp_psram/system_layer/esp_psram.c | 2 -- .../esp_psram/xip_impl/mmu_psram_flash.c | 20 +++++------ .../esp_psram/xip_impl/mmu_psram_flash_v2.c | 34 +++++++++---------- .../patches/esp_rom_cache_esp32s2_esp32s3.c | 8 ++--- .../port/arch/riscv/expression_with_stack.c | 7 ++-- .../port/soc/esp32c5/system_internal.c | 3 +- .../port/soc/esp32c61/system_internal.c | 3 +- .../port/soc/esp32h4/system_internal.c | 3 +- .../port/soc/esp32p4/system_internal.c | 3 +- .../port/soc/esp32s2/system_internal.c | 4 +-- .../port/soc/esp32s3/system_internal.c | 4 +-- .../port/soc/esp32s31/system_internal.c | 3 +- .../attestation/esp_att_utils_part_info.c | 4 +-- .../components/tee_flash_mgr/esp_tee_flash.c | 5 ++- .../tee_test_fw/main/test_esp_tee_ota.c | 5 ++- components/espcoredump/src/core_dump_elf.c | 22 +++++------- .../FreeRTOS-Kernel-SMP/portable/riscv/port.c | 15 +++----- .../portable/xtensa/port.c | 23 +++++-------- .../FreeRTOS-Kernel/portable/riscv/port.c | 17 ++++------ .../FreeRTOS-Kernel/portable/xtensa/port.c | 23 +++++-------- components/heap/multi_heap.c | 4 --- components/heap/multi_heap_poisoning.c | 2 -- .../mbedtls/port/aes/dma/esp_aes_dma_core.c | 27 +++++++-------- .../test_apps/mbedtls_ut/main/test_psa_aes.c | 6 ++-- .../shared/ulp_lp_core_memory_shared.c | 5 ++- .../mipi_dsi/main/mipi_dsi_lcd_example_main.c | 8 ++--- .../main/device_cdc_main.c | 7 ++-- .../system/panic/common/main/test_memprot.c | 3 +- 66 files changed, 241 insertions(+), 309 deletions(-) diff --git a/components/app_update/esp_ota_ops.c b/components/app_update/esp_ota_ops.c index 4ee7814beaf..702fe0dd595 100644 --- a/components/app_update/esp_ota_ops.c +++ b/components/app_update/esp_ota_ops.c @@ -31,12 +31,12 @@ #include "esp_bootloader_desc.h" #include "esp_flash.h" #include "esp_private/esp_flash_internal.h" //For dangerous write protection +#include "esp_macros.h" #if CONFIG_SECURE_SIGNED_DATA_PARTITION #include "psa/crypto.h" #endif // CONFIG_SECURE_SIGNED_DATA_PARTITION #define OTA_SLOT(i) (i & 0x0F) -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) /* Partial_data is word aligned so no reallocation is necessary for encrypted flash write */ typedef struct ota_ops_entry_ { @@ -212,7 +212,7 @@ esp_err_t esp_ota_begin(const esp_partition_t *partition, size_t image_size, esp if ((image_size == 0) || (image_size == OTA_SIZE_UNKNOWN)) { erase_size = partition->size; } else { - erase_size = ALIGN_UP(image_size, partition->erase_size); + erase_size = ESP_ALIGN_UP(image_size, partition->erase_size); } esp_err_t err = esp_partition_erase_range(partition, 0, erase_size); if (err != ESP_OK) { @@ -549,7 +549,7 @@ static esp_err_t ota_verify_data_partition_signature(const esp_partition_t *part uint32_t data_length = ((total_written_size) & ~((SPI_FLASH_SEC_SIZE) - 1)) - SPI_FLASH_SEC_SIZE; /* Rounding off data length to the upper 4k boundary for hash calculation */ - uint32_t padded_length = ALIGN_UP(data_length, SPI_FLASH_SEC_SIZE); + uint32_t padded_length = ESP_ALIGN_UP(data_length, SPI_FLASH_SEC_SIZE); #if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS err = ota_calc_partition_bin_sha(partition, padded_length, digest, PSA_ALG_SHA_384); #else diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c index 95137eae797..900585a398d 100644 --- a/components/bootloader_support/src/bootloader_common_loader.c +++ b/components/bootloader_support/src/bootloader_common_loader.c @@ -26,10 +26,10 @@ #include "sys/param.h" #include "bootloader_flash_priv.h" #include "esp_rom_caps.h" +#include "esp_macros.h" #define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */ #define IS_FIELD_SET(rev_full) (((rev_full) != 65535) && ((rev_full) != 0)) -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) ESP_LOG_ATTR_TAG(TAG, "boot_comm"); @@ -272,7 +272,7 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void) #else /* Since the structure containing the retain_mem_t is aligned on 8 by the linker, make sure we align this * structure size here too */ - #define RETAIN_MEM_SIZE ALIGN_UP(sizeof(rtc_retain_mem_t), 8) + #define RETAIN_MEM_SIZE ESP_ALIGN_UP(sizeof(rtc_retain_mem_t), 8) #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - RETAIN_MEM_SIZE) #endif //ESP_ROM_HAS_LP_ROM diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index 1ea161ffb61..0166f34ce3b 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -26,8 +26,7 @@ #include "spi_flash_mmap.h" #include "hal/efuse_hal.h" #include "sdkconfig.h" - -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#include "esp_macros.h" /* Checking signatures as part of verifying images is necessary: - Always if secure boot is enabled @@ -1039,7 +1038,7 @@ static esp_err_t process_appended_hash_and_sig(esp_image_metadata_t *data, uint3 // sector (offset 0x0) and does not get appended to the image. #if CONFIG_SECURE_BOOT_V2_ENABLED // Sanity check - secure boot v2 signature block starts on 4K boundary - sig_block_len = ALIGN_UP(end, FLASH_SECTOR_SIZE) - end; + sig_block_len = ESP_ALIGN_UP(end, FLASH_SECTOR_SIZE) - end; sig_block_len += sizeof(ets_secure_boot_signature_t); #endif } else { @@ -1048,7 +1047,7 @@ static esp_err_t process_appended_hash_and_sig(esp_image_metadata_t *data, uint3 sig_block_len = sizeof(esp_secure_boot_sig_block_t); #else // Sanity check - secure boot v2 signature block starts on 4K boundary - sig_block_len = ALIGN_UP(end, FLASH_SECTOR_SIZE) - end; + sig_block_len = ESP_ALIGN_UP(end, FLASH_SECTOR_SIZE) - end; sig_block_len += sizeof(ets_secure_boot_signature_t); #endif } @@ -1179,7 +1178,7 @@ static esp_err_t verify_secure_boot_signature(bootloader_sha256_handle_t sha_han #if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME || CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME // End of the image needs to be padded all the way to a 4KB boundary, after the simple hash // (for apps they are usually already padded due to --secure-pad-v2, only a problem if this option was not used.) - uint32_t padded_end = ALIGN_UP(end, FLASH_SECTOR_SIZE); + uint32_t padded_end = ESP_ALIGN_UP(end, FLASH_SECTOR_SIZE); if (padded_end > end) { const void *padding = bootloader_mmap(end, padded_end - end); #if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS diff --git a/components/bootloader_support/src/secure_boot_v2/secure_boot.c b/components/bootloader_support/src/secure_boot_v2/secure_boot.c index 3d57cbf62c9..111991477a9 100644 --- a/components/bootloader_support/src/secure_boot_v2/secure_boot.c +++ b/components/bootloader_support/src/secure_boot_v2/secure_boot.c @@ -15,6 +15,7 @@ #include "esp_efuse.h" #include "esp_efuse_table.h" #include "secure_boot_signature_priv.h" +#include "esp_macros.h" /* The following API implementations are used only when called @@ -27,7 +28,6 @@ extern esp_image_metadata_t tee_data; #endif -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) ESP_LOG_ATTR_TAG(TAG, "secure_boot_v2"); /* A signature block is valid when it has correct magic byte, crc and image digest. */ @@ -72,7 +72,7 @@ static esp_err_t s_calculate_image_public_key_digests(uint32_t flash_offset, uin esp_err_t ret = ESP_FAIL; uint8_t image_digest[ESP_SECURE_BOOT_DIGEST_LEN] = {0}; uint8_t __attribute__((aligned(4))) key_digest[ESP_SECURE_BOOT_KEY_DIGEST_SHA_256_LEN] = {0}; - size_t sig_block_addr = flash_offset + ALIGN_UP(flash_size, FLASH_SECTOR_SIZE); + size_t sig_block_addr = flash_offset + ESP_ALIGN_UP(flash_size, FLASH_SECTOR_SIZE); ESP_LOGD(TAG, "calculating public key digests for sig blocks of image offset 0x%" PRIx32 " (sig block offset 0x%x)", flash_offset, sig_block_addr); diff --git a/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_app.c b/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_app.c index 5f9a5b17fa3..44a2ea05f1c 100644 --- a/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_app.c +++ b/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_app.c @@ -19,6 +19,7 @@ #include "esp_efuse_chip.h" #include "secure_boot_signature_priv.h" +#include "esp_macros.h" // Secure boot V2 for app @@ -29,7 +30,6 @@ _Static_assert(SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS == SECURE_BOOT_NUM_BLOCKS, #if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME || CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME || CONFIG_SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT ESP_LOG_ATTR_TAG(TAG, "secure_boot_v2"); -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) /* A signature block is valid when it has correct magic byte, crc. */ static esp_err_t validate_signature_block(const ets_secure_boot_sig_block_t *block) @@ -64,7 +64,7 @@ static esp_err_t calculate_image_public_key_digests(bool verify_image_digest, bo uint8_t image_digest[ESP_SECURE_BOOT_DIGEST_LEN] = {0}; uint8_t __attribute__((aligned(4))) key_digest[ESP_SECURE_BOOT_KEY_DIGEST_SHA_256_LEN] = {0}; - size_t sig_block_addr = img_metadata.start_addr + ALIGN_UP(img_metadata.image_len, FLASH_SECTOR_SIZE); + size_t sig_block_addr = img_metadata.start_addr + ESP_ALIGN_UP(img_metadata.image_len, FLASH_SECTOR_SIZE); ESP_LOGD(TAG, "calculating public key digests for sig blocks of image offset 0x%"PRIu32" (sig block offset 0x%u)", img_metadata.start_addr, sig_block_addr); @@ -182,7 +182,7 @@ esp_err_t esp_secure_boot_verify_signature(uint32_t src_addr, uint32_t length) uint8_t digest[ESP_SECURE_BOOT_DIGEST_LEN] = {0}; /* Rounding off length to the upper 4k boundary */ - uint32_t padded_length = ALIGN_UP(length, FLASH_SECTOR_SIZE); + uint32_t padded_length = ESP_ALIGN_UP(length, FLASH_SECTOR_SIZE); ESP_LOGD(TAG, "verifying signature src_addr 0x%"PRIx32" length 0x%"PRIx32, src_addr, length); #if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS diff --git a/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c b/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c index 71cc6dcd7f6..f81e8972b8f 100644 --- a/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c +++ b/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c @@ -15,6 +15,7 @@ #include "esp_image_format.h" #include "esp_secure_boot.h" #include "esp_efuse.h" +#include "esp_macros.h" // Secure boot V2 for bootloader. @@ -22,8 +23,6 @@ ESP_LOG_ATTR_TAG(TAG, "secure_boot_v2"); -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - esp_err_t esp_secure_boot_verify_signature(uint32_t src_addr, uint32_t length) { esp_err_t err = ESP_FAIL; @@ -31,7 +30,7 @@ esp_err_t esp_secure_boot_verify_signature(uint32_t src_addr, uint32_t length) uint8_t verified_digest[ESP_SECURE_BOOT_DIGEST_LEN] = { 0 }; /* Note: this function doesn't do any anti-FI checks on this buffer */ /* Rounding off length to the upper 4k boundary */ - uint32_t padded_length = ALIGN_UP(length, FLASH_SECTOR_SIZE); + uint32_t padded_length = ESP_ALIGN_UP(length, FLASH_SECTOR_SIZE); ESP_LOGD(TAG, "verifying signature src_addr 0x%" PRIx32 " length 0x%" PRIx32, src_addr, length); /* Calculate digest of main image */ diff --git a/components/esp_common/include/esp_macros.h b/components/esp_common/include/esp_macros.h index 5400bf4fc4a..9c3ed59ba13 100644 --- a/components/esp_common/include/esp_macros.h +++ b/components/esp_common/include/esp_macros.h @@ -91,6 +91,20 @@ static inline __attribute__((always_inline, __noreturn__)) void esp_infinite_loo } #define ESP_INFINITE_LOOP() esp_infinite_loop() +/** + * @brief Round value up to a given alignment (must be a power of 2) + * @param val Value to align + * @param align Alignment value (must be a power of 2) + */ +#define ESP_ALIGN_UP(val, align) (((val) + ((align) - 1)) & ~((align) - 1)) + +/** + * @brief Round value down to a given alignment (must be a power of 2) + * @param val Value to align + * @param align Alignment value (must be a power of 2) + */ +#define ESP_ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) + #ifdef __cplusplus } #endif diff --git a/components/esp_common/test_apps/esp_common/main/test_attr.c b/components/esp_common/test_apps/esp_common/main/test_attr.c index d349c93b5a2..bf9dab9d64d 100644 --- a/components/esp_common/test_apps/esp_common/main/test_attr.c +++ b/components/esp_common/test_apps/esp_common/main/test_attr.c @@ -13,12 +13,11 @@ #include "hal/cache_ll.h" #include "hal/cache_hal.h" #include "esp_cache.h" +#include "esp_macros.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp_private/esp_psram_extram.h" #endif -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - ESP_LOG_ATTR_TAG(TAG, "attr_test"); extern int _rtc_noinit_start; @@ -107,7 +106,7 @@ static void write_spiram_and_reset(void) #else size_t psram_alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); uint32_t ext_noinit_size = sizeof(s_noinit_buffer); - TEST_ESP_OK(esp_cache_msync(&s_noinit_buffer, ALIGN_UP(ext_noinit_size, psram_alignment), ESP_CACHE_MSYNC_FLAG_DIR_C2M)); + TEST_ESP_OK(esp_cache_msync(&s_noinit_buffer, ESP_ALIGN_UP(ext_noinit_size, psram_alignment), ESP_CACHE_MSYNC_FLAG_DIR_C2M)); #endif printf("Restarting\n"); diff --git a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c index a64df57d63e..3d8c36300ab 100644 --- a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c +++ b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c @@ -11,6 +11,7 @@ #include "hal/color_hal.h" #include "driver/gpio.h" #include "esp_cache.h" +#include "esp_macros.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_cache_private.h" #include "esp_private/gpio.h" @@ -45,8 +46,6 @@ #define CAM_DVP_DATA_SIG_NUM 0 /*!< Default value */ #endif -#define ALIGN_UP_BY(num, align) ((align) == 0 ? (num) : (((num) + ((align) - 1)) & ~((align) - 1))) - #define DVP_CAM_CONFIG_INPUT_PIN(pin, sig, inv) \ { \ if (pin != GPIO_NUM_NC) { \ @@ -230,7 +229,7 @@ static uint32_t IRAM_ATTR esp_cam_ctlr_dvp_get_recved_size(esp_cam_ctlr_dvp_cam_ uint32_t recv_buffer_size; if (ctlr->pic_format_jpeg) { - recv_buffer_size = ALIGN_UP_BY(MIN(dma_recv_size, ctlr->fb_size_in_bytes), 64); + recv_buffer_size = ESP_ALIGN_UP(MIN(dma_recv_size, ctlr->fb_size_in_bytes), 64); } else { recv_buffer_size = ctlr->fb_size_in_bytes; } @@ -861,7 +860,9 @@ esp_err_t esp_cam_new_dvp_ctlr(const esp_cam_ctlr_dvp_config_t *config, esp_cam_ ESP_GOTO_ON_ERROR(s_dvp_claim_ctlr(config->ctlr_id, ctlr), fail1, TAG, "no available DVP controller"); ESP_LOGD(TAG, "alignment: 0x%x\n", alignment_size); - fb_size_in_bytes = ALIGN_UP_BY(fb_size_in_bytes, alignment_size); + if (alignment_size) { + fb_size_in_bytes = ESP_ALIGN_UP(fb_size_in_bytes, alignment_size); + } if (!config->bk_buffer_dis) { ctlr->backup_buffer = heap_caps_aligned_alloc(alignment_size, fb_size_in_bytes, DVP_CAM_BK_BUFFER_ALLOC_CAPS); ESP_GOTO_ON_FALSE(ctlr->backup_buffer, ESP_ERR_NO_MEM, fail2, TAG, "no mem for DVP backup buffer"); diff --git a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c index 4164d85fb8b..41f4a670fcf 100644 --- a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c +++ b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c @@ -11,8 +11,7 @@ #include "esp_private/esp_cache_private.h" #include "esp_cam_ctlr_dvp_dma.h" #include "esp_memory_utils.h" - -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#include "esp_macros.h" #if defined(SOC_GDMA_TRIG_PERIPH_CAM0_BUS) && (SOC_GDMA_TRIG_PERIPH_CAM0_BUS == SOC_GDMA_BUS_AHB) #define DVP_GDMA_NEW_CHANNEL gdma_new_ahb_channel @@ -113,7 +112,7 @@ esp_err_t esp_cam_ctlr_dvp_dma_init(esp_cam_ctlr_dvp_dma_t *dma, uint32_t burst_ } dma->size = size; alignment_size = (alignment_size == 0) ? 1 : alignment_size; - dma->desc_size = ALIGN_UP_BY(dma->desc_count * sizeof(esp_cam_ctlr_dvp_dma_desc_t), alignment_size); + dma->desc_size = ESP_ALIGN_UP(dma->desc_count * sizeof(esp_cam_ctlr_dvp_dma_desc_t), alignment_size); ESP_LOGD(TAG, "alignment_size: %d, dma->desc_count: %d, dma->desc_size: %d", alignment_size, dma->desc_count, dma->desc_size); dma->desc = heap_caps_aligned_alloc(alignment_size, dma->desc_size, DVP_GDMA_DESC_ALLOC_CAPS); diff --git a/components/esp_driver_dma/src/dw_gdma.c b/components/esp_driver_dma/src/dw_gdma.c index a8cf6aecb8b..0ec00c65a44 100644 --- a/components/esp_driver_dma/src/dw_gdma.c +++ b/components/esp_driver_dma/src/dw_gdma.c @@ -56,8 +56,6 @@ ESP_LOG_ATTR_TAG(TAG, "dw-gdma"); #define DW_GDMA_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - typedef struct dw_gdma_group_t dw_gdma_group_t; typedef struct dw_gdma_channel_t dw_gdma_channel_t; diff --git a/components/esp_driver_dma/src/esp_dma_utils.c b/components/esp_driver_dma/src/esp_dma_utils.c index 9836f7670a9..03a6b66630a 100644 --- a/components/esp_driver_dma/src/esp_dma_utils.c +++ b/components/esp_driver_dma/src/esp_dma_utils.c @@ -26,8 +26,6 @@ ESP_LOG_ATTR_TAG(TAG, "dma_utils"); -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - esp_err_t esp_dma_split_rx_buffer_to_cache_aligned(void *rx_buffer, size_t buffer_len, dma_buffer_split_array_t *align_buf_array, uint8_t** ret_stash_buffer) { esp_err_t ret = ESP_OK; diff --git a/components/esp_driver_dma/src/gdma_link.c b/components/esp_driver_dma/src/gdma_link.c index 4bd452e4d22..75d50aa0fe8 100644 --- a/components/esp_driver_dma/src/gdma_link.c +++ b/components/esp_driver_dma/src/gdma_link.c @@ -20,12 +20,10 @@ #include "hal/cache_ll.h" #include "esp_cache.h" #include "esp_efuse.h" +#include "esp_macros.h" ESP_LOG_ATTR_TAG(TAG, "gdma-link"); -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) - // GDMA link list item definition // TODO: this type will eventually become target specific, we need to move it to the LL layer or soc layer typedef struct gdma_link_list_item_t gdma_link_list_item_t; @@ -71,7 +69,7 @@ esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_li uint32_t num_items = config->num_items; size_t item_alignment = config->item_alignment ? config->item_alignment : 4; // each list item should align to the specified alignment - size_t item_size = ALIGN_UP(sizeof(gdma_link_list_item_t), item_alignment); + size_t item_size = ESP_ALIGN_UP(sizeof(gdma_link_list_item_t), item_alignment); // guard against overflow when calculating total bytes for descriptors ESP_GOTO_ON_FALSE(num_items <= SIZE_MAX / item_size, ESP_ERR_INVALID_SIZE, err, TAG, "list too big"); @@ -100,7 +98,7 @@ esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_li } if (data_cache_line_size) { // write back and then invalidate the cache, because later we will read/write the link list items by non-cached address - ESP_GOTO_ON_ERROR(esp_cache_msync(items, ALIGN_UP(num_items * item_size, data_cache_line_size), + ESP_GOTO_ON_ERROR(esp_cache_msync(items, ESP_ALIGN_UP(num_items * item_size, data_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE), err, TAG, "cache sync failed"); } @@ -192,7 +190,7 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, int start_item_i } // alignment must be a power of 2 ESP_RETURN_ON_FALSE_ISR((buffer_alignment & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "align err idx=%"PRIu32" align=%"PRIu32, bi, buffer_alignment); - size_t max_buffer_mount_length = ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment); + size_t max_buffer_mount_length = ESP_ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment); if (!config->flags.bypass_buffer_align_check) { ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buf & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "buf misalign idx=%"PRIu32" align=%"PRIu32, bi, buffer_alignment); if (esp_efuse_is_flash_encryption_enabled()) { @@ -219,7 +217,7 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, int start_item_i if (buffer_alignment == 0) { buffer_alignment = 1; } - size_t max_buffer_mount_length = ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment); + size_t max_buffer_mount_length = ESP_ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment); // skip zero-length buffer but scrub any stale descriptor to keep ring clean; no slot consumption if (len == 0 || buf == NULL) { lli_nc = (gdma_link_list_item_t *)(list->items_nc + begin_item_idx % list_item_capacity * item_size); diff --git a/components/esp_driver_dma/test_apps/dma/main/test_gdma.c b/components/esp_driver_dma/test_apps/dma/main/test_gdma.c index 46b19ad90aa..3cad88ee2dc 100644 --- a/components/esp_driver_dma/test_apps/dma/main/test_gdma.c +++ b/components/esp_driver_dma/test_apps/dma/main/test_gdma.c @@ -25,9 +25,7 @@ #include "esp_memory_utils.h" #include "gdma_test_utils.h" #include "esp_efuse.h" - -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) +#include "esp_macros.h" TEST_CASE("GDMA channel allocation", "[GDMA]") { @@ -573,7 +571,7 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_ } if (sram_alignment) { // do write-back for the source data because it's in the cache - TEST_ESP_OK(esp_cache_msync(src_data, ALIGN_UP(data_length, sram_alignment), ESP_CACHE_MSYNC_FLAG_DIR_C2M)); + TEST_ESP_OK(esp_cache_msync(src_data, ESP_ALIGN_UP(data_length, sram_alignment), ESP_CACHE_MSYNC_FLAG_DIR_C2M)); } gdma_buffer_mount_config_t tx_buf_mount_config[] = { diff --git a/components/esp_driver_dma/test_apps/dma2d/main/test_dma2d.c b/components/esp_driver_dma/test_apps/dma2d/main/test_dma2d.c index 40f0be1a69e..83da4ba47ba 100644 --- a/components/esp_driver_dma/test_apps/dma2d/main/test_dma2d.c +++ b/components/esp_driver_dma/test_apps/dma2d/main/test_dma2d.c @@ -18,8 +18,7 @@ #include "esp_heap_caps.h" #include "esp_cache.h" #include "esp_efuse.h" - -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#include "esp_macros.h" // All test will perform `M2M_TRANS_TIMES` times memcpy transactions, utilizing all available 2D-DMA channels. // This tests the hardware capability of multiple 2D-DMA transactions running together, and the driver capbility of @@ -623,9 +622,9 @@ TEST_CASE("DMA2D_M2M_2D_window", "[DMA2D]") uint8_t *prtx; uint8_t *prrx; - size_t tx_buf_size = ALIGN_UP(vb * hb * 2, 64); // buffer msync alignment restriction + size_t tx_buf_size = ESP_ALIGN_UP(vb * hb * 2, 64); // buffer msync alignment restriction uint8_t *tx_buf = heap_caps_aligned_calloc(64, tx_buf_size * M2M_TRANS_TIMES, sizeof(uint8_t), buf_malloc_cap); - size_t rx_buf_size = ALIGN_UP(va * ha * 2, 64); // buffer msync alignment restriction + size_t rx_buf_size = ESP_ALIGN_UP(va * ha * 2, 64); // buffer msync alignment restriction uint8_t *rx_buf = heap_caps_aligned_calloc(64, rx_buf_size * M2M_TRANS_TIMES, sizeof(uint8_t), buf_malloc_cap); TEST_ASSERT_NOT_NULL(tx_buf); TEST_ASSERT_NOT_NULL(rx_buf); diff --git a/components/esp_driver_jpeg/jpeg_decode.c b/components/esp_driver_jpeg/jpeg_decode.c index 9a3df3cc28a..6cdc70ee2fd 100644 --- a/components/esp_driver_jpeg/jpeg_decode.c +++ b/components/esp_driver_jpeg/jpeg_decode.c @@ -76,7 +76,7 @@ esp_err_t jpeg_new_decoder_engine(const jpeg_decode_engine_cfg_t *dec_eng_cfg, j uint32_t cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); uint32_t alignment = cache_line_size; - size_t dma_desc_mem_size = JPEG_ALIGN_UP(sizeof(dma2d_descriptor_t), cache_line_size); + size_t dma_desc_mem_size = ESP_ALIGN_UP(sizeof(dma2d_descriptor_t), cache_line_size); decoder_engine->rxlink = (dma2d_descriptor_t*)heap_caps_aligned_calloc(alignment, 1, dma_desc_mem_size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | JPEG_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(decoder_engine->rxlink, ESP_ERR_NO_MEM, err, TAG, "no memory for jpeg decode rxlink"); @@ -437,7 +437,7 @@ void *jpeg_alloc_decoder_mem(size_t size, const jpeg_decode_memory_alloc_cfg_t * size_t cache_align = 0; esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_align); if (mem_cfg->buffer_direction == JPEG_DEC_ALLOC_OUTPUT_BUFFER) { - size = JPEG_ALIGN_UP(size, cache_align); + size = ESP_ALIGN_UP(size, cache_align); *allocated_size = size; return heap_caps_aligned_calloc(cache_align, 1, size, MALLOC_CAP_SPIRAM); } else { diff --git a/components/esp_driver_jpeg/jpeg_encode.c b/components/esp_driver_jpeg/jpeg_encode.c index 570c9adfa91..41749189da8 100644 --- a/components/esp_driver_jpeg/jpeg_encode.c +++ b/components/esp_driver_jpeg/jpeg_encode.c @@ -113,7 +113,7 @@ esp_err_t jpeg_new_encoder_engine(const jpeg_encode_engine_cfg_t *enc_eng_cfg, j uint32_t cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); uint32_t alignment = cache_line_size; - size_t dma_desc_mem_size = JPEG_ALIGN_UP(sizeof(dma2d_descriptor_t), cache_line_size); + size_t dma_desc_mem_size = ESP_ALIGN_UP(sizeof(dma2d_descriptor_t), cache_line_size); encoder_engine->rxlink = (dma2d_descriptor_t*)heap_caps_aligned_calloc(alignment, 1, dma_desc_mem_size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | JPEG_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(encoder_engine->rxlink, ESP_ERR_NO_MEM, err, TAG, "no memory for jpeg encoder rxlink"); @@ -322,7 +322,7 @@ esp_err_t jpeg_encoder_process(jpeg_encoder_handle_t encoder_engine, const jpeg_ ESP_GOTO_ON_ERROR(esp_cache_msync((void*)encoder_engine->rxlink, encoder_engine->dma_desc_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C), err1, TAG, "sync memory to cache failed"); } compressed_size = s_dma_desc_get_len(encoder_engine->rxlink); - uint32_t _compressed_size = JPEG_ALIGN_UP(compressed_size, cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA)); + uint32_t _compressed_size = ESP_ALIGN_UP(compressed_size, cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA)); cache_line_size = esp_cache_get_line_size_by_addr(bit_stream + encoder_engine->header_info->header_len); if (cache_line_size > 0) { ESP_GOTO_ON_ERROR(esp_cache_msync((void*)(bit_stream + encoder_engine->header_info->header_len), _compressed_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C), err1, TAG, "sync memory to cache failed"); @@ -403,7 +403,7 @@ void *jpeg_alloc_encoder_mem(size_t size, const jpeg_encode_memory_alloc_cfg_t * size_t cache_align = 0; esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_align); if (mem_cfg->buffer_direction == JPEG_ENC_ALLOC_OUTPUT_BUFFER) { - size = JPEG_ALIGN_UP(size, cache_align); + size = ESP_ALIGN_UP(size, cache_align); *allocated_size = size; return heap_caps_aligned_calloc(cache_align, 1, size, MALLOC_CAP_SPIRAM); } else { diff --git a/components/esp_driver_jpeg/jpeg_private.h b/components/esp_driver_jpeg/jpeg_private.h index 3a038ce321b..7c9f187e50f 100644 --- a/components/esp_driver_jpeg/jpeg_private.h +++ b/components/esp_driver_jpeg/jpeg_private.h @@ -8,7 +8,8 @@ #include #include -#include "sys/queue.h" +#include +#include "esp_macros.h" #include "esp_private/dma2d.h" #include "driver/jpeg_types.h" #include "freertos/FreeRTOS.h" @@ -30,8 +31,6 @@ extern "C" { // JPEG encoder and decoder shares same interrupt ID. #define JPEG_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED) -#define JPEG_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - // Use retention link only when the target supports sleep retention and PM is enabled #define JPEG_USE_RETENTION_LINK (CONFIG_PM_ENABLE && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) diff --git a/components/esp_driver_parlio/src/parlio_rx.c b/components/esp_driver_parlio/src/parlio_rx.c index 4bc92783a37..744f70a4998 100644 --- a/components/esp_driver_parlio/src/parlio_rx.c +++ b/components/esp_driver_parlio/src/parlio_rx.c @@ -11,8 +11,6 @@ #include "driver/parlio_rx.h" #include "parlio_priv.h" -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE #define PARLIO_MAX_ALIGNED_DMA_BUF_SIZE DMA_DESCRIPTOR_BUFFER_MAX_SIZE_64B_ALIGNED #else diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c index b1cd80042ac..4e9d6cdde55 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c @@ -25,6 +25,7 @@ #include "esp_attr.h" #include "test_board.h" #include "esp_private/parlio_rx_private.h" +#include "esp_macros.h" #define TEST_SPI_HOST SPI2_HOST #define TEST_I2S_PORT I2S_NUM_0 @@ -68,10 +69,6 @@ typedef struct { uint32_t timeout_cnt; } test_data_t; -#ifndef ALIGN_UP -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#endif - TEST_PARLIO_CALLBACK_ATTR static bool test_parlio_rx_partial_recv_callback(parlio_rx_unit_handle_t rx_unit, const parlio_rx_event_data_t *edata, void *user_data) { @@ -312,7 +309,7 @@ static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_ uint8_t *recv_buff = NULL; uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); alignment = alignment < 4 ? 4 : alignment; - size_t buff_size = ALIGN_UP(TEST_EOF_DATA_LEN, alignment); + size_t buff_size = ESP_ALIGN_UP(TEST_EOF_DATA_LEN, alignment); recv_buff = heap_caps_aligned_calloc(alignment, 1, buff_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS); bool is_success = false; // sample 5 times @@ -477,7 +474,7 @@ TEST_CASE("parallel_rx_unit_receive_transaction_test", "[parlio_rx]") uint8_t *payload = NULL; uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); alignment = alignment < 4 ? 4 : alignment; - size_t payload_size = ALIGN_UP(TEST_PAYLOAD_SIZE, alignment); + size_t payload_size = ESP_ALIGN_UP(TEST_PAYLOAD_SIZE, alignment); payload = heap_caps_aligned_calloc(alignment, 1, payload_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS); TEST_ASSERT(payload); @@ -623,7 +620,7 @@ TEST_CASE("parallel_rx_unit_receive_timeout_test", "[parlio_rx]") uint8_t *payload = NULL; uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); alignment = alignment < 4 ? 4 : alignment; - size_t payload_size = ALIGN_UP(TEST_PAYLOAD_SIZE, alignment); + size_t payload_size = ESP_ALIGN_UP(TEST_PAYLOAD_SIZE, alignment); payload = heap_caps_aligned_calloc(alignment, 1, payload_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS); TEST_ASSERT(payload); @@ -729,7 +726,7 @@ TEST_CASE("parallel_rx_unit_receive_isr_test", "[parlio_rx]") // Allocate DMA compatible buffers uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); alignment = alignment < 4 ? 4 : alignment; - size_t payload_size = ALIGN_UP(1024, alignment); + size_t payload_size = ESP_ALIGN_UP(1024, alignment); uint8_t *payload1 = heap_caps_aligned_calloc(alignment, 1, payload_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS); uint8_t *payload2 = heap_caps_aligned_calloc(alignment, 1, payload_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS); @@ -866,7 +863,7 @@ TEST_CASE("parallel_rx_unit_infinite_transaction_switch_test", "[parlio_rx]") // Allocate DMA compatible buffers uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); alignment = alignment < 4 ? 4 : alignment; - size_t payload_size = ALIGN_UP(1024, alignment); + size_t payload_size = ESP_ALIGN_UP(1024, alignment); uint8_t *payload1 = heap_caps_aligned_calloc(alignment, 1, payload_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS); uint8_t *payload2 = heap_caps_aligned_calloc(alignment, 1, payload_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS); @@ -981,7 +978,7 @@ TEST_CASE("parallel_rx_unit_force_trigger_eof_test", "[parlio_rx][release_only]" uint8_t *recv_buff = NULL; uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); alignment = alignment < 4 ? 4 : alignment; - size_t buff_size = ALIGN_UP(TEST_TASK_LARGE_TRANS_SIZE, alignment); + size_t buff_size = ESP_ALIGN_UP(TEST_TASK_LARGE_TRANS_SIZE, alignment); recv_buff = heap_caps_aligned_calloc(alignment, 1, buff_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS); TEST_ASSERT_NOT_NULL(recv_buff); diff --git a/components/esp_driver_ppa/test_apps/main/test_ppa.cpp b/components/esp_driver_ppa/test_apps/main/test_ppa.cpp index 5ab02567ff8..09f7b263d73 100644 --- a/components/esp_driver_ppa/test_apps/main/test_ppa.cpp +++ b/components/esp_driver_ppa/test_apps/main/test_ppa.cpp @@ -26,8 +26,7 @@ #include "esp_clk_tree.h" #include "esp_private/esp_sleep_internal.h" #include "esp_private/esp_pmu.h" - -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#include "esp_macros.h" TEST_CASE("ppa_client_do_ppa_operation", "[PPA]") { @@ -36,8 +35,8 @@ TEST_CASE("ppa_client_do_ppa_operation", "[PPA]") const esp_color_fourcc_t buf_1_color_type_id = ESP_COLOR_FOURCC_BGRA32; const esp_color_fourcc_t buf_2_color_type_id = ESP_COLOR_FOURCC_BGRA32; - uint32_t buf_1_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth(buf_1_color_type_id) / 8, 64); - uint32_t buf_2_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth(buf_2_color_type_id) / 8, 64); + uint32_t buf_1_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth(buf_1_color_type_id) / 8, 64); + uint32_t buf_2_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth(buf_2_color_type_id) / 8, 64); uint8_t *buf_1 = static_cast(heap_caps_aligned_calloc(4, buf_1_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); // cache alignment is implicited by MALLOC_CAP_DMA TEST_ASSERT_NOT_NULL(buf_1); uint8_t *buf_2 = static_cast(heap_caps_aligned_calloc(4, buf_2_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); @@ -166,7 +165,7 @@ TEST_CASE("ppa_pending_transactions_in_queue", "[PPA]") const esp_color_fourcc_t buf_2_color_type_id = ESP_COLOR_FOURCC_OUYY_EVYY; uint32_t buf_1_size = w * h * color_hal_pixel_format_fourcc_get_bit_depth(buf_1_color_type_id) / 8; - uint32_t buf_2_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth(buf_2_color_type_id) / 8, 64); + uint32_t buf_2_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth(buf_2_color_type_id) / 8, 64); uint8_t *buf_1 = static_cast(heap_caps_aligned_calloc(4, buf_1_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); TEST_ASSERT_NOT_NULL(buf_1); uint8_t *buf_2 = static_cast(heap_caps_aligned_calloc(4, buf_2_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); @@ -273,7 +272,7 @@ static void ppa_srm_basic_data_correctness_check(bool auto_light_sleep) const float scale_y = 1.0; const uint32_t buf_len = w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)cm) / 8; // 32 - uint32_t out_buf_size = ALIGN_UP(buf_len, 64); + uint32_t out_buf_size = ESP_ALIGN_UP(buf_len, 64); uint8_t *out_buf = static_cast(heap_caps_aligned_calloc(4, out_buf_size, sizeof(uint8_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA)); // located in internal RAM so even w/ flash encrypted, it won't be affected TEST_ASSERT_NOT_NULL(out_buf); esp_cache_msync((void *)out_buf, out_buf_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M); @@ -681,7 +680,7 @@ static void ppa_fill_basic_data_correctness_check(bool auto_light_sleep) uint32_t out_pixel_depth = color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm); // bits uint32_t out_buf_len = w * h * out_pixel_depth / 8; - uint32_t out_buf_size = ALIGN_UP(out_buf_len, 64); + uint32_t out_buf_size = ESP_ALIGN_UP(out_buf_len, 64); uint8_t *out_buf = static_cast(heap_caps_aligned_calloc(4, out_buf_size, sizeof(uint8_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA)); TEST_ASSERT_NOT_NULL(out_buf); @@ -816,7 +815,7 @@ TEST_CASE("ppa_srm_performance", "[PPA]") const float scale_y = 1.0; uint32_t in_buf_size = w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)in_cm) / 8; - uint32_t out_buf_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm) / 8, 64); + uint32_t out_buf_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm) / 8, 64); uint8_t *out_buf = static_cast(heap_caps_aligned_calloc(4, out_buf_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); TEST_ASSERT_NOT_NULL(out_buf); uint8_t *in_buf = static_cast(heap_caps_aligned_calloc(4, in_buf_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); @@ -892,9 +891,9 @@ TEST_CASE("ppa_blend_performance", "[PPA]") if (esp_efuse_is_flash_encryption_enabled()) { in_buf_alignment = SOC_MEMSPI_ENCRYPTION_ALIGNMENT; } - uint32_t in_bg_buf_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)in_bg_cm) / 8, in_buf_alignment); - uint32_t in_fg_buf_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)in_fg_cm) / 8, in_buf_alignment); - uint32_t out_buf_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm) / 8, 64); + uint32_t in_bg_buf_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)in_bg_cm) / 8, in_buf_alignment); + uint32_t in_fg_buf_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)in_fg_cm) / 8, in_buf_alignment); + uint32_t out_buf_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm) / 8, 64); uint8_t *out_buf = static_cast(heap_caps_aligned_calloc(4, out_buf_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); TEST_ASSERT_NOT_NULL(out_buf); uint8_t *in_bg_buf = static_cast(heap_caps_aligned_calloc(4, in_bg_buf_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); @@ -976,7 +975,7 @@ TEST_CASE("ppa_fill_performance", "[PPA]") const uint32_t block_h = 480; const ppa_fill_color_mode_t out_cm = PPA_FILL_COLOR_MODE_RGB565; - uint32_t out_buf_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm) / 8, 64); + uint32_t out_buf_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm) / 8, 64); uint8_t *out_buf = static_cast(heap_caps_aligned_calloc(4, out_buf_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); TEST_ASSERT_NOT_NULL(out_buf); @@ -1036,7 +1035,7 @@ TEST_CASE("ppa_srm_stress_test", "[PPA]") const float scale_y = 1.0; uint32_t in_buf_size = w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)in_cm) / 8; - uint32_t out_buf_size = ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm) / 8, 64); + uint32_t out_buf_size = ESP_ALIGN_UP(w * h * color_hal_pixel_format_fourcc_get_bit_depth((esp_color_fourcc_t)out_cm) / 8, 64); uint8_t *out_buf = static_cast(heap_caps_aligned_calloc(4, out_buf_size, sizeof(uint8_t), MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA)); TEST_ASSERT_NOT_NULL(out_buf); uint8_t *in_buf = static_cast(heap_caps_aligned_calloc(4, in_buf_size, sizeof(uint8_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA)); diff --git a/components/esp_driver_rmt/src/rmt_private.h b/components/esp_driver_rmt/src/rmt_private.h index 71070099e5d..1332d5aebcf 100644 --- a/components/esp_driver_rmt/src/rmt_private.h +++ b/components/esp_driver_rmt/src/rmt_private.h @@ -48,6 +48,7 @@ #include "esp_private/esp_clk_tree_common.h" #include "esp_private/esp_dma_utils.h" #include "driver/rmt_types.h" +#include "esp_macros.h" #ifdef __cplusplus extern "C" { @@ -89,9 +90,6 @@ extern "C" { #define RMT_GET_NON_CACHE_ADDR(addr) (addr) #endif -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) - #define RMT_USE_RETENTION_LINK (SOC_RMT_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) #if SOC_RMT_SUPPORT_SLEEP_RETENTION diff --git a/components/esp_driver_rmt/src/rmt_rx.c b/components/esp_driver_rmt/src/rmt_rx.c index 51af2291c21..e93bc4284ea 100644 --- a/components/esp_driver_rmt/src/rmt_rx.c +++ b/components/esp_driver_rmt/src/rmt_rx.c @@ -371,7 +371,7 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_ // Align the buffer address to mem_alignment if ((((uintptr_t)buffer) & (mem_alignment - 1)) != 0) { - uintptr_t aligned_address = ALIGN_UP((uintptr_t)buffer, mem_alignment); + uintptr_t aligned_address = ESP_ALIGN_UP((uintptr_t)buffer, mem_alignment); size_t offset = aligned_address - (uintptr_t)buffer; ESP_RETURN_ON_FALSE_ISR(buffer_size > offset, ESP_ERR_INVALID_ARG, TAG, "buffer size is not aligned and is too small, please increase the buffer size"); ESP_EARLY_LOGD(TAG, "origin buffer %p not satisfy alignment %d, align buffer to %p", buffer, mem_alignment, aligned_address); @@ -379,12 +379,12 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_ buffer_size -= offset; } // Align the buffer size to mem_alignment - buffer_size = ALIGN_DOWN(buffer_size, mem_alignment); + buffer_size = ESP_ALIGN_DOWN(buffer_size, mem_alignment); ESP_RETURN_ON_FALSE_ISR(buffer_size > 0, ESP_ERR_INVALID_ARG, TAG, "buffer size is less than alignment: %"PRIu32", please increase the buffer size", mem_alignment); #if SOC_RMT_SUPPORT_DMA if (channel->dma_chan) { - size_t max_buf_sz_per_dma_node = ALIGN_DOWN(DMA_DESCRIPTOR_BUFFER_MAX_SIZE, mem_alignment); + size_t max_buf_sz_per_dma_node = ESP_ALIGN_DOWN(DMA_DESCRIPTOR_BUFFER_MAX_SIZE, mem_alignment); ESP_RETURN_ON_FALSE_ISR(buffer_size <= rx_chan->num_dma_nodes * max_buf_sz_per_dma_node, ESP_ERR_INVALID_ARG, TAG, "buffer size exceeds DMA capacity: %"PRIu32", please increase the mem_block_symbols", rx_chan->num_dma_nodes * max_buf_sz_per_dma_node); } @@ -424,7 +424,7 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_ } // we will mount the buffer to multiple DMA nodes, in a balanced way size_t per_dma_block_size = buffer_size / rx_chan->num_dma_nodes; - per_dma_block_size = ALIGN_DOWN(per_dma_block_size, mem_alignment); + per_dma_block_size = ESP_ALIGN_DOWN(per_dma_block_size, mem_alignment); size_t last_dma_block_size = buffer_size - per_dma_block_size * (rx_chan->num_dma_nodes - 1); rmt_rx_mount_dma_buffer(rx_chan, buffer, buffer_size, mem_alignment, per_dma_block_size, last_dma_block_size); gdma_reset(channel->dma_chan); @@ -790,7 +790,7 @@ __attribute__((always_inline)) static inline size_t rmt_rx_count_symbols_until_eof(rmt_rx_channel_t *rx_chan, int start_index) { size_t received_bytes = gdma_link_count_buffer_size_till_eof(rx_chan->dma_link, start_index); - received_bytes = ALIGN_UP(received_bytes, sizeof(rmt_symbol_word_t)); + received_bytes = ESP_ALIGN_UP(received_bytes, sizeof(rmt_symbol_word_t)); return received_bytes / sizeof(rmt_symbol_word_t); } @@ -798,7 +798,7 @@ __attribute__((always_inline)) static inline size_t rmt_rx_count_symbols_for_single_block(rmt_rx_channel_t *rx_chan, int desc_index) { size_t received_bytes = gdma_link_get_length(rx_chan->dma_link, desc_index); - received_bytes = ALIGN_UP(received_bytes, sizeof(rmt_symbol_word_t)); + received_bytes = ESP_ALIGN_UP(received_bytes, sizeof(rmt_symbol_word_t)); return received_bytes / sizeof(rmt_symbol_word_t); } diff --git a/components/esp_driver_rmt/src/rmt_tx.c b/components/esp_driver_rmt/src/rmt_tx.c index b1a70e5a580..f021be76090 100644 --- a/components/esp_driver_rmt/src/rmt_tx.c +++ b/components/esp_driver_rmt/src/rmt_tx.c @@ -74,7 +74,7 @@ static esp_err_t rmt_tx_init_dma_link(rmt_tx_channel_t *tx_channel, const rmt_tx // For simplicity, encoder will use the non-cached address to read/write the DMA buffer tx_channel->dma_mem_base_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(dma_mem_base); // the DMA buffer size should be aligned to the DMA requirement - size_t mount_size_per_node = ALIGN_DOWN(config->mem_block_symbols * sizeof(rmt_symbol_word_t) / RMT_DMA_NODES_PING_PONG, int_alignment); + size_t mount_size_per_node = ESP_ALIGN_DOWN(config->mem_block_symbols * sizeof(rmt_symbol_word_t) / RMT_DMA_NODES_PING_PONG, int_alignment); // check the upper and lower bound of mount_size_per_node ESP_RETURN_ON_FALSE(mount_size_per_node >= sizeof(rmt_symbol_word_t), ESP_ERR_INVALID_ARG, TAG, "mem_block_symbols is too small"); diff --git a/components/esp_hw_support/lowpower/port/esp32s3/sleep_cpu.c b/components/esp_hw_support/lowpower/port/esp32s3/sleep_cpu.c index a4f4570e7ba..fcf8dd47499 100644 --- a/components/esp_hw_support/lowpower/port/esp32s3/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/port/esp32s3/sleep_cpu.c @@ -15,6 +15,7 @@ #include "esp_ipc_isr.h" #include "esp_sleep.h" #include "esp_log.h" +#include "esp_macros.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_heap_caps.h" @@ -66,7 +67,7 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c index = (code_seg_vaddr / imode.cache_line_size) % sets; waysgrp = imode.cache_ways >> 2; - code_seg_size = ALIGNUP(imode.cache_line_size, code_seg_size); + code_seg_size = ESP_ALIGN_UP(code_seg_size, imode.cache_line_size); s_tag_mem->icache.start_point = index; s_tag_mem->icache.size = (sets * waysgrp) & 0xff; @@ -76,7 +77,7 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c } s_tag_mem->icache.enable = (code_seg_size != 0) ? 1 : 0; icache_tagmem_blk_gs = s_tag_mem->icache.vld_size ? s_tag_mem->icache.vld_size : sets * waysgrp; - icache_tagmem_blk_gs = ALIGNUP(4, icache_tagmem_blk_gs); + icache_tagmem_blk_gs = ESP_ALIGN_UP(icache_tagmem_blk_gs, 4); ESP_LOGD(TAG, "I-cache size:%"PRIu32" KiB, line size:%d B, ways:%d, sets:%"PRIu32", index:%"PRIu32", tag block groups:%"PRIu32"", (imode.cache_size>>10), imode.cache_line_size, imode.cache_ways, sets, index, icache_tagmem_blk_gs); @@ -86,7 +87,7 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c index = (data_seg_vaddr / dmode.cache_line_size) % sets; waysgrp = dmode.cache_ways >> 2; - data_seg_size = ALIGNUP(dmode.cache_line_size, data_seg_size); + data_seg_size = ESP_ALIGN_UP(data_seg_size, dmode.cache_line_size); s_tag_mem->dcache.start_point = index; s_tag_mem->dcache.size = (sets * waysgrp) & 0x1ff; @@ -100,7 +101,7 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c s_tag_mem->dcache.enable = 1; #endif dcache_tagmem_blk_gs = s_tag_mem->dcache.vld_size ? s_tag_mem->dcache.vld_size : sets * waysgrp; - dcache_tagmem_blk_gs = ALIGNUP(4, dcache_tagmem_blk_gs); + dcache_tagmem_blk_gs = ESP_ALIGN_UP(dcache_tagmem_blk_gs, 4); ESP_LOGD(TAG, "D-cache size:%"PRIu32" KiB, line size:%d B, ways:%d, sets:%"PRIu32", index:%"PRIu32", tag block groups:%"PRIu32"", (dmode.cache_size>>10), dmode.cache_line_size, dmode.cache_ways, sets, index, dcache_tagmem_blk_gs); diff --git a/components/esp_hw_support/port/esp32c5/cpu_region_protect.c b/components/esp_hw_support/port/esp32c5/cpu_region_protect.c index d8f5bd38473..59f1565897a 100644 --- a/components/esp_hw_support/port/esp32c5/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32c5/cpu_region_protect.c @@ -8,6 +8,7 @@ #include "soc/soc.h" #include "esp_cpu.h" #include "esp_fault.h" +#include "esp_macros.h" #include "esp32c5/rom/rom_layout.h" #if !BOOTLOADER_BUILD && CONFIG_SPIRAM #include "esp_private/esp_psram_extram.h" @@ -27,9 +28,8 @@ #define CONDITIONAL_RWX RWX #endif -#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_UP(addr, align) (((addr) + (align) - 1) & ~((align) - 1)) +#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_UP(addr, SOC_MMU_PAGE_SIZE) +#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_DOWN(addr, SOC_MMU_PAGE_SIZE) static void esp_cpu_configure_invalid_regions(void) { @@ -259,7 +259,7 @@ void esp_cpu_configure_region_protection(void) #if CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION size_t available_psram_heap = esp_psram_get_heap_size_to_protect(); PMP_ENTRY_CFG_RESET(10); - PMP_ENTRY_SET(10, ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); + PMP_ENTRY_SET(10, ESP_ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); #endif /* CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */ #else const uint32_t pmpaddr6 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH); diff --git a/components/esp_hw_support/port/esp32c6/cpu_region_protect.c b/components/esp_hw_support/port/esp32c6/cpu_region_protect.c index 9a0870260c7..cea14dc5d2c 100644 --- a/components/esp_hw_support/port/esp32c6/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32c6/cpu_region_protect.c @@ -9,6 +9,7 @@ #include "soc/soc.h" #include "esp_cpu.h" #include "esp_fault.h" +#include "esp_macros.h" #ifdef BOOTLOADER_BUILD // Without L bit set @@ -26,8 +27,8 @@ #define CONDITIONAL_RWX RWX #endif -#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1)) +#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_UP(addr, SOC_MMU_PAGE_SIZE) +#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_DOWN(addr, SOC_MMU_PAGE_SIZE) static void esp_cpu_configure_invalid_regions(void) { diff --git a/components/esp_hw_support/port/esp32c61/cpu_region_protect.c b/components/esp_hw_support/port/esp32c61/cpu_region_protect.c index 07ad769289e..816813b2ba3 100644 --- a/components/esp_hw_support/port/esp32c61/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32c61/cpu_region_protect.c @@ -9,6 +9,7 @@ #include "soc/soc.h" #include "esp_cpu.h" #include "esp_fault.h" +#include "esp_macros.h" #include "esp32c61/rom/rom_layout.h" #if !BOOTLOADER_BUILD && CONFIG_SPIRAM #include "esp_private/esp_psram_extram.h" @@ -28,9 +29,8 @@ #define CONDITIONAL_RWX RWX #endif -#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_UP(addr, align) (((addr) + (align) - 1) & ~((align) - 1)) +#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_UP(addr, SOC_MMU_PAGE_SIZE) +#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_DOWN(addr, SOC_MMU_PAGE_SIZE) static void esp_cpu_configure_invalid_regions(void) { @@ -240,7 +240,7 @@ void esp_cpu_configure_region_protection(void) #if CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION size_t available_psram_heap = esp_psram_get_heap_size_to_protect(); PMP_ENTRY_CFG_RESET(11); - PMP_ENTRY_SET(11, ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); + PMP_ENTRY_SET(11, ESP_ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); #endif /* CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */ #else const uint32_t pmpaddr7 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH); diff --git a/components/esp_hw_support/port/esp32h2/cpu_region_protect.c b/components/esp_hw_support/port/esp32h2/cpu_region_protect.c index 52fa0a06527..b0fa5acda32 100644 --- a/components/esp_hw_support/port/esp32h2/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32h2/cpu_region_protect.c @@ -9,6 +9,7 @@ #include "soc/soc.h" #include "esp_cpu.h" #include "esp_fault.h" +#include "esp_macros.h" #ifdef BOOTLOADER_BUILD // Without L bit set @@ -26,8 +27,8 @@ #define CONDITIONAL_RWX RWX #endif -#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1)) +#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_UP(addr, SOC_MMU_PAGE_SIZE) +#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_DOWN(addr, SOC_MMU_PAGE_SIZE) static void esp_cpu_configure_invalid_regions(void) { diff --git a/components/esp_hw_support/port/esp32h21/cpu_region_protect.c b/components/esp_hw_support/port/esp32h21/cpu_region_protect.c index 3ad86e928f3..9349733debc 100644 --- a/components/esp_hw_support/port/esp32h21/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32h21/cpu_region_protect.c @@ -9,6 +9,7 @@ #include "soc/soc.h" #include "esp_cpu.h" #include "esp_fault.h" +#include "esp_macros.h" #include "esp32h21/rom/rom_layout.h" #ifdef BOOTLOADER_BUILD @@ -27,8 +28,8 @@ #define CONDITIONAL_RWX RWX #endif -#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1)) +#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_UP(addr, SOC_MMU_PAGE_SIZE) +#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_DOWN(addr, SOC_MMU_PAGE_SIZE) static void esp_cpu_configure_invalid_regions(void) { diff --git a/components/esp_hw_support/port/esp32p4/cpu_region_protect.c b/components/esp_hw_support/port/esp32p4/cpu_region_protect.c index ab682877734..37dc596fb29 100644 --- a/components/esp_hw_support/port/esp32p4/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32p4/cpu_region_protect.c @@ -11,6 +11,7 @@ #include "esp_fault.h" #include "hal/cache_ll.h" #include "riscv/csr.h" +#include "esp_macros.h" #if !BOOTLOADER_BUILD && CONFIG_SPIRAM #include "esp_private/esp_psram_extram.h" #endif /* !BOOTLOADER_BUILD && CONFIG_SPIRAM */ @@ -34,9 +35,8 @@ #define CONDITIONAL_RWX RWX #endif -#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_UP(addr, align) (((addr) + (align) - 1) & ~((align) - 1)) +#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_UP(addr, SOC_MMU_PAGE_SIZE) +#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_DOWN(addr, SOC_MMU_PAGE_SIZE) static void esp_cpu_configure_invalid_regions(void) { @@ -175,19 +175,19 @@ static void esp_cpu_configure_region_protection_rev_v3(void) PMP_ENTRY_SET_CACHED_AND_UNCACHED(11, 16, (uint32_t)(&_instruction_reserved_end), PMP_TOR | RX); PMP_ENTRY_SET_CACHED_AND_UNCACHED(12, 17, page_aligned_irom_resv_end, PMP_TOR | RW); PMP_ENTRY_SET_CACHED_AND_UNCACHED(13, 18, (uint32_t)(&_rodata_reserved_end), PMP_TOR | R); - PMP_ENTRY_SET_CACHED_AND_UNCACHED(14, 19, ALIGN_UP((uint32_t)(&_rodata_reserved_end) + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); + PMP_ENTRY_SET_CACHED_AND_UNCACHED(14, 19, ESP_ALIGN_UP((uint32_t)(&_rodata_reserved_end) + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); #elif CONFIG_SPIRAM_FETCH_INSTRUCTIONS PMP_ENTRY_SET_CACHED_AND_UNCACHED(11, 16, (uint32_t)(&_instruction_reserved_end), PMP_TOR | RX); PMP_ENTRY_SET_CACHED_AND_UNCACHED(12, 17, page_aligned_irom_resv_end, PMP_TOR | RW); - PMP_ENTRY_SET_CACHED_AND_UNCACHED(13, 18, ALIGN_UP(page_aligned_irom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); + PMP_ENTRY_SET_CACHED_AND_UNCACHED(13, 18, ESP_ALIGN_UP(page_aligned_irom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); #elif CONFIG_SPIRAM_RODATA PMP_ENTRY_SET_CACHED_AND_UNCACHED(11, 16, (uint32_t)(&_rodata_reserved_end), PMP_TOR | R); - PMP_ENTRY_SET_CACHED_AND_UNCACHED(12, 17, ALIGN_UP((uint32_t)(&_rodata_reserved_end) + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); + PMP_ENTRY_SET_CACHED_AND_UNCACHED(12, 17, ESP_ALIGN_UP((uint32_t)(&_rodata_reserved_end) + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); #else - PMP_ENTRY_SET_CACHED_AND_UNCACHED(11, 16, ALIGN_UP(SOC_EXTRAM_LOW + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); + PMP_ENTRY_SET_CACHED_AND_UNCACHED(11, 16, ESP_ALIGN_UP(SOC_EXTRAM_LOW + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); #endif #endif /* CONFIG_SPIRAM && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */ @@ -322,7 +322,7 @@ static void esp_cpu_configure_region_protection_rev_less_than_v3(void) size_t available_psram_heap = esp_psram_get_heap_size_to_protect(); PMP_ENTRY_CFG_RESET(10); - PMP_ENTRY_SET(10, ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); + PMP_ENTRY_SET(10, ESP_ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW); #else PMP_ENTRY_CFG_RESET(6); PMP_ENTRY_CFG_RESET(7); diff --git a/components/esp_hw_support/port/esp32s31/cpu_region_protect.c b/components/esp_hw_support/port/esp32s31/cpu_region_protect.c index 23ff084deb9..17506593ae5 100644 --- a/components/esp_hw_support/port/esp32s31/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32s31/cpu_region_protect.c @@ -11,6 +11,7 @@ #include "esp_fault.h" #include "hal/cache_ll.h" #include "riscv/csr.h" +#include "esp_macros.h" #if !BOOTLOADER_BUILD && CONFIG_SPIRAM #include "esp_private/esp_psram_extram.h" #endif /* !BOOTLOADER_BUILD && CONFIG_SPIRAM */ @@ -33,9 +34,8 @@ #define CONDITIONAL_RWX RWX #endif -#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1)) -#define ALIGN_UP(addr, align) (((addr) + (align) - 1) & ~((align) - 1)) +#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_UP(addr, SOC_MMU_PAGE_SIZE) +#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_DOWN(addr, SOC_MMU_PAGE_SIZE) void esp_cpu_configure_region_protection(void) { diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c index 1c642b9ded6..a4961d0c48d 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c @@ -18,9 +18,7 @@ #include "esp_lcd_ek79007.h" #include "driver/ppa.h" #include "esp_efuse.h" - -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) +#include "esp_macros.h" TEST_CASE("MIPI DSI Pattern Generator (EK79007)", "[mipi_dsi]") { @@ -251,17 +249,17 @@ TEST_CASE("MIPI DSI use DMA2D (EK79007)", "[mipi_dsi]") size_t src_y_start = 50; // If flash encryption is enabled, the buffer address and size must be aligned to SOC_MEMSPI_ENCRYPTION_ALIGNMENT. if (esp_efuse_is_flash_encryption_enabled()) { - test_block_size = ALIGN_DOWN(test_block_size, SOC_MEMSPI_ENCRYPTION_ALIGNMENT); + test_block_size = ESP_ALIGN_DOWN(test_block_size, SOC_MEMSPI_ENCRYPTION_ALIGNMENT); start_alignment = SOC_MEMSPI_ENCRYPTION_ALIGNMENT; - src_x_start = ALIGN_DOWN(src_x_start, SOC_MEMSPI_ENCRYPTION_ALIGNMENT); - src_y_start = ALIGN_DOWN(src_y_start, SOC_MEMSPI_ENCRYPTION_ALIGNMENT); + src_x_start = ESP_ALIGN_DOWN(src_x_start, SOC_MEMSPI_ENCRYPTION_ALIGNMENT); + src_y_start = ESP_ALIGN_DOWN(src_y_start, SOC_MEMSPI_ENCRYPTION_ALIGNMENT); } printf("Add Built-in DMA2D draw bitmap hook\r\n"); TEST_ESP_OK(esp_lcd_dpi_panel_enable_dma2d(mipi_dpi_panel)); for (int i = 0; i < 100; i++) { - int x_start = ALIGN_DOWN(rand() % (MIPI_DSI_LCD_H_RES - test_block_size), start_alignment); - int y_start = ALIGN_DOWN(rand() % (MIPI_DSI_LCD_V_RES - test_block_size), start_alignment); + int x_start = ESP_ALIGN_DOWN(rand() % (MIPI_DSI_LCD_H_RES - test_block_size), start_alignment); + int y_start = ESP_ALIGN_DOWN(rand() % (MIPI_DSI_LCD_V_RES - test_block_size), start_alignment); uint8_t color_byte = rand() & 0xFF; memset(img, color_byte, TEST_IMG_SIZE / 2); color_byte = rand() & 0xFF; diff --git a/components/esp_mm/esp_cache_msync.c b/components/esp_mm/esp_cache_msync.c index 5ef4f9a5323..51a7617e530 100644 --- a/components/esp_mm/esp_cache_msync.c +++ b/components/esp_mm/esp_cache_msync.c @@ -26,8 +26,6 @@ static const char *TAG = "cache"; -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - DEFINE_CRIT_SECTION_LOCK_STATIC(s_spinlock); #if CONFIG_ESP_MM_CACHE_MSYNC_C2M_CHUNKED_OPS static _lock_t s_mutex; diff --git a/components/esp_mm/esp_cache_utils.c b/components/esp_mm/esp_cache_utils.c index f986c3b4ff5..b1d7ecb9144 100644 --- a/components/esp_mm/esp_cache_utils.c +++ b/components/esp_mm/esp_cache_utils.c @@ -22,8 +22,6 @@ #include "riscv/rv_utils.h" #endif -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - void esp_cache_suspend_ext_mem_cache(void) { #if (CONFIG_SPIRAM && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) diff --git a/components/esp_mm/esp_mmu_map.c b/components/esp_mm/esp_mmu_map.c index f1645facf86..b24ce911da3 100644 --- a/components/esp_mm/esp_mmu_map.c +++ b/components/esp_mm/esp_mmu_map.c @@ -31,11 +31,7 @@ #include "esp_private/esp_mmu_map_private.h" #include "ext_mem_layout.h" #include "esp_mmu_map.h" - -//This is for size align -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -//This is for vaddr align -#define ALIGN_DOWN_BY(num, align) ((num) & (~((align) - 1))) +#include "esp_macros.h" //This flag indicates the memory region is merged, we don't care about it anymore #define MEM_REGION_MERGED -1 @@ -145,8 +141,8 @@ static void s_reserve_irom_region(mem_region_t *hw_mem_regions, int region_nums) size_t irom_len_to_reserve = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start; assert((mmu_ll_vaddr_to_laddr((uint32_t)&_instruction_reserved_end) - mmu_ll_vaddr_to_laddr((uint32_t)&_instruction_reserved_start)) == irom_len_to_reserve); - irom_len_to_reserve += (uint32_t)&_instruction_reserved_start - ALIGN_DOWN_BY((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE); - irom_len_to_reserve = ALIGN_UP_BY(irom_len_to_reserve, CONFIG_MMU_PAGE_SIZE); + irom_len_to_reserve += (uint32_t)&_instruction_reserved_start - ESP_ALIGN_DOWN((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE); + irom_len_to_reserve = ESP_ALIGN_UP(irom_len_to_reserve, CONFIG_MMU_PAGE_SIZE); cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_instruction_reserved_start, irom_len_to_reserve); for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { @@ -173,8 +169,8 @@ static void s_reserve_drom_region(mem_region_t *hw_mem_regions, int region_nums) size_t drom_len_to_reserve = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start; assert((mmu_ll_vaddr_to_laddr((uint32_t)&_rodata_reserved_end) - mmu_ll_vaddr_to_laddr((uint32_t)&_rodata_reserved_start)) == drom_len_to_reserve); - drom_len_to_reserve += (uint32_t)&_rodata_reserved_start - ALIGN_DOWN_BY((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE); - drom_len_to_reserve = ALIGN_UP_BY(drom_len_to_reserve, CONFIG_MMU_PAGE_SIZE); + drom_len_to_reserve += (uint32_t)&_rodata_reserved_start - ESP_ALIGN_DOWN((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE); + drom_len_to_reserve = ESP_ALIGN_UP(drom_len_to_reserve, CONFIG_MMU_PAGE_SIZE); cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_rodata_reserved_start, drom_len_to_reserve); for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { @@ -357,7 +353,7 @@ esp_err_t esp_mmu_map_reserve_block_with_caps(size_t size, mmu_mem_caps_t caps, ESP_RETURN_ON_FALSE(out_ptr, ESP_ERR_INVALID_ARG, TAG, "null pointer"); ESP_RETURN_ON_ERROR(s_mem_caps_check(caps), TAG, "invalid caps"); - size_t aligned_size = ALIGN_UP_BY(size, CONFIG_MMU_PAGE_SIZE); + size_t aligned_size = ESP_ALIGN_UP(size, CONFIG_MMU_PAGE_SIZE); uint32_t laddr = 0; int32_t found_region_id = s_find_available_region(s_mmu_ctx.mem_regions, s_mmu_ctx.num_regions, 0, aligned_size, caps, target); @@ -517,7 +513,7 @@ esp_err_t esp_mmu_map_virt(esp_vaddr_t vaddr_start, esp_paddr_t paddr_start, siz _lock_acquire(&s_mmu_ctx.mutex); mem_block_t *dummy_head = NULL; mem_block_t *dummy_tail = NULL; - size_t aligned_size = ALIGN_UP_BY(size, CONFIG_MMU_PAGE_SIZE); + size_t aligned_size = ESP_ALIGN_UP(size, CONFIG_MMU_PAGE_SIZE); int32_t found_region_id = s_find_available_region(s_mmu_ctx.mem_regions, s_mmu_ctx.num_regions, vaddr_start, aligned_size, caps, target); ESP_GOTO_ON_FALSE(found_region_id != -1, ESP_ERR_NOT_FOUND, err, TAG, "no such vaddr range"); diff --git a/components/esp_mm/test_apps/mm/main/test_mmap.c b/components/esp_mm/test_apps/mm/main/test_mmap.c index 65b625ac0d2..825ade01fee 100644 --- a/components/esp_mm/test_apps/mm/main/test_mmap.c +++ b/components/esp_mm/test_apps/mm/main/test_mmap.c @@ -16,12 +16,12 @@ #include "unity.h" #include "esp_heap_caps.h" #include "esp_partition.h" +#include "esp_macros.h" #include "esp_mmu_map.h" #include "esp_rom_sys.h" #define TEST_BLOCK_SIZE CONFIG_MMU_PAGE_SIZE -#define ALIGN_DOWN(num, align) (((uint32_t)num) & ~((align) - 1)) const static char *TAG = "MMU_TEST"; @@ -85,7 +85,7 @@ TEST_CASE("Cannot map partition to a reserved addresses", "[mmu]") /* Map in the address space of the flash ROM area, should fail */ void *ptr0 = NULL; extern uint8_t _flash_rodata_start[]; - const esp_vaddr_t addr = ALIGN_DOWN(_flash_rodata_start, CONFIG_MMU_PAGE_SIZE); + const esp_vaddr_t addr = ESP_ALIGN_DOWN((uint32_t)_flash_rodata_start, CONFIG_MMU_PAGE_SIZE); esp_err_t err = esp_mmu_map_virt(addr, part->address, TEST_BLOCK_SIZE, MMU_TARGET_FLASH0, MMU_MEM_CAP_READ, 0, &ptr0); TEST_ESP_ERR(ESP_ERR_INVALID_ARG, err); } diff --git a/components/esp_partition/partition.c b/components/esp_partition/partition.c index b3dc33bf392..1a930292f49 100644 --- a/components/esp_partition/partition.c +++ b/components/esp_partition/partition.c @@ -32,6 +32,7 @@ #include "esp_log.h" #include "esp_rom_md5.h" #include "bootloader_util.h" +#include "esp_macros.h" #include "hal/efuse_hal.h" #if CONFIG_IDF_TARGET_LINUX @@ -50,8 +51,6 @@ #define INVARIANTS #endif -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - typedef struct partition_list_item_ { esp_partition_t info; bool user_registered; @@ -592,7 +591,7 @@ esp_err_t esp_partition_copy(const esp_partition_t* dest_part, uint32_t dest_off return ESP_ERR_INVALID_SIZE; } - esp_err_t error = esp_partition_erase_range(dest_part, dest_offset, ALIGN_UP(dest_erase_size, SPI_FLASH_SEC_SIZE)); + esp_err_t error = esp_partition_erase_range(dest_part, dest_offset, ESP_ALIGN_UP(dest_erase_size, SPI_FLASH_SEC_SIZE)); if (error) { ESP_LOGE(TAG, "Erasing destination partition range failed (err=0x%x)", error); return error; diff --git a/components/esp_psram/system_layer/esp_psram.c b/components/esp_psram/system_layer/esp_psram.c index 926631e97c0..e511fb6b05d 100644 --- a/components/esp_psram/system_layer/esp_psram.c +++ b/components/esp_psram/system_layer/esp_psram.c @@ -87,8 +87,6 @@ extern uint8_t _ext_ram_noinit_start; extern uint8_t _ext_ram_noinit_end; #endif //#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - typedef struct { intptr_t vaddr_start; intptr_t vaddr_end; diff --git a/components/esp_psram/xip_impl/mmu_psram_flash.c b/components/esp_psram/xip_impl/mmu_psram_flash.c index 256cbef6bc0..69e427067bb 100644 --- a/components/esp_psram/xip_impl/mmu_psram_flash.c +++ b/components/esp_psram/xip_impl/mmu_psram_flash.c @@ -21,6 +21,7 @@ #include "sdkconfig.h" #include "esp_log.h" #include "esp_attr.h" +#include "esp_macros.h" #include "soc/ext_mem_defs.h" #include "hal/cache_types.h" #include "hal/cache_ll.h" @@ -32,9 +33,6 @@ #include "esp32s3/rom/cache.h" #endif -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#define ALIGN_DOWN_BY(num, align) ((num) & (~((align) - 1))) - /*---------------------------------------------------------------------------- Part 1 APIs (See @Backgrounds on top of this file) -------------------------------------------------------------------------------*/ @@ -61,8 +59,8 @@ extern char _rodata_reserved_end; #endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS -#define INSTRUCTION_ALIGNMENT_GAP_START ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, 4) -#define INSTRUCTION_ALIGNMENT_GAP_END ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE) +#define INSTRUCTION_ALIGNMENT_GAP_START ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, 4) +#define INSTRUCTION_ALIGNMENT_GAP_END ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE) size_t mmu_psram_get_text_segment_length(void) { @@ -79,14 +77,14 @@ size_t mmu_psram_get_text_segment_length(void) void mmu_psram_get_instruction_alignment_gap_info(uint32_t *gap_start, uint32_t *gap_end) { // As we need the memory to start with word aligned address, max virtual space that could be wasted = 3 bytes - // Or create a new region from (uint32_t)&_instruction_reserved_end to ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, 4) as only byte-accessible + // Or create a new region from (uint32_t)&_instruction_reserved_end to ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, 4) as only byte-accessible *gap_start = INSTRUCTION_ALIGNMENT_GAP_START; *gap_end = INSTRUCTION_ALIGNMENT_GAP_END; } bool mmu_psram_check_ptr_addr_in_xip_psram_instruction_region(const void *p) { - if ((intptr_t)p >= ALIGN_DOWN_BY((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE) && (intptr_t)p < ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE)) { + if ((intptr_t)p >= ESP_ALIGN_DOWN((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE) && (intptr_t)p < ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE)) { return true; } @@ -130,8 +128,8 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size #endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS #if CONFIG_SPIRAM_RODATA -#define RODATA_ALIGNMENT_GAP_START ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, 4) -#define RODATA_ALIGNMENT_GAP_END ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE) +#define RODATA_ALIGNMENT_GAP_START ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, 4) +#define RODATA_ALIGNMENT_GAP_END ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE) size_t mmu_psram_get_rodata_segment_length(void) { @@ -150,14 +148,14 @@ size_t mmu_psram_get_rodata_segment_length(void) void mmu_psram_get_rodata_alignment_gap_info(uint32_t *gap_start, uint32_t *gap_end) { // As we need the memory to start with word aligned address, max virtual space that could be wasted = 3 bytes - // Or create a new region from (uint32_t)&_rodata_reserved_end to ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, 4) as only byte-accessible + // Or create a new region from (uint32_t)&_rodata_reserved_end to ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, 4) as only byte-accessible *gap_start = RODATA_ALIGNMENT_GAP_START; *gap_end = RODATA_ALIGNMENT_GAP_END; } bool mmu_psram_check_ptr_addr_in_xip_psram_rodata_region(const void *p) { - if ((intptr_t)p >= ALIGN_DOWN_BY((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE) && (intptr_t)p < ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE)) { + if ((intptr_t)p >= ESP_ALIGN_DOWN((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE) && (intptr_t)p < ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE)) { return true; } diff --git a/components/esp_psram/xip_impl/mmu_psram_flash_v2.c b/components/esp_psram/xip_impl/mmu_psram_flash_v2.c index 2ce08c853b5..db9e6038d4f 100644 --- a/components/esp_psram/xip_impl/mmu_psram_flash_v2.c +++ b/components/esp_psram/xip_impl/mmu_psram_flash_v2.c @@ -25,9 +25,7 @@ #include "esp_mmu_map.h" #include "esp_heap_caps.h" #include "esp_private/image_process.h" - -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#define ALIGN_DOWN_BY(num, align) ((num) & (~((align) - 1))) +#include "esp_macros.h" /** * If using `int`, then for CLANG, with enabled optimization when inlined function is provided with the address of external symbol, the two least bits of the constant used inside that function get cleared. @@ -102,7 +100,7 @@ static uint32_t s_do_load_from_flash(uint32_t flash_paddr_start, uint32_t size, } ESP_EARLY_LOGV(TAG, "mapped_size: 0x%"PRIx32, mapped_size); - assert(mapped_size == ALIGN_UP_BY(size, CONFIG_MMU_PAGE_SIZE)); + assert(mapped_size == ESP_ALIGN_UP(size, CONFIG_MMU_PAGE_SIZE)); return mapped_size; } @@ -110,26 +108,26 @@ static uint32_t s_do_load_from_flash(uint32_t flash_paddr_start, uint32_t size, #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS /* As heap memory is allocated in 4-byte aligned manner, we need to align the instruction to 4-byte boundary */ -#define INSTRUCTION_ALIGNMENT_GAP_START ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, 4) +#define INSTRUCTION_ALIGNMENT_GAP_START ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, 4) /* The end of the instruction is aligned to CONFIG_MMU_PAGE_SIZE boundary as the flash instruction is mapped to PSRAM */ -#define INSTRUCTION_ALIGNMENT_GAP_END ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE) +#define INSTRUCTION_ALIGNMENT_GAP_END ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE) size_t mmu_psram_get_text_segment_length(void) { - return ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE) - ALIGN_DOWN_BY((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE); + return ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE) - ESP_ALIGN_DOWN((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE); } void mmu_psram_get_instruction_alignment_gap_info(uint32_t *gap_start, uint32_t *gap_end) { // As we need the memory to start with word aligned address, max virtual space that could be wasted = 3 bytes - // Or create a new region from (uint32_t)&_instruction_reserved_end to ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, 4) as only byte-accessible + // Or create a new region from (uint32_t)&_instruction_reserved_end to ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, 4) as only byte-accessible *gap_start = INSTRUCTION_ALIGNMENT_GAP_START; *gap_end = INSTRUCTION_ALIGNMENT_GAP_END; } bool mmu_psram_check_ptr_addr_in_xip_psram_instruction_region(const void *p) { - if ((intptr_t)p >= ALIGN_DOWN_BY((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE) && (intptr_t)p < ALIGN_UP_BY((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE)) { + if ((intptr_t)p >= ESP_ALIGN_DOWN((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE) && (intptr_t)p < ESP_ALIGN_UP((uint32_t)&_instruction_reserved_end, CONFIG_MMU_PAGE_SIZE)) { return true; } @@ -143,7 +141,7 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size uint32_t flash_drom_paddr_start = 0; uint32_t flash_irom_paddr_start = 0; image_process_get_flash_segments_info(&flash_drom_paddr_start, &flash_irom_paddr_start); - flash_irom_paddr_start = ALIGN_DOWN_BY(flash_irom_paddr_start, CONFIG_MMU_PAGE_SIZE); + flash_irom_paddr_start = ESP_ALIGN_DOWN(flash_irom_paddr_start, CONFIG_MMU_PAGE_SIZE); ESP_EARLY_LOGV(TAG, "flash_irom_paddr_start: 0x%x", flash_irom_paddr_start); if ((MMU_PAGE_TO_BYTES(start_page) + s_irom_size) > psram_size) { @@ -151,7 +149,7 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size return ESP_ERR_NO_MEM; } - uint32_t irom_load_addr_aligned = ALIGN_DOWN_BY((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE); + uint32_t irom_load_addr_aligned = ESP_ALIGN_DOWN((uint32_t)&_instruction_reserved_start, CONFIG_MMU_PAGE_SIZE); s_irom_paddr_offset = flash_irom_paddr_start - MMU_PAGE_TO_BYTES(start_page); s_irom_vaddr_start = irom_load_addr_aligned; ESP_EARLY_LOGV(TAG, "flash_irom_paddr_start: 0x%"PRIx32", MMU_PAGE_TO_BYTES(start_page): 0x%"PRIx32", s_irom_paddr_offset: 0x%"PRIx32", s_irom_vaddr_start: 0x%"PRIx32, flash_irom_paddr_start, MMU_PAGE_TO_BYTES(start_page), s_irom_paddr_offset, s_irom_vaddr_start); @@ -173,25 +171,25 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size size_t mmu_psram_get_rodata_segment_length(void) { - return ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE) - ALIGN_DOWN_BY((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE); + return ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE) - ESP_ALIGN_DOWN((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE); } /* As heap memory is allocated in 4-byte aligned manner, we need to align the rodata to 4-byte boundary */ -#define RODATA_ALIGNMENT_GAP_START ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, 4) +#define RODATA_ALIGNMENT_GAP_START ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, 4) /* The end of the rodata is aligned to CONFIG_MMU_PAGE_SIZE boundary as the flash rodata is mapped to PSRAM */ -#define RODATA_ALIGNMENT_GAP_END ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE) +#define RODATA_ALIGNMENT_GAP_END ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE) void mmu_psram_get_rodata_alignment_gap_info(uint32_t *gap_start, uint32_t *gap_end) { // As we need the memory to start with word aligned address, max virtual space that could be wasted = 3 bytes - // Or create a new region from (uint32_t)&_rodata_reserved_end to ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, 4) as only byte-accessible + // Or create a new region from (uint32_t)&_rodata_reserved_end to ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, 4) as only byte-accessible *gap_start = RODATA_ALIGNMENT_GAP_START; *gap_end = RODATA_ALIGNMENT_GAP_END; } bool mmu_psram_check_ptr_addr_in_xip_psram_rodata_region(const void *p) { - if ((intptr_t)p >= ALIGN_DOWN_BY((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE) && (intptr_t)p < ALIGN_UP_BY((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE)) { + if ((intptr_t)p >= ESP_ALIGN_DOWN((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE) && (intptr_t)p < ESP_ALIGN_UP((uint32_t)&_rodata_reserved_end, CONFIG_MMU_PAGE_SIZE)) { return true; } @@ -205,7 +203,7 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si uint32_t flash_drom_paddr_start = 0; uint32_t flash_irom_paddr_start = 0; image_process_get_flash_segments_info(&flash_drom_paddr_start, &flash_irom_paddr_start); - flash_drom_paddr_start = ALIGN_DOWN_BY(flash_drom_paddr_start, CONFIG_MMU_PAGE_SIZE); + flash_drom_paddr_start = ESP_ALIGN_DOWN(flash_drom_paddr_start, CONFIG_MMU_PAGE_SIZE); ESP_EARLY_LOGV(TAG, "flash_drom_paddr_start: 0x%x", flash_drom_paddr_start); if ((MMU_PAGE_TO_BYTES(start_page) + s_drom_size) > psram_size) { @@ -213,7 +211,7 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si return ESP_ERR_NO_MEM; } - uint32_t drom_load_addr_aligned = ALIGN_DOWN_BY((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE); + uint32_t drom_load_addr_aligned = ESP_ALIGN_DOWN((uint32_t)&_rodata_reserved_start, CONFIG_MMU_PAGE_SIZE); s_drom_paddr_offset = flash_drom_paddr_start - MMU_PAGE_TO_BYTES(start_page); s_drom_vaddr_start = drom_load_addr_aligned; ESP_EARLY_LOGV(TAG, "flash_drom_paddr_start: 0x%"PRIx32", MMU_PAGE_TO_BYTES(start_page): 0x%"PRIx32", s_drom_paddr_offset: 0x%"PRIx32", s_drom_vaddr_start: 0x%"PRIx32, flash_drom_paddr_start, MMU_PAGE_TO_BYTES(start_page), s_drom_paddr_offset, s_drom_vaddr_start); diff --git a/components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c b/components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c index 34e4bd11dde..d18bc61abd6 100644 --- a/components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c +++ b/components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c @@ -10,13 +10,11 @@ #include "esp_rom_caps.h" #include "soc/extmem_reg.h" #include "xtensa/xtruntime.h" +#include "esp_macros.h" #if CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/cache.h" #endif -#define ALIGN_UP(addr, align) (((addr) + (align)-1) & ~((align)-1)) -#define ALIGN_DOWN(addr, align) ((addr) & ~((align) - 1)) - // this api is renamed for patch extern uint32_t rom_Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped) @@ -115,7 +113,7 @@ int Cache_WriteBack_Addr(uint32_t addr, uint32_t size) /*the start address is unaligned*/ if (start & (dcache_line_size -1)) { - addr = ALIGN_UP(start, dcache_line_size); + addr = ESP_ALIGN_UP(start, dcache_line_size); start_len = addr - start; size = (size < start_len) ? 0 : (size - start_len); @@ -131,7 +129,7 @@ int Cache_WriteBack_Addr(uint32_t addr, uint32_t size) /*the end address is unaligned*/ if (end & (dcache_line_size -1)) { - end = ALIGN_DOWN(end, dcache_line_size); + end = ESP_ALIGN_DOWN(end, dcache_line_size); end_len = addr + size - end; size = (size - end_len); diff --git a/components/esp_system/port/arch/riscv/expression_with_stack.c b/components/esp_system/port/arch/riscv/expression_with_stack.c index 1e4001a6af7..34999351225 100644 --- a/components/esp_system/port/arch/riscv/expression_with_stack.c +++ b/components/esp_system/port/arch/riscv/expression_with_stack.c @@ -4,11 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -#include #include +#include "esp_expression_with_stack.h" +#include "riscv/rvruntime-frames.h" #include "freertos/FreeRTOS.h" #include "freertos/portmacro.h" +#include "esp_macros.h" #include "sdkconfig.h" #if CONFIG_ESP_SYSTEM_HW_STACK_GUARD #include "esp_private/hw_stack_guard.h" @@ -21,7 +22,7 @@ static StackType_t *esp_shared_stack_setup_context(StaticTask_t *tcb, void **sp_ memset(stack, 0xa5U, stack_size * sizeof(StackType_t)); //Align stack to a 16-byte boundary, as required by CPU specific: - StackType_t *top_of_stack = (StackType_t *) ALIGNUP(0x10, (uint32_t)(stack + stack_size)); + StackType_t *top_of_stack = (StackType_t *) ESP_ALIGN_UP((uint32_t)(stack + stack_size), 0x10); StackType_t *adjusted_top_of_stack = top_of_stack - RV_STK_FRMSZ; //Then put the fake stack inside of TCB: diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c index 4246b0c7c6a..e518e326ff2 100644 --- a/components/esp_system/port/soc/esp32c5/system_internal.c +++ b/components/esp_system/port/soc/esp32c5/system_internal.c @@ -31,7 +31,6 @@ #include "esp_private/cache_err_int.h" #include "esp_memory_utils.h" -#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) extern int _bss_end; #include "esp32c5/rom/cache.h" @@ -168,7 +167,7 @@ void esp_restart_noos(void) // If stack is in external RAM (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM), switch SP to // internal RAM before disabling the cache to avoid a "Cache disabled but cached memory // region accessed" crash. - uint32_t new_sp = ALIGN_DOWN((uint32_t)&_bss_end, 16); + uint32_t new_sp = ESP_ALIGN_DOWN((uint32_t)&_bss_end, 16); rv_utils_set_sp((void *)new_sp); } #endif diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c index 1dbf60ddccd..8a291b2569d 100644 --- a/components/esp_system/port/soc/esp32c61/system_internal.c +++ b/components/esp_system/port/soc/esp32c61/system_internal.c @@ -28,7 +28,6 @@ #include "esp_private/cache_err_int.h" #include "esp_memory_utils.h" -#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) extern int _bss_end; #if SOC_MODEM_CLOCK_SUPPORTED @@ -160,7 +159,7 @@ void esp_restart_noos(void) // If stack is in external RAM (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM), switch SP to // internal RAM before disabling the cache to avoid a "Cache disabled but cached memory // region accessed" crash. - uint32_t new_sp = ALIGN_DOWN((uint32_t)&_bss_end, 16); + uint32_t new_sp = ESP_ALIGN_DOWN((uint32_t)&_bss_end, 16); rv_utils_set_sp((void *)new_sp); } #endif diff --git a/components/esp_system/port/soc/esp32h4/system_internal.c b/components/esp_system/port/soc/esp32h4/system_internal.c index c54e140e1e6..d70c69deae8 100644 --- a/components/esp_system/port/soc/esp32h4/system_internal.c +++ b/components/esp_system/port/soc/esp32h4/system_internal.c @@ -26,7 +26,6 @@ #include "hal/uart_ll.h" #include "esp_memory_utils.h" -#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) extern int _bss_end; #include "esp32h4/rom/cache.h" @@ -178,7 +177,7 @@ void esp_restart_noos(void) // If stack is in external RAM (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM), switch SP to // internal RAM before disabling the cache to avoid a "Cache disabled but cached memory // region accessed" crash. - uint32_t new_sp = ALIGN_DOWN((uint32_t)&_bss_end, 16); + uint32_t new_sp = ESP_ALIGN_DOWN((uint32_t)&_bss_end, 16); rv_utils_set_sp((void *)new_sp); } #endif diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index a310fa296c7..2c713248a01 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -39,7 +39,6 @@ #include "hal/efuse_hal.h" #include "esp_memory_utils.h" -#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) extern int _bss_end; void esp_system_reset_modules_on_exit(void) @@ -252,7 +251,7 @@ void esp_restart_noos(void) // If stack is in external RAM (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM), switch SP to // internal RAM before disabling the cache to avoid a "Cache disabled but cached memory // region accessed" crash. - uint32_t new_sp = ALIGN_DOWN((uint32_t)&_bss_end, 16); + uint32_t new_sp = ESP_ALIGN_DOWN((uint32_t)&_bss_end, 16); rv_utils_set_sp((void *)new_sp); } #endif diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c index 8ff900bf8cc..ffdebdffea3 100644 --- a/components/esp_system/port/soc/esp32s2/system_internal.c +++ b/components/esp_system/port/soc/esp32s2/system_internal.c @@ -29,8 +29,6 @@ #include "esp32s2/rom/rtc.h" -#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) - extern int _bss_end; void esp_system_reset_modules_on_exit(void) @@ -104,7 +102,7 @@ void esp_restart_noos(void) // If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used) // then need to switch SP to Internal Memory otherwise // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable. - uint32_t new_sp = ALIGN_DOWN((uint32_t)&_bss_end, 16); + uint32_t new_sp = ESP_ALIGN_DOWN((uint32_t)&_bss_end, 16); SET_STACK(new_sp); } #endif diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c index 31c7a0e64a6..97efd51cc9c 100644 --- a/components/esp_system/port/soc/esp32s3/system_internal.c +++ b/components/esp_system/port/soc/esp32s3/system_internal.c @@ -30,8 +30,6 @@ #include "esp32s3/rom/cache.h" #include "esp32s3/rom/rtc.h" -#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) - extern int _bss_end; void esp_system_reset_modules_on_exit(void) @@ -108,7 +106,7 @@ void esp_restart_noos(void) // If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used) // then need to switch SP to Internal Memory otherwise // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable. - uint32_t new_sp = ALIGN_DOWN((uint32_t)&_bss_end, 16); + uint32_t new_sp = ESP_ALIGN_DOWN((uint32_t)&_bss_end, 16); SET_STACK(new_sp); } #endif diff --git a/components/esp_system/port/soc/esp32s31/system_internal.c b/components/esp_system/port/soc/esp32s31/system_internal.c index 2da0d2b1275..deca93027e9 100644 --- a/components/esp_system/port/soc/esp32s31/system_internal.c +++ b/components/esp_system/port/soc/esp32s31/system_internal.c @@ -28,7 +28,6 @@ #include "hal/uart_ll.h" #include "esp_memory_utils.h" -#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) extern int _bss_end; #include "esp32s31/rom/cache.h" @@ -147,7 +146,7 @@ void esp_restart_noos(void) // If stack is in external RAM (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM), switch SP to // internal RAM before disabling the cache to avoid a "Cache disabled but cached memory // region accessed" crash. - uint32_t new_sp = ALIGN_DOWN((uint32_t)&_bss_end, 16); + uint32_t new_sp = ESP_ALIGN_DOWN((uint32_t)&_bss_end, 16); rv_utils_set_sp((void *)new_sp); } #endif diff --git a/components/esp_tee/subproject/components/attestation/esp_att_utils_part_info.c b/components/esp_tee/subproject/components/attestation/esp_att_utils_part_info.c index c6aff792ef5..e83cc6dc6dd 100644 --- a/components/esp_tee/subproject/components/attestation/esp_att_utils_part_info.c +++ b/components/esp_tee/subproject/components/attestation/esp_att_utils_part_info.c @@ -41,9 +41,9 @@ #include "psa/crypto.h" #include "bootloader_flash_priv.h" #include "esp_attestation_utils.h" +#include "esp_macros.h" #define SECURE_BOOT_V2 (0x02) -#define ALIGN_UP(num, align) (((num) + ((align)-1)) & ~((align)-1)) static const char *TAG = "esp_att_utils"; @@ -305,7 +305,7 @@ static esp_err_t get_part_digest(const esp_partition_pos_t *pos, esp_att_part_di memcpy(part_digest->calc_digest, digest, digest_len); #if CONFIG_SECURE_BOOT_V2_ENABLED - uint32_t signed_image_len = ALIGN_UP(metadata.image_len, FLASH_SECTOR_SIZE); + uint32_t signed_image_len = ESP_ALIGN_UP(metadata.image_len, FLASH_SECTOR_SIZE); if (signed_image_len % CONFIG_MMU_PAGE_SIZE == 0) { part_digest->secure_padding = true; diff --git a/components/esp_tee/subproject/components/tee_flash_mgr/esp_tee_flash.c b/components/esp_tee/subproject/components/tee_flash_mgr/esp_tee_flash.c index f6badae0c1b..8d874066404 100644 --- a/components/esp_tee/subproject/components/tee_flash_mgr/esp_tee_flash.c +++ b/components/esp_tee/subproject/components/tee_flash_mgr/esp_tee_flash.c @@ -17,8 +17,7 @@ #include "esp_tee.h" #include "esp_tee_flash.h" #include "sdkconfig.h" - -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#include "esp_macros.h" static const char *TAG = "esp_tee_flash"; @@ -258,7 +257,7 @@ bool esp_tee_flash_check_prange_write_protected(const size_t paddr, const size_t } const size_t ptb_start = CONFIG_PARTITION_TABLE_OFFSET; - const size_t ptb_end = ALIGN_UP(CONFIG_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_MAX_LEN, FLASH_SECTOR_SIZE); + const size_t ptb_end = ESP_ALIGN_UP(CONFIG_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_MAX_LEN, FLASH_SECTOR_SIZE); bool ptb_overlap = (paddr_start < ptb_end) && (paddr_end > ptb_start); /* Bootloader: write-protected unless dangerous writes are explicitly allowed. */ diff --git a/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_ota.c b/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_ota.c index 5e305af3839..7dc27c5846a 100644 --- a/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_ota.c +++ b/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_ota.c @@ -15,13 +15,12 @@ #include "esp_tee.h" #include "secure_service_num.h" +#include "esp_macros.h" #define TEE_IMG_SRC_PART_SUBTYPE (ESP_PARTITION_SUBTYPE_APP_OTA_1) #define OTA_BUF_SIZE (512) #define FLASH_SECTOR_SIZE (4096) -#define ALIGN_UP(num, align) (((num) + ((align)-1)) & ~((align)-1)) -#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) static const char *TAG = "test_esp_tee_ota"; @@ -81,7 +80,7 @@ static uint32_t copy_tee_update(void) uint32_t tee_next_img_len = tee_next_metadata.image_len; #if CONFIG_SECURE_BOOT_V2_ENABLED - tee_next_img_len = ALIGN_UP(tee_next_img_len, FLASH_SECTOR_SIZE) + FLASH_SECTOR_SIZE; + tee_next_img_len = ESP_ALIGN_UP(tee_next_img_len, FLASH_SECTOR_SIZE) + FLASH_SECTOR_SIZE; #endif uint32_t curr_write_offset = 0; diff --git a/components/espcoredump/src/core_dump_elf.c b/components/espcoredump/src/core_dump_elf.c index 98544ea2b43..1fc18439a9b 100644 --- a/components/espcoredump/src/core_dump_elf.c +++ b/components/espcoredump/src/core_dump_elf.c @@ -18,6 +18,7 @@ #include // for the MIN macro #include "esp_app_desc.h" #include "esp_memory_utils.h" +#include "esp_macros.h" #define ELF_CLASS ELFCLASS32 @@ -89,11 +90,6 @@ typedef struct { // Represents lightweight implementation to save core dump data into ELF formatted binary -#ifdef ALIGN_UP -#undef ALIGN_UP -#endif -#define ALIGN_UP(x, a) (((x) + (a) - 1) & ~((a) - 1)) - // Builds elf header and check all data offsets static int elf_write_file_header(core_dump_elf_t *self, uint32_t seg_count) { @@ -157,7 +153,7 @@ static int elf_add_segment(core_dump_elf_t *self, { esp_err_t err = ESP_FAIL; elf_phdr seg_hdr = { 0 }; - int data_len = ALIGN_UP(data_sz, 4); + int data_len = ESP_ALIGN_UP(data_sz, 4); ELF_CHECK_ERR((data != NULL), ELF_PROC_ERR_OTHER, "Invalid data for segment."); @@ -219,7 +215,7 @@ static int elf_write_note_header(core_dump_elf_t *self, const char* name, uint32 ELF_CHECK_ERR((err == ESP_OK), ELF_PROC_ERR_WRITE_FAIL, "Write ELF note header failure (%d)", err); // write note name - err = esp_core_dump_write_data(&self->write_data, name_buffer, ALIGN_UP(note_hdr.n_namesz, 4)); + err = esp_core_dump_write_data(&self->write_data, name_buffer, ESP_ALIGN_UP(note_hdr.n_namesz, 4)); ELF_CHECK_ERR((err == ESP_OK), ELF_PROC_ERR_WRITE_FAIL, "Write ELF note name failure (%d)", err); @@ -238,7 +234,7 @@ static int elf_write_note(core_dump_elf_t *self, ELF_CHECK_ERR((name_len <= ELF_NOTE_NAME_MAX_SIZE), 0, "Segment note name is too long %d.", name_len); - uint32_t note_size = ALIGN_UP(name_len, 4) + ALIGN_UP(data_sz, 4) + sizeof(elf_note); + uint32_t note_size = ESP_ALIGN_UP(name_len, 4) + ESP_ALIGN_UP(data_sz, 4) + sizeof(elf_note); // write segment data during second pass if (self->elf_stage == ELF_STAGE_PLACE_DATA) { @@ -252,7 +248,7 @@ static int elf_write_note(core_dump_elf_t *self, // which might not be aligned by default. Therefore, we need to verify alignment and add padding if necessary. err = esp_core_dump_write_data(&self->write_data, data, data_sz); if (err == ESP_OK) { - const int pad_size = ALIGN_UP(data_sz, 4) - data_sz; + const int pad_size = ESP_ALIGN_UP(data_sz, 4) - data_sz; if (pad_size > 0) { uint8_t pad_bytes[3] = {0}; ESP_COREDUMP_LOG_PROCESS("Core dump note data needs %d bytes padding", pad_size); @@ -687,7 +683,7 @@ static int elf_add_wdt_panic_details(core_dump_elf_t *self) esp_task_wdt_print_triggered_tasks(elf_write_core_dump_note_cb, ¶m, NULL); ELF_CHECK_ERR((param.total_size > 0), ELF_PROC_ERR_WRITE_FAIL, "Write ELF note data failure (%d)", err); - const int pad_size = ALIGN_UP(self->note_data_size, 4) - self->note_data_size; + const int pad_size = ESP_ALIGN_UP(self->note_data_size, 4) - self->note_data_size; if (pad_size > 0) { uint8_t pad_bytes[3] = {0}; ESP_COREDUMP_LOG_PROCESS("Core dump note needs %d bytes padding", pad_size); @@ -696,7 +692,7 @@ static int elf_add_wdt_panic_details(core_dump_elf_t *self) } } - return ALIGN_UP(name_len, 4) + ALIGN_UP(self->note_data_size, 4) + sizeof(elf_note); + return ESP_ALIGN_UP(name_len, 4) + ESP_ALIGN_UP(self->note_data_size, 4) + sizeof(elf_note); } #endif //CONFIG_ESP_TASK_WDT_EN @@ -966,14 +962,14 @@ static void esp_core_dump_parse_note_section(uint8_t *coredump_data, elf_note_co for (size_t idx = 0; idx < size; ++idx) { if (target_notes[idx].n_type == note->n_type) { char *nm = (char *)¬e[1]; - target_notes[idx].n_ptr = nm + ALIGN_UP(note->n_namesz, 4); + target_notes[idx].n_ptr = nm + ESP_ALIGN_UP(note->n_namesz, 4); target_notes[idx].n_descsz = note->n_descsz; ESP_COREDUMP_LOGD("%d bytes target note (%X) found in the note section", note->n_descsz, note->n_type); break; } } - consumed_note_sz += ALIGN_UP(note->n_namesz, 4) + ALIGN_UP(note->n_descsz, 4) + sizeof(elf_note); + consumed_note_sz += ESP_ALIGN_UP(note->n_namesz, 4) + ESP_ALIGN_UP(note->n_descsz, 4) + sizeof(elf_note); } } } diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c index 44016d4114f..279e18c31c2 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c @@ -33,6 +33,7 @@ #include "port_systick.h" #include "portmacro.h" #include "esp_memory_utils.h" +#include "esp_macros.h" #if CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER #include "esp_timer.h" #endif @@ -351,13 +352,7 @@ void vPortEndScheduler(void) // ------------------------ Stack -------------------------- -/** - * @brief Align stack pointer in a downward growing stack - * - * This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2. - * This macro is generally used when allocating aligned areas on a downward growing stack. - */ -#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1))) + /** * @brief Allocate and initialize GCC TLS area @@ -401,11 +396,11 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, u extern char _thread_local_bss_start, _thread_local_bss_end; const uint32_t tls_data_size = (uint32_t)&_thread_local_data_end - (uint32_t)&_thread_local_data_start; const uint32_t tls_bss_size = (uint32_t)&_thread_local_bss_end - (uint32_t)&_thread_local_bss_start; - const uint32_t tls_area_size = ALIGNUP(16, tls_data_size + tls_bss_size); + const uint32_t tls_area_size = ESP_ALIGN_UP(tls_data_size + tls_bss_size, 16); // TODO: check that TLS area fits the stack // Allocate space for the TLS area on the stack. The area must be aligned to 16-bytes - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - (UBaseType_t)tls_area_size, 16); // Initialize the TLS data with the initialization values of each TLS variable memcpy((void *)uxStackPointer, &_thread_local_data_start, tls_data_size); // Initialize the TLS bss with zeroes @@ -453,7 +448,7 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, - The stack frame must be allocated to a 16-byte aligned address. - We use RV_STK_FRMSZ (instead of sizeof(RvExcFrame)) as it rounds up the total size to a multiple of 16. */ - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - RV_STK_FRMSZ); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - RV_STK_FRMSZ, 16); // Clear the entire interrupt stack frame RvExcFrame *frame = (RvExcFrame *)uxStackPointer; diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c index 695f97c6767..eb594a2ed15 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c @@ -36,6 +36,7 @@ #include "esp_freertos_hooks.h" #include "esp_intr_alloc.h" #include "esp_memory_utils.h" +#include "esp_macros.h" #include /* required for xthal_get_ccount() */ #if CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER #include "esp_timer.h" @@ -49,14 +50,6 @@ _Static_assert(portBYTE_ALIGNMENT == 16, "portBYTE_ALIGNMENT must be set to 16"); -/** - * @brief Align stack pointer in a downward growing stack - * - * This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2. - * This macro is generally used when allocating aligned areas on a downward growing stack. - */ -#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1))) - /* ---------------------------------------------------- Variables ------------------------------------------------------ * - Various variables used to maintain the FreeRTOS port's state. Used from both port.c and various .S files * - Constant offsets are used by assembly to jump to particular TCB members or a stack area (such as the CPSA). We use @@ -310,7 +303,7 @@ static void vPortCleanUpCoprocArea( void *pxTCB ) /* Get pointer to the task's coprocessor save area from TCB->pxEndOfStack. See uxInitialiseStackCPSA() */ uxCoprocArea = ( UBaseType_t ) ( ( ( StaticTask_t * ) pxTCB )->pxDummy8 ); /* Get TCB_t.pxEndOfStack */ - uxCoprocArea = STACKPTR_ALIGN_DOWN(16, uxCoprocArea - XT_CP_SIZE); + uxCoprocArea = ESP_ALIGN_DOWN(uxCoprocArea - XT_CP_SIZE, 16); /* Extract core ID from the affinity mask */ xTargetCoreID = ( ( StaticTask_t * ) pxTCB )->uxDummy26; @@ -447,13 +440,13 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackCPSA(UBaseType_t uxStackPointer) */ // Allocate overall coprocessor save area, aligned down to 16 byte boundary - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_CP_SIZE); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - XT_CP_SIZE, 16); // Initialize the coprocessor context switching flags. uint32_t *p = (uint32_t *)uxStackPointer; p[0] = 0; // Clear XT_CPENABLE and XT_CPSTORED p[1] = 0; // Clear XT_CP_CS_ST // XT_CP_ASA points to the aligned start of the individual CP save areas (i.e., start of CP0 SA) - p[2] = (uint32_t)ALIGNUP(XCHAL_TOTAL_SA_ALIGN, (uint32_t)uxStackPointer + 12); + p[2] = (uint32_t)ESP_ALIGN_UP((uint32_t)uxStackPointer + 12, XCHAL_TOTAL_SA_ALIGN); return uxStackPointer; } #endif /* XCHAL_CP_NUM > 0 */ @@ -503,11 +496,11 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, u extern char _thread_local_bss_start, _thread_local_bss_end; const uint32_t tls_data_size = (uint32_t)&_thread_local_data_end - (uint32_t)&_thread_local_data_start; const uint32_t tls_bss_size = (uint32_t)&_thread_local_bss_end - (uint32_t)&_thread_local_bss_start; - const uint32_t tls_area_size = ALIGNUP(16, tls_data_size + tls_bss_size); + const uint32_t tls_area_size = ESP_ALIGN_UP(tls_data_size + tls_bss_size, 16); // TODO: check that TLS area fits the stack // Allocate space for the TLS area on the stack. The area must be allocated at a 16-byte aligned address - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - (UBaseType_t)tls_area_size, 16); // Initialize the TLS data with the initialization values of each TLS variable memcpy((void *)uxStackPointer, &_thread_local_data_start, tls_data_size); // Initialize the TLS bss with zeroes @@ -540,7 +533,7 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, u */ const uint32_t tls_section_align = (uint32_t)&_tls_section_alignment; // ALIGN value of .flash.tdata section #define TCB_SIZE 8 - const uint32_t base = ALIGNUP(tls_section_align, TCB_SIZE); + const uint32_t base = ESP_ALIGN_UP(TCB_SIZE, tls_section_align); *ret_threadptr_reg_init = (uint32_t)uxStackPointer - base; return uxStackPointer; @@ -587,7 +580,7 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, - rounds up the total size to a multiple of 16 */ UBaseType_t uxStackPointerPrevious = uxStackPointer; - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_STK_FRMSZ); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - XT_STK_FRMSZ, 16); // Clear the entire interrupt stack frame memset((void *)uxStackPointer, 0, (size_t)(uxStackPointerPrevious - uxStackPointer)); diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c index 3dc596098ff..151caa2b9e8 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c @@ -58,6 +58,7 @@ #include "portmacro.h" #include "port_systick.h" #include "esp_memory_utils.h" +#include "esp_macros.h" #if CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER #include "esp_timer.h" #endif @@ -195,13 +196,7 @@ void vPortEndScheduler(void) // ------------------------ Stack -------------------------- -/** - * @brief Align stack pointer in a downward growing stack - * - * This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2. - * This macro is generally used when allocating aligned areas on a downward growing stack. - */ -#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1))) + /** * @brief Allocate and initialize GCC TLS area @@ -245,11 +240,11 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, u extern char _thread_local_bss_start, _thread_local_bss_end; const uint32_t tls_data_size = (uint32_t)&_thread_local_data_end - (uint32_t)&_thread_local_data_start; const uint32_t tls_bss_size = (uint32_t)&_thread_local_bss_end - (uint32_t)&_thread_local_bss_start; - const uint32_t tls_area_size = ALIGNUP(16, tls_data_size + tls_bss_size); + const uint32_t tls_area_size = ESP_ALIGN_UP(tls_data_size + tls_bss_size, 16); // TODO: check that TLS area fits the stack // Allocate space for the TLS area on the stack. The area must be aligned to 16-bytes - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - (UBaseType_t)tls_area_size, 16); // Initialize the TLS data with the initialization values of each TLS variable memcpy((void *)uxStackPointer, &_thread_local_data_start, tls_data_size); // Initialize the TLS bss with zeroes @@ -285,7 +280,7 @@ static void vPortTaskWrapper(TaskFunction_t pxCode, void *pvParameters) */ FORCE_INLINE_ATTR RvCoprocSaveArea* pxRetrieveCoprocSaveAreaFromStackPointer(UBaseType_t pxTopOfStack) { - return (RvCoprocSaveArea*) STACKPTR_ALIGN_DOWN(16, pxTopOfStack - sizeof(RvCoprocSaveArea)); + return (RvCoprocSaveArea*) ESP_ALIGN_DOWN(pxTopOfStack - sizeof(RvCoprocSaveArea), 16); } /** @@ -360,7 +355,7 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, - The stack frame must be allocated to a 16-byte aligned address. - We use RV_STK_FRMSZ as it rounds up the total size to a multiple of 16. */ - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - RV_STK_FRMSZ); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - RV_STK_FRMSZ, 16); // Clear the entire interrupt stack frame RvExcFrame *frame = (RvExcFrame *)uxStackPointer; diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c b/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c index 6a9c4e1f899..ec2be1c6185 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c @@ -55,6 +55,7 @@ #include "esp_timer.h" #endif #include "esp_memory_utils.h" +#include "esp_macros.h" _Static_assert(portBYTE_ALIGNMENT == 16, "portBYTE_ALIGNMENT must be set to 16"); @@ -157,13 +158,7 @@ static void vPortTaskWrapper(TaskFunction_t pxCode, void *pvParameters) } #endif -/** - * @brief Align stack pointer in a downward growing stack - * - * This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2. - * This macro is generally used when allocating aligned areas on a downward growing stack. - */ -#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1))) + #if XCHAL_CP_NUM > 0 /** @@ -198,13 +193,13 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackCPSA(UBaseType_t uxStackPointer) */ // Allocate overall coprocessor save area, aligned down to 16 byte boundary - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_CP_SIZE); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - XT_CP_SIZE, 16); // Initialize the coprocessor context switching flags. uint32_t *p = (uint32_t *)uxStackPointer; p[0] = 0; // Clear XT_CPENABLE and XT_CPSTORED p[1] = 0; // Clear XT_CP_CS_ST // XT_CP_ASA points to the aligned start of the individual CP save areas (i.e., start of CP0 SA) - p[2] = (uint32_t)ALIGNUP(XCHAL_TOTAL_SA_ALIGN, (uint32_t)uxStackPointer + 12); + p[2] = (uint32_t)ESP_ALIGN_UP((uint32_t)uxStackPointer + 12, XCHAL_TOTAL_SA_ALIGN); return uxStackPointer; } #endif /* XCHAL_CP_NUM > 0 */ @@ -254,11 +249,11 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, u extern char _thread_local_bss_start, _thread_local_bss_end; const uint32_t tls_data_size = (uint32_t)&_thread_local_data_end - (uint32_t)&_thread_local_data_start; const uint32_t tls_bss_size = (uint32_t)&_thread_local_bss_end - (uint32_t)&_thread_local_bss_start; - const uint32_t tls_area_size = ALIGNUP(16, tls_data_size + tls_bss_size); + const uint32_t tls_area_size = ESP_ALIGN_UP(tls_data_size + tls_bss_size, 16); // TODO: check that TLS area fits the stack // Allocate space for the TLS area on the stack. The area must be allocated at a 16-byte aligned address - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - (UBaseType_t)tls_area_size, 16); // Initialize the TLS data with the initialization values of each TLS variable memcpy((void *)uxStackPointer, &_thread_local_data_start, tls_data_size); // Initialize the TLS bss with zeroes @@ -291,7 +286,7 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, u */ const uint32_t tls_section_align = (uint32_t)&_tls_section_alignment; // ALIGN value of .flash.tdata section #define TCB_SIZE 8 - const uint32_t base = ALIGNUP(tls_section_align, TCB_SIZE); + const uint32_t base = ESP_ALIGN_UP(TCB_SIZE, tls_section_align); *ret_threadptr_reg_init = (uint32_t)uxStackPointer - base; return uxStackPointer; @@ -338,7 +333,7 @@ FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, - rounds up the total size to a multiple of 16 */ UBaseType_t uxStackPointerPrevious = uxStackPointer; - uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_STK_FRMSZ); + uxStackPointer = ESP_ALIGN_DOWN(uxStackPointer - XT_STK_FRMSZ, 16); // Clear the entire interrupt stack frame memset((void *)uxStackPointer, 0, (size_t)(uxStackPointerPrevious - uxStackPointer)); @@ -671,7 +666,7 @@ static void vPortCleanUpCoprocArea(void *pvTCB) /* Get a pointer to the task's coprocessor save area */ uxCoprocArea = ( UBaseType_t ) ( ( ( StaticTask_t * ) pvTCB )->pxDummy8 ); /* Get TCB_t.pxEndOfStack */ - uxCoprocArea = STACKPTR_ALIGN_DOWN(16, uxCoprocArea - XT_CP_SIZE); + uxCoprocArea = ESP_ALIGN_DOWN(uxCoprocArea - XT_CP_SIZE, 16); #if ( configNUMBER_OF_CORES > 1 ) /* Get xTargetCoreID from the TCB.xCoreID */ diff --git a/components/heap/multi_heap.c b/components/heap/multi_heap.c index bb58882ec06..426eba5ccd1 100644 --- a/components/heap/multi_heap.c +++ b/components/heap/multi_heap.c @@ -78,10 +78,6 @@ void *multi_heap_find_containing_block(multi_heap_handle_t heap, void *ptr) #endif // !CONFIG_HEAP_TLSF_USE_ROM_IMPL #endif // !MULTI_HEAP_POISONING -#define ALIGN(X) ((X) & ~(sizeof(void *)-1)) -#define ALIGN_UP(X) ALIGN((X)+sizeof(void *)-1) -#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - typedef struct multi_heap_info { void *lock; size_t free_bytes; diff --git a/components/heap/multi_heap_poisoning.c b/components/heap/multi_heap_poisoning.c index c171b9f8d1a..53ba9c1db9d 100644 --- a/components/heap/multi_heap_poisoning.c +++ b/components/heap/multi_heap_poisoning.c @@ -47,8 +47,6 @@ #define TAIL_CANARY_PATTERN 0xBAAD5678 -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - typedef struct { uint32_t head_canary; size_t alloc_size; diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c index bc2b2e586dc..330751cb45c 100644 --- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c +++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c @@ -26,6 +26,7 @@ #include "psa/crypto.h" #include "mbedtls/platform_util.h" +#include "esp_macros.h" #if !ESP_TEE_BUILD #include "esp_cache.h" @@ -354,8 +355,6 @@ static inline void dma_desc_append(crypto_dma_desc_t **head, crypto_dma_desc_t * #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) #define AES_DMA_ALLOC_CAPS (MALLOC_CAP_DMA | MALLOC_CAP_8BIT) static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_t *actual_size) @@ -372,8 +371,8 @@ static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_ #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE /* Write back both input buffers and output buffers to clear any cache dirty bit if set */ // Even output buffers are C2M synced here, because, while performing an aligned up M2C operation, - // extra bytes in the cache (len - ALIGN_UP(len)) might get corrupted if not C2M synced before. - ret = esp_cache_msync(dmadesc[i].buffer, ALIGN_UP(dmadesc[i].dw0.length, buffer_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_C2M); + // extra bytes in the cache (len - ESP_ALIGN_UP(len)) might get corrupted if not C2M synced before. + ret = esp_cache_msync(dmadesc[i].buffer, ESP_ALIGN_UP(dmadesc[i].dw0.length, buffer_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_C2M); if (ret != ESP_OK) { return ret; } @@ -435,7 +434,7 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le } /* Extra bytes that were needed to be processed for supplying the AES peripheral a padded multiple of 16 bytes input */ - size_t extra_bytes = ALIGN_UP(len, AES_BLOCK_BYTES) - len; + size_t extra_bytes = ESP_ALIGN_UP(len, AES_BLOCK_BYTES) - len; size_t start_offset = ((intptr_t)buffer & (cache_line_size - 1)); @@ -446,7 +445,7 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le } if (unaligned_start_bytes < len) { - aligned_block_bytes = ALIGN_DOWN((len - unaligned_start_bytes), cache_line_size); + aligned_block_bytes = ESP_ALIGN_DOWN((len - unaligned_start_bytes), cache_line_size); unaligned_end_bytes = len - unaligned_start_bytes - aligned_block_bytes + extra_bytes; } else { unaligned_start_bytes = len + extra_bytes; @@ -454,7 +453,7 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le aligned_block_bytes = 0; } - size_t max_desc_size = (is_output) ? ALIGN_DOWN(DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED, cache_line_size) : ALIGN_DOWN(DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED, cache_line_size); + size_t max_desc_size = (is_output) ? ESP_ALIGN_DOWN(DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED, cache_line_size) : ESP_ALIGN_DOWN(DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED, cache_line_size); dma_descs_needed = (unaligned_start_bytes ? 1 : 0) + dma_desc_get_required_num(aligned_block_bytes, max_desc_size) + (unaligned_end_bytes ? 1 : 0); @@ -666,19 +665,19 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE size_t output_desc_cache_line_size = get_cache_line_size(output_desc); - if (esp_cache_msync(output_desc, ALIGN_UP(output_dma_desc_num * sizeof(crypto_dma_desc_t), output_desc_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) { + if (esp_cache_msync(output_desc, ESP_ALIGN_UP(output_dma_desc_num * sizeof(crypto_dma_desc_t), output_desc_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) { ESP_LOGE(TAG, "Output DMA descriptor cache sync M2C failed"); ret = -1; goto cleanup; } for (int i = 0; i < output_dma_desc_num; i++) { // Align the output buffer to the cache line size before performing the M2C sync, because M2C sync cannot be performed on buffers with unaligned lengths. - // Note: This does not corrupt the extra bytes in the cache (len - ALIGN_UP(len)) because the ESP32-P4 AES driver already performs cache-to-memory (C2M) + // Note: This does not corrupt the extra bytes in the cache (len - ESP_ALIGN_UP(len)) because the ESP32-P4 AES driver already performs cache-to-memory (C2M) // operations on the output buffer using the aligned-up length. // But what if those extra bytes get updated (say by a different process) during the AES operation? Would the updated value be lost/corrupted? // No, because the heap allocator would have already allocated a ALIGNED_UP buffer for the output buffer according to the alignment requirements, // while allocating the output buffer (see esp_heap_adjust_alignment_to_hw()). - if (esp_cache_msync(output_desc[i].buffer, ALIGN_UP(output_desc[i].dw0.length, output_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) { + if (esp_cache_msync(output_desc[i].buffer, ESP_ALIGN_UP(output_desc[i].dw0.length, output_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) { ESP_LOGE(TAG, "Output DMA descriptor buffers cache sync M2C failed"); ret = -1; goto cleanup; @@ -689,7 +688,7 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign aes_hal_transform_dma_finish(); /* Extra bytes that were needed to be processed for supplying the AES peripheral a padded multiple of 16 bytes input */ - size_t extra_bytes = ALIGN_UP(len, AES_BLOCK_BYTES) - len; + size_t extra_bytes = ESP_ALIGN_UP(len, AES_BLOCK_BYTES) - len; if (output_start_alignment) { memcpy(output, output_start_stream_buffer, (output_start_alignment > len) ? len : output_start_alignment); @@ -908,13 +907,13 @@ int esp_aes_process_dma_gcm(esp_aes_context *ctx, const unsigned char *input, un #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE size_t output_desc_cache_line_size = get_cache_line_size(output_desc); - if (esp_cache_msync(output_desc, ALIGN_UP(output_dma_desc_num * sizeof(crypto_dma_desc_t), output_desc_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) { + if (esp_cache_msync(output_desc, ESP_ALIGN_UP(output_dma_desc_num * sizeof(crypto_dma_desc_t), output_desc_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) { ESP_LOGE(TAG, "Output DMA descriptor cache sync M2C failed"); ret = -1; goto cleanup; } for (int i = 0; i < output_dma_desc_num; i++) { - if (esp_cache_msync(output_desc[i].buffer, ALIGN_UP(output_desc[i].dw0.length, output_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) { + if (esp_cache_msync(output_desc[i].buffer, ESP_ALIGN_UP(output_desc[i].dw0.length, output_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) { ESP_LOGE(TAG, "Output DMA descriptor buffers cache sync M2C failed"); ret = -1; goto cleanup; @@ -925,7 +924,7 @@ int esp_aes_process_dma_gcm(esp_aes_context *ctx, const unsigned char *input, un aes_hal_transform_dma_finish(); /* Extra bytes that were needed to be processed for supplying the AES peripheral a padded multiple of 16 bytes input */ - size_t extra_bytes = ALIGN_UP(len, AES_BLOCK_BYTES) - len; + size_t extra_bytes = ESP_ALIGN_UP(len, AES_BLOCK_BYTES) - len; if (output_start_alignment) { memcpy(output, output_start_stream_buffer, (output_start_alignment > len) ? len : output_start_alignment); diff --git a/components/mbedtls/test_apps/mbedtls_ut/main/test_psa_aes.c b/components/mbedtls/test_apps/mbedtls_ut/main/test_psa_aes.c index 448ccf5dd62..2d510f83a55 100644 --- a/components/mbedtls/test_apps/mbedtls_ut/main/test_psa_aes.c +++ b/components/mbedtls/test_apps/mbedtls_ut/main/test_psa_aes.c @@ -19,6 +19,7 @@ #include "test_aes_params.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" +#include "esp_macros.h" #include "freertos/semphr.h" #include "esp_memory_utils.h" #include "soc/lldesc.h" @@ -447,9 +448,8 @@ TEST_CASE("PSA AES-CBC-PKCS7 multipart", "[psa-aes]") TEST_CASE("mbedtls CBC AES-256 DMA buffer align test", "[aes]") { -#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1)) - // Size is taken considering the maximum DMA buffer size - const unsigned SZ = ALIGN_DOWN((2*LLDESC_MAX_NUM_PER_DESC), 16); +// Size is taken considering the maximum DMA buffer size + const unsigned SZ = ESP_ALIGN_DOWN((2*LLDESC_MAX_NUM_PER_DESC), 16); psa_key_id_t key_id; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; psa_cipher_operation_t operation = PSA_CIPHER_OPERATION_INIT; diff --git a/components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c b/components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c index c3779b50208..5482cab5dcd 100644 --- a/components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c +++ b/components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c @@ -9,8 +9,7 @@ #include "soc/soc.h" #include "esp_rom_caps.h" #include "esp_assert.h" - -#define ALIGN_DOWN(SIZE, AL) (SIZE & ~(AL - 1)) +#include "esp_macros.h" /* The last CONFIG_ULP_SHARED_MEM bytes of the reserved memory are reserved for a shared cfg struct The main cpu app and the ulp binary can share variables automatically through the linkerscript generated from @@ -38,6 +37,6 @@ ulp_lp_core_memory_shared_cfg_t* ulp_lp_core_memory_shared_cfg_get(void) /* Ensure the end where the shared memory starts is aligned to 8 bytes if updating this also update the same in ulp_lp_core_riscv.ld */ - return (ulp_lp_core_memory_shared_cfg_t *)(ulp_base_addr + ALIGN_DOWN(CONFIG_ULP_COPROC_RESERVE_MEM, 0x8) - CONFIG_ULP_SHARED_MEM); + return (ulp_lp_core_memory_shared_cfg_t *)(ulp_base_addr + ESP_ALIGN_DOWN(CONFIG_ULP_COPROC_RESERVE_MEM, 0x8) - CONFIG_ULP_SHARED_MEM); #endif } diff --git a/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c b/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c index 38918f0351d..33d49a0b1f6 100644 --- a/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c +++ b/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c @@ -19,6 +19,7 @@ #include "driver/gpio.h" #include "esp_err.h" #include "esp_log.h" +#include "esp_macros.h" #include "lvgl.h" #include "esp_lcd_ili9881c.h" #include "esp_lcd_ek79007.h" @@ -73,9 +74,6 @@ static const char *TAG = "example"; #define EXAMPLE_PIN_NUM_REFRESH_MONITOR 20 // Monitor the Refresh Rate by toggling the GPIO #endif -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////// Please update the following configuration according to your Application /////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -96,8 +94,8 @@ extern void example_lvgl_demo_ui(lv_display_t *disp); void example_rounder_flush_area_cb(lv_event_t * event) { lv_area_t * area = lv_event_get_invalidated_area(event); - area->x1 = ALIGN_DOWN(area->x1, 16); - area->x2 = ALIGN_UP(area->x2, 16) - 1; + area->x1 = ESP_ALIGN_DOWN(area->x1, 16); + area->x2 = ESP_ALIGN_UP(area->x2, 16) - 1; } #endif diff --git a/examples/peripherals/usb/device/cherryusb_serial_device/main/device_cdc_main.c b/examples/peripherals/usb/device/cherryusb_serial_device/main/device_cdc_main.c index 520b62da636..7db07255cfd 100644 --- a/examples/peripherals/usb/device/cherryusb_serial_device/main/device_cdc_main.c +++ b/examples/peripherals/usb/device/cherryusb_serial_device/main/device_cdc_main.c @@ -9,6 +9,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_log.h" +#include "esp_macros.h" #include "usbd_core.h" #include "usbd_cdc_acm.h" @@ -72,12 +73,10 @@ static ep_status_t s_ep_status[CDC_ACM_CHANNEL_NUM] = { #endif }; -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - -#define WRITE_BUFFER_SIZE ALIGN_UP(ALIGN_UP(2048, CDC_MAX_MPS), CONFIG_USB_ALIGN_SIZE) +#define WRITE_BUFFER_SIZE ESP_ALIGN_UP(ESP_ALIGN_UP(2048, CDC_MAX_MPS), CONFIG_USB_ALIGN_SIZE) #if CONFIG_EXAMPLE_CHERRYUSB_SET_READ_BUFFER_SIZE_MPS -#define READ_BUFFER_SIZE ALIGN_UP(CDC_MAX_MPS, CONFIG_USB_ALIGN_SIZE) +#define READ_BUFFER_SIZE ESP_ALIGN_UP(CDC_MAX_MPS, CONFIG_USB_ALIGN_SIZE) #else #define READ_BUFFER_SIZE WRITE_BUFFER_SIZE #endif diff --git a/tools/test_apps/system/panic/common/main/test_memprot.c b/tools/test_apps/system/panic/common/main/test_memprot.c index 420225405d1..618546dc1b1 100644 --- a/tools/test_apps/system/panic/common/main/test_memprot.c +++ b/tools/test_apps/system/panic/common/main/test_memprot.c @@ -11,6 +11,7 @@ #include "esp_err.h" #include "esp_system.h" +#include "esp_macros.h" #include "esp_log.h" #include "soc/soc.h" #include "soc/soc_caps.h" @@ -29,7 +30,7 @@ extern int _iram_start; extern int _iram_text_start; extern int _iram_text_end; -#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1)) +#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) ESP_ALIGN_UP(addr, SOC_MMU_PAGE_SIZE) __attribute__((noinline)) static void run_function(void (*test_addr)(void)) {