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refactor(i2c): cleanup I2C definitions in soc_caps.h

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This commit is contained in:
Chen Chen
2026-01-12 17:07:04 +08:00
parent 1b55ab941a
commit 17d2041821
46 changed files with 340 additions and 586 deletions
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components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
-12
View File
@@ -335,18 +335,6 @@ config SOC_HP_I2C_NUM
int
default 1
config SOC_I2C_FIFO_LEN
int
default 16
config SOC_I2C_CMD_REG_NUM
int
default 8
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
components/soc/esp32c2/include/soc/soc_caps.h
+1 -8
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -151,16 +151,9 @@
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C2 has 1 I2C
#define SOC_I2C_NUM (1U)
#define SOC_HP_I2C_NUM (1U)
#define SOC_I2C_FIFO_LEN (16) /*!< I2C hardware FIFO depth */
#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)