From 17b98b7a294974072cb8bb074eda468d961194c1 Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Thu, 27 Nov 2025 16:13:26 +0530 Subject: [PATCH] feat(esp_tee): Enable GDMA burst mode for AES/SHA operations - Fix the compile-time minimum chip revision check for patching the `ets_delay_us` API Co-authored-by: Harshal Patil --- components/esp_rom/patches/esp_rom_sys.c | 3 ++- .../mbedtls/esp_tee/esp_tee_crypto_shared_gdma.c | 15 +++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c index b645ee06485..02e1265c408 100644 --- a/components/esp_rom/patches/esp_rom_sys.c +++ b/components/esp_rom/patches/esp_rom_sys.c @@ -118,7 +118,8 @@ uint32_t esp_rom_get_bootloader_offset(void) #endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED #if ESP_ROM_DELAY_US_PATCH && CONFIG_SECURE_ENABLE_TEE && !NON_OS_BUILD -#if CONFIG_ESP32C5_REV_MIN_FULL <= 100 || CONFIG_ESP32C61_REV_MIN_FULL <= 100 +#if (CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL <= 100) || \ + (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL <= 100) #include "riscv/rv_utils.h" diff --git a/components/mbedtls/esp_tee/esp_tee_crypto_shared_gdma.c b/components/mbedtls/esp_tee/esp_tee_crypto_shared_gdma.c index 2bc36171703..0a810eaab00 100644 --- a/components/mbedtls/esp_tee/esp_tee_crypto_shared_gdma.c +++ b/components/mbedtls/esp_tee/esp_tee_crypto_shared_gdma.c @@ -6,6 +6,7 @@ #include #include "esp_err.h" +#include "soc/soc_caps.h" #include "esp_crypto_dma.h" @@ -50,6 +51,10 @@ #define dma_ll_rx_stop DMA_LL_FUNC(rx_stop) #define dma_ll_tx_set_priority DMA_LL_FUNC(tx_set_priority) #define dma_ll_rx_set_priority DMA_LL_FUNC(rx_set_priority) +#if SOC_AHB_GDMA_VERSION == 2 +#define dma_ll_tx_set_burst_size DMA_LL_FUNC(tx_set_burst_size) +#define dma_ll_rx_set_burst_size DMA_LL_FUNC(rx_set_burst_size) +#endif /* * NOTE: [ESP-TEE] This is a low-level (LL), non-OS version of @@ -67,10 +72,16 @@ static void crypto_shared_gdma_init(void) dma_ll_force_enable_reg_clock(&DMA_DEV, true); // setting the transfer ability +#if SOC_AHB_GDMA_VERSION == 2 + dma_ll_rx_enable_data_burst(&DMA_DEV, TEE_CRYPTO_GDMA_CH, true); + dma_ll_rx_set_burst_size(&DMA_DEV, TEE_CRYPTO_GDMA_CH, 16); + dma_ll_tx_set_burst_size(&DMA_DEV, TEE_CRYPTO_GDMA_CH, 16); +#else + dma_ll_rx_enable_data_burst(&DMA_DEV, TEE_CRYPTO_GDMA_CH, false); +#endif + dma_ll_tx_enable_data_burst(&DMA_DEV, TEE_CRYPTO_GDMA_CH, true); dma_ll_tx_enable_descriptor_burst(&DMA_DEV, TEE_CRYPTO_GDMA_CH, true); - - dma_ll_rx_enable_data_burst(&DMA_DEV, TEE_CRYPTO_GDMA_CH, false); dma_ll_rx_enable_descriptor_burst(&DMA_DEV, TEE_CRYPTO_GDMA_CH, true); dma_ll_tx_reset_channel(&DMA_DEV, TEE_CRYPTO_GDMA_CH);