Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'fix/spi_master_p4_change_default_clk_pll_v5.3' into 'release/v5.3'

Browse Source 
fix(driver_spi): master driver change esp32p4 default src to pll (v5.3)

See merge request espressif/esp-idf!40115
This commit is contained in:
Jiang Jiang Jian
2025-07-16 17:30:28 +08:00
parent c04f7e0650 77eff50f99
commit 17264e6711
6 changed files with 37 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/hal/esp32p4/include/hal/spi_ll.h
+2 -2
View File
@@ -38,10 +38,10 @@ extern "C" {
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : (((ID)==2) ? &GPSPI3 : NULL))
#define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits
#define SPI_LL_DMA_MAX_BIT_LEN SPI_MS_DATA_BITLEN
#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words
#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral
#define SPI_LL_CLK_SRC_PRE_DIV_MAX 512//div1(8bit) * div2(8bit but set const 2)
#define SPI_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized
/**