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feat(dma2d,ppa): Support flash encryption for DMA2D and PPA

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This commit is contained in:
Song Ruo Jing
2026-03-20 16:53:29 +08:00
parent cdcb4cbce8
commit 163a95614c
67 changed files with 469 additions and 146 deletions
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components/esp_hal_dma/esp32c5/include/hal/gdma_ll.h
-1
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@@ -17,7 +17,6 @@
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 32 // PSRAM controller doesn't support burst access with size > 32 bytes
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#ifdef __cplusplus
extern "C" {
components/esp_hal_dma/esp32c61/include/hal/gdma_ll.h
-1
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@@ -17,7 +17,6 @@
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 32 // PSRAM controller doesn't support burst access with size > 32 bytes
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#ifdef __cplusplus
extern "C" {
components/esp_hal_dma/esp32h21/include/hal/gdma_ll.h
-1
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@@ -53,7 +53,6 @@ extern "C" {
#define GDMA_LL_AHB_DESC_ALIGNMENT 4
#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT 1
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#define GDMA_LL_AHB_M2M_CAPABLE_PAIR_MASK 0x07 // pair 0,1,2 are M2M capable
components/esp_hal_dma/esp32h4/include/hal/gdma_ll.h
-1
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@@ -17,7 +17,6 @@
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 64 // PSRAM support INCR16
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#ifdef __cplusplus
extern "C" {
components/esp_hal_dma/esp32p4/include/hal/dma2d_ll.h
+13 -13
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -245,23 +245,23 @@ static inline void dma2d_ll_rx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t
* @brief Set 2D-DMA RX channel maximum burst reading data length in bytes
*/
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t channel, dma2d_data_burst_length_t length)
static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t channel, uint32_t length)
{
uint32_t sel;
switch (length) {
case DMA2D_DATA_BURST_LENGTH_8:
case 8:
sel = 0;
break;
case DMA2D_DATA_BURST_LENGTH_16:
case 16:
sel = 1;
break;
case DMA2D_DATA_BURST_LENGTH_32:
case 32:
sel = 2;
break;
case DMA2D_DATA_BURST_LENGTH_64:
case 64:
sel = 3;
break;
case DMA2D_DATA_BURST_LENGTH_128:
case 128:
sel = 4;
break;
default:
@@ -761,23 +761,23 @@ static inline void dma2d_ll_tx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t
* @brief Set 2D-DMA TX channel maximum burst reading data length in bytes
*/
__attribute__((always_inline))
static inline void dma2d_ll_tx_set_data_burst_length(dma2d_dev_t *dev, uint32_t channel, dma2d_data_burst_length_t length)
static inline void dma2d_ll_tx_set_data_burst_length(dma2d_dev_t *dev, uint32_t channel, uint32_t length)
{
uint32_t sel;
switch (length) {
case DMA2D_DATA_BURST_LENGTH_8:
case 8:
sel = 0;
break;
case DMA2D_DATA_BURST_LENGTH_16:
case 16:
sel = 1;
break;
case DMA2D_DATA_BURST_LENGTH_32:
case 32:
sel = 2;
break;
case DMA2D_DATA_BURST_LENGTH_64:
case 64:
sel = 3;
break;
case DMA2D_DATA_BURST_LENGTH_128:
case 128:
sel = 4;
break;
default:
components/esp_hal_dma/esp32p4/include/hal/gdma_ll.h
-1
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@@ -58,7 +58,6 @@
#define GDMA_LL_AHB_DESC_ALIGNMENT 4
#define GDMA_LL_AXI_DESC_ALIGNMENT 8
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 128 // PSRAM controller doesn't support burst access with size > 128 bytes
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
components/esp_hal_dma/esp32s3/include/hal/gdma_ll.h
-1
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@@ -71,7 +71,6 @@ extern "C" {
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT 1
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 64 // PSRAM controller doesn't support burst access with size > 64 bytes
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#define GDMA_LL_AHB_M2M_CAPABLE_PAIR_MASK 0x1F // pair 0,1,2,3,4 are M2M capable
components/esp_hal_dma/include/hal/dma2d_types.h
+1 -15
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -116,20 +116,6 @@ typedef enum {
DMA2D_CHANNEL_DIRECTION_RX, /*!< 2D-DMA channel direction: RX */
} dma2d_channel_direction_t;
/**
* @brief Enumeration of 2D-DMA data burst length options
*
* Starting from 1, saving 0 for special purpose (upper layer could use 0 to be a default burst length)
*/
typedef enum {
DMA2D_DATA_BURST_LENGTH_8 = 1, /*!< 2D-DMA block size: 8 bytes */
DMA2D_DATA_BURST_LENGTH_16, /*!< 2D-DMA block size: 16 bytes */
DMA2D_DATA_BURST_LENGTH_32, /*!< 2D-DMA block size: 32 bytes */
DMA2D_DATA_BURST_LENGTH_64, /*!< 2D-DMA block size: 64 bytes */
DMA2D_DATA_BURST_LENGTH_128, /*!< 2D-DMA block size: 128 bytes */
DMA2D_DATA_BURST_LENGTH_INVALID, /*!< Invalid 2D-DMA block size */
} dma2d_data_burst_length_t;
/**
* @brief Enumeration of 2D-DMA macro block size options
* Only useful in DMA2D_DESCRIPTOR_BLOCK_RW_MODE_MULTIPLE mode (dma2d_en = 1, mode = 1)