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https://github.com/espressif/esp-idf.git
synced 2026-10-03 03:31:41 +03:00
feat(esp_hw_support): add cache access counter API
This commit is contained in:
Ivan Grokhotkov (bot)
@@ -69,7 +69,8 @@ if(NOT non_os_build)
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"port/${target}/esp_clk_tree.c"
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"spi_bus_lock.c"
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"heap_align_hw.c"
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"clk_utils.c")
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"clk_utils.c"
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"esp_cache_cnt.c")
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if(CONFIG_SOC_USB_OTG_SUPPORTED)
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list(APPEND srcs "usb_phy/usb_phy.c")
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endif()
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@@ -0,0 +1,164 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Chip-agnostic implementation of the cache access counter API, built on
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* top of the cache profile counter functions of hal/cache_ll.h and the
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* unit descriptor table in soc/cache_periph.h.
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*/
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#include <inttypes.h>
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#include "esp_cache_cnt.h"
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#include "soc/soc_caps.h"
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float esp_cache_cnt_miss_ratio(const esp_cache_cnt_data_t *data)
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{
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const uint32_t needed = ESP_CACHE_CNT_VALID_ACCESSES | ESP_CACHE_CNT_VALID_LINE_FILLS;
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if ((data->valid_mask & needed) != needed || data->accesses == 0) {
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return 0.0f;
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}
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return (float)data->line_fills / (float)data->accesses;
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}
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#if SOC_CACHE_CNT_SUPPORTED
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#include "hal/cache_ll.h"
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size_t esp_cache_cnt_num_units(void)
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{
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return SOC_CACHE_CNT_UNITS_NUM;
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}
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esp_err_t esp_cache_cnt_get_unit_info(size_t unit, esp_cache_cnt_unit_info_t *out)
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{
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if (unit >= SOC_CACHE_CNT_UNITS_NUM || out == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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const cache_profile_counter_unit_t *desc = &cache_periph_profile_counter_units[unit];
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out->name = desc->name;
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out->cache_level = desc->level;
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out->core_id = desc->core_id;
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out->traffic_type = desc->traffic;
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return ESP_OK;
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}
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esp_err_t esp_cache_cnt_start(void)
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{
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cache_ll_clear_profile_counter();
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cache_ll_enable_profile_counter(true);
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return ESP_OK;
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}
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esp_err_t esp_cache_cnt_stop(void)
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{
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cache_ll_enable_profile_counter(false);
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return ESP_OK;
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}
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esp_err_t esp_cache_cnt_clear(void)
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{
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cache_ll_clear_profile_counter();
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return ESP_OK;
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}
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esp_err_t esp_cache_cnt_get(size_t unit, esp_cache_cnt_data_t *out)
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{
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if (unit >= SOC_CACHE_CNT_UNITS_NUM || out == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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*out = (esp_cache_cnt_data_t) { 0 };
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if (cache_ll_get_profile_counter(unit, CACHE_PROFILE_COUNTER_HIT, &out->accesses)) {
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out->valid_mask |= ESP_CACHE_CNT_VALID_ACCESSES;
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}
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if (cache_ll_get_profile_counter(unit, CACHE_PROFILE_COUNTER_MISS, &out->stall_events)) {
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out->valid_mask |= ESP_CACHE_CNT_VALID_STALL_EVENTS;
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}
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if (cache_ll_get_profile_counter(unit, CACHE_PROFILE_COUNTER_CONFLICT, &out->conflicts)) {
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out->valid_mask |= ESP_CACHE_CNT_VALID_CONFLICTS;
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}
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if (cache_ll_get_profile_counter(unit, CACHE_PROFILE_COUNTER_NXTLVL_RD, &out->line_fills)) {
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out->valid_mask |= ESP_CACHE_CNT_VALID_LINE_FILLS;
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}
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if (cache_ll_get_profile_counter(unit, CACHE_PROFILE_COUNTER_NXTLVL_WR, &out->writebacks)) {
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out->valid_mask |= ESP_CACHE_CNT_VALID_WRITEBACKS;
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}
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return ESP_OK;
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}
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static void print_counter(FILE *out, const esp_cache_cnt_data_t *data, uint32_t flag, uint32_t value)
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{
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if (data->valid_mask & flag) {
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fprintf(out, " %12" PRIu32, value);
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} else {
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fprintf(out, " %12s", "-");
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}
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}
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esp_err_t esp_cache_cnt_dump(FILE *out)
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{
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if (out == NULL) {
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out = stdout;
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}
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fprintf(out, "%-20s %12s %12s %12s %12s %10s\n",
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"unit", "accesses", "line fills", "writebacks", "conflicts", "miss rate");
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for (size_t unit = 0; unit < SOC_CACHE_CNT_UNITS_NUM; unit++) {
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esp_cache_cnt_unit_info_t info;
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esp_cache_cnt_data_t data;
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esp_cache_cnt_get_unit_info(unit, &info);
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esp_cache_cnt_get(unit, &data);
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fprintf(out, "%-20s", info.name);
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print_counter(out, &data, ESP_CACHE_CNT_VALID_ACCESSES, data.accesses);
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print_counter(out, &data, ESP_CACHE_CNT_VALID_LINE_FILLS, data.line_fills);
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print_counter(out, &data, ESP_CACHE_CNT_VALID_WRITEBACKS, data.writebacks);
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print_counter(out, &data, ESP_CACHE_CNT_VALID_CONFLICTS, data.conflicts);
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fprintf(out, " %9.2f%%\n", 100.0f * esp_cache_cnt_miss_ratio(&data));
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}
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return ESP_OK;
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}
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#else // !SOC_CACHE_CNT_SUPPORTED
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size_t esp_cache_cnt_num_units(void)
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{
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return 0;
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}
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esp_err_t esp_cache_cnt_get_unit_info(size_t unit, esp_cache_cnt_unit_info_t *out)
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{
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(void) unit;
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(void) out;
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return ESP_ERR_INVALID_ARG;
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}
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esp_err_t esp_cache_cnt_start(void)
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{
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return ESP_ERR_NOT_SUPPORTED;
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}
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esp_err_t esp_cache_cnt_stop(void)
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{
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return ESP_ERR_NOT_SUPPORTED;
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}
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esp_err_t esp_cache_cnt_clear(void)
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{
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return ESP_ERR_NOT_SUPPORTED;
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}
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esp_err_t esp_cache_cnt_get(size_t unit, esp_cache_cnt_data_t *out)
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{
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(void) unit;
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(void) out;
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return ESP_ERR_NOT_SUPPORTED;
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}
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esp_err_t esp_cache_cnt_dump(FILE *out)
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{
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(void) out;
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return ESP_ERR_NOT_SUPPORTED;
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}
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#endif // !SOC_CACHE_CNT_SUPPORTED
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@@ -0,0 +1,168 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stddef.h>
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#include <stdio.h>
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#include "esp_err.h"
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#include "soc/cache_periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Cache access counter API.
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*
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* The set of counters differs between chips: the number of cache levels, the
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* number of request buses per cache, and which counters exist per bus all
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* vary. Instead of a fixed list of caches, the API exposes a chip-defined
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* list of counter "units". Each unit is one set of counters observing one
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* traffic stream (e.g. "instruction fetches from core 0 into the L1 cache").
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* Applications enumerate the units at runtime with esp_cache_cnt_num_units()
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* and esp_cache_cnt_get_unit_info(), so they keep working when a new chip
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* adds or removes units.
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*/
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/**
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* @brief Description of one counter unit.
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*/
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typedef struct {
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const char *name; /*!< Short human-readable name, e.g. "l1-icache-core0" */
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uint8_t cache_level; /*!< Cache level the counters belong to, counting from the CPU.
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On most chips there is a single level (the flash/PSRAM cache);
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on the ESP32-P4, level 1 is the L1 cache in front of internal
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memory and level 2 is the flash/PSRAM cache. */
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cache_profile_traffic_t traffic_type; /*!< Kind of traffic observed */
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int8_t core_id; /*!< Core the traffic originates from, or -1 if unknown/mixed */
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} esp_cache_cnt_unit_info_t;
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/**
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* @name Flags for esp_cache_cnt_data_t::valid_mask
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*
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* Not every counter exists for every unit (e.g. instruction buses have no
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* write-back counter). A field of esp_cache_cnt_data_t is only meaningful if
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* the corresponding flag is set.
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* @{
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*/
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#define ESP_CACHE_CNT_VALID_ACCESSES (1 << 0)
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#define ESP_CACHE_CNT_VALID_STALL_EVENTS (1 << 1)
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#define ESP_CACHE_CNT_VALID_CONFLICTS (1 << 2)
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#define ESP_CACHE_CNT_VALID_LINE_FILLS (1 << 3)
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#define ESP_CACHE_CNT_VALID_WRITEBACKS (1 << 4)
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/** @} */
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/**
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* @brief Counter values for one unit.
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*
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* Note that the hardware "hit" and "miss" counters do not directly hold the
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* number of hit and missed accesses:
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* - accesses: the hit counter increments once for every access that completes,
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* whether or not it had to wait for a line fill first.
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* - stall_events: the miss counter increments repeatedly while an access is
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* stalled on a miss, so it grows roughly with the total miss latency. This is
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* only useful as a relative measure.
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* - line_fills: the next-level read counter increments once per line fetched
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* from the next level, so it is the true miss count.
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*
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* The miss ratio of a cache is therefore line_fills / accesses.
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*/
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typedef struct {
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uint32_t valid_mask; /*!< Bitwise OR of ESP_CACHE_CNT_VALID_* flags for the fields below */
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uint32_t accesses; /*!< Completed accesses (hardware hit counter) */
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uint32_t stall_events; /*!< Miss stall events; grows with total miss latency,
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NOT the number of missed accesses */
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uint32_t conflicts; /*!< Conflicts between requesters on this cache */
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uint32_t line_fills; /*!< Lines fetched from the next level (true miss count) */
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uint32_t writebacks; /*!< Lines written back to the next level. Only present for data
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traffic on chips with a write-back cache (PSRAM support,
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see SOC_CACHE_WRITEBACK_SUPPORTED). */
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} esp_cache_cnt_data_t;
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/**
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* @brief Number of counter units on this chip.
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*
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* @return Number of units; 0 if the chip has no cache access counters.
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*/
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size_t esp_cache_cnt_num_units(void);
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/**
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* @brief Get the description of a counter unit.
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*
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* @param unit Unit index, 0 to esp_cache_cnt_num_units() - 1
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* @param[out] out Unit description
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*
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* @return
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* - ESP_OK on success
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* - ESP_ERR_INVALID_ARG if unit is out of range or out is NULL
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*/
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esp_err_t esp_cache_cnt_get_unit_info(size_t unit, esp_cache_cnt_unit_info_t *out);
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/**
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* @brief Clear and enable all cache access counters.
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*
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* @return
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* - ESP_OK on success
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* - ESP_ERR_NOT_SUPPORTED if the target has no cache access counters
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*/
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esp_err_t esp_cache_cnt_start(void);
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/**
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* @brief Disable all cache access counters. Counter values are retained.
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*
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* @return
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* - ESP_OK on success
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* - ESP_ERR_NOT_SUPPORTED if the target has no cache access counters
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*/
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esp_err_t esp_cache_cnt_stop(void);
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/**
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* @brief Reset all cache access counters to zero. Counting state is not changed.
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*
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* @return
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* - ESP_OK on success
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* - ESP_ERR_NOT_SUPPORTED if the target has no cache access counters
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*/
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esp_err_t esp_cache_cnt_clear(void);
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/**
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* @brief Read the current counter values for the given unit.
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*
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* @param unit Unit index, 0 to esp_cache_cnt_num_units() - 1
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* @param[out] out Counter values
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*
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* @return
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* - ESP_OK on success
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* - ESP_ERR_INVALID_ARG if unit is out of range or out is NULL
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* - ESP_ERR_NOT_SUPPORTED if the target has no cache access counters
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*/
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esp_err_t esp_cache_cnt_get(size_t unit, esp_cache_cnt_data_t *out);
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/**
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* @brief Miss ratio (0.0 to 1.0) computed from a set of counter values.
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*
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* @param data Counter values obtained from esp_cache_cnt_get()
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*
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* @return Miss ratio; 0.0 if the unit does not provide the counters needed
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* to compute it.
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*/
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float esp_cache_cnt_miss_ratio(const esp_cache_cnt_data_t *data);
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/**
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* @brief Print a table with the current values of all cache access counters.
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*
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* @param out Output stream; if NULL, print to stdout
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*
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* @return
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* - ESP_OK on success
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* - ESP_ERR_NOT_SUPPORTED if the target has no cache access counters
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*/
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esp_err_t esp_cache_cnt_dump(FILE *out);
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#ifdef __cplusplus
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}
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#endif
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