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fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop
The Xtensa load/store handler did not properly handle 8/16-bit memory access to IRAM regions configured with MALLOC_CAP_IRAM_8BIT (and CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y) from a loop (LBEG/LEND/LCOUNT) context. This caused the loop to exit after the first access, instead of continuing to iterate as intended. Closes https://github.com/espressif/esp-idf/issues/14127
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@@ -0,0 +1,53 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Zero-overhead loop adjustment helpers for Xtensa assembly code.
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*
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* Used by exception handlers to emulate loop hardware when an exception
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* occurs at LEND so execution resumes at LBEG with LCOUNT decremented.
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*/
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#ifndef XTENSA_ZOL_MACROS_H
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#define XTENSA_ZOL_MACROS_H
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#if __XTENSA__
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#include "xtensa/config/core-isa.h"
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#include "xtensa/config/xt_specreg.h"
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/**
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* Adjust loop counter and return address for exceptions at LEND.
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*
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* When an exception occurs on instruction at LEND address of a zero-overhead loop,
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* we must decrement LCOUNT and set EPC back to LBEG so the loop continues
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* iterating after the exception is handled. Otherwise, the loop exits prematurely.
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*
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* if (EPC == LEND && LCOUNT != 0) {
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* LCOUNT--;
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* EPC = LBEG;
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* }
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*
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* param[in/out] epc_reg - register containing EPC, updated to LBEG if needed
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* param[in/out] tmp_reg - temporary register for intermediate values
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*
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* Return: Use epc_reg to set corrected EPC value.
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*/
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.macro XT_ZOL_EPC_LCOUNT_RESTORE epc_reg tmp_reg
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#if XCHAL_HAVE_LOOPS
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rsr \tmp_reg, XT_REG_LEND
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bne \epc_reg, \tmp_reg, 1f
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rsr \tmp_reg, XT_REG_LCOUNT
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beqz \tmp_reg, 1f
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addi \tmp_reg, \tmp_reg, -1
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wsr \tmp_reg, XT_REG_LCOUNT
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rsr \epc_reg, XT_REG_LBEG
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1:
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#endif
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.endm
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#endif /* __XTENSA__ */
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#endif /* XTENSA_ZOL_MACROS_H */
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