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feat(ppa): add sleep retention support for DMA2D and PPA

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This commit is contained in:
Song Ruo Jing
2026-06-15 15:45:07 +08:00
parent 67fdf46105
commit 14d8570163
26 changed files with 690 additions and 155 deletions
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components/soc/esp32p4/include/soc/retention_periph_defs.h
+3 -1
View File
@@ -64,6 +64,8 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_JPEG = 38,
SLEEP_RETENTION_MODULE_LCDCAM = 39,
SLEEP_RETENTION_MODULE_H264 = 40,
SLEEP_RETENTION_MODULE_DMA2D = 41,
SLEEP_RETENTION_MODULE_PPA = 42,
/* PMU REGDMA clock icg */
SLEEP_RETENTION_MODULE_CLOCK_ICG = SOC_PM_RETENTION_MODULE_NUM - 2,
@@ -71,7 +73,7 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
#define is_top_domain_module(m) (((m) <= SLEEP_RETENTION_MODULE_H264) || ((m) == SLEEP_RETENTION_MODULE_CLOCK_ICG))
#define is_top_domain_module(m) (((m) <= SLEEP_RETENTION_MODULE_PPA) || ((m) == SLEEP_RETENTION_MODULE_CLOCK_ICG))
#ifdef __cplusplus
}
components/soc/esp32p4/system_retention_periph.c
+5
View File
@@ -25,8 +25,13 @@
#include "soc/pvt_reg.h"
/* Interrupt Matrix Registers Context */
#if (CONFIG_ESP_REV_MIN_FULL < 300)
#define N_REGS_INTR_CORE0() (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1)
#define N_REGS_INTR_CORE1() (((INTERRUPT_CORE1_CLOCK_GATE_REG - DR_REG_INTERRUPT_CORE1_BASE) / 4) + 1)
#else
#define N_REGS_INTR_CORE0() (((INTERRUPT_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1)
#define N_REGS_INTR_CORE1() (((INTERRUPT_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_REG - DR_REG_INTERRUPT_CORE1_BASE) / 4) + 1)
#endif
const regdma_entries_config_t intr_matrix_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0x00), DR_REG_INTERRUPT_CORE0_BASE, DR_REG_INTERRUPT_CORE0_BASE, N_REGS_INTR_CORE0(), 0, 0), .owner = ENTRY(0) }, /* intr matrix */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0x01), DR_REG_INTERRUPT_CORE1_BASE, DR_REG_INTERRUPT_CORE1_BASE, N_REGS_INTR_CORE1(), 0, 0), .owner = ENTRY(0) } /* intr matrix */