Merge branch 'feature/update-gnu-toolchain-to-12.2.0_20230208' into 'master'

tools: update GNU toolchain version to 'esp-12.2.0_20230208'

Closes GCC-297, GCC-224, GCC-299, GCC-254, and GCC-256

See merge request espressif/esp-idf!22270

components/app_trace/CMakeLists.txt

@@ -1,8 +1,16 @@
 set(srcs
     "app_trace.c"
     "app_trace_util.c"
-    "host_file_io.c"
-    "gcov/gcov_rtio.c")
+    "host_file_io.c")
+
+if(CONFIG_APPTRACE_GCOV_ENABLE)
+    if("${CMAKE_C_COMPILER_ID}" STREQUAL "GNU")
+        list(APPEND srcs
+            "gcov/gcov_rtio.c")
+    else()
+        fail_at_build_time(app_trace "Only GNU compiler can link with Gcov library")
+    endif()
+endif()
 
 set(include_dirs "include")
 
@@ -54,13 +62,49 @@ idf_component_register(SRCS "${srcs}"
                        REQUIRES esp_timer
                        LDFRAGMENTS linker.lf)
 
-# disable --coverage for this component, as it is used as transport
-# for gcov
-target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-profile-arcs" "-fno-test-coverage")
-
 # Force app_trace to also appear later than gcov in link line
 idf_component_get_property(app_trace app_trace COMPONENT_LIB)
-target_link_libraries(${COMPONENT_LIB} INTERFACE $<TARGET_FILE:${app_trace}> gcov $<TARGET_FILE:${app_trace}> c)
+
+if(CONFIG_APPTRACE_GCOV_ENABLE)
+    # The original Gcov library from toolchain will be objcopy with symbols redefinitions (see file gcov/io_sym.map).
+    # This needs because ESP has no file-system onboard, and redefined functions solves this problem and transmits
+    # output file to host PC.
+
+    # Set a name for Gcov library
+    set(GCOV_LIB libgcov_rtio)
+
+    # Set include direcrory of Gcov internal headers
+    execute_process(COMMAND ${CMAKE_C_COMPILER} -print-file-name=plugin
+                    OUTPUT_VARIABLE gcc_plugin_dir
+                    OUTPUT_STRIP_TRAILING_WHITESPACE
+                    ERROR_QUIET)
+    set_source_files_properties(gcov/gcov_rtio.c
+                                PROPERTIES COMPILE_FLAGS "-I${gcc_plugin_dir}/include")
+
+    # Copy libgcov.a with symbols redefinition
+    find_library(GCOV_LIBRARY_PATH gcov ${CMAKE_C_IMPLICIT_LINK_DIRECTORIES})
+    add_custom_command(OUTPUT ${GCOV_LIB}.a
+                       COMMAND ${_CMAKE_TOOLCHAIN_PREFIX}objcopy
+                               --redefine-syms ${CMAKE_CURRENT_LIST_DIR}/gcov/io_sym.map
+                               ${GCOV_LIBRARY_PATH} ${GCOV_LIB}.a
+                       MAIN_DEPENDENCY ${GCOV_LIBRARY_PATH}
+                       VERBATIM)
+    add_custom_target(${GCOV_LIB}_target DEPENDS ${GCOV_LIB}.a)
+    add_library(${GCOV_LIB} STATIC IMPORTED)
+    set_target_properties(${GCOV_LIB}
+                          PROPERTIES
+                          IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/${GCOV_LIB}.a)
+    add_dependencies(${GCOV_LIB} ${GCOV_LIB}_target)
+    add_dependencies(${COMPONENT_LIB} ${GCOV_LIB})
+
+    # disable --coverage for this component, as it is used as transport for gcov
+    target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-profile-arcs" "-fno-test-coverage")
+    target_link_options(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=__gcov_init")
+
+    target_link_libraries(${COMPONENT_LIB} INTERFACE ${GCOV_LIB} $<TARGET_FILE:${app_trace}> c)
+else()
+    target_link_libraries(${COMPONENT_LIB} INTERFACE $<TARGET_FILE:${app_trace}> c)
+endif()
 
 # This function adds a dependency on the given component if the component is included into the build.
 function(maybe_add_component component_name)

components/app_trace/gcov/gcov_rtio.c

@@ -103,7 +103,7 @@ static int esp_dbg_stub_gcov_entry(void)
     return ESP_OK;
 }
 
-int gcov_rtio_atexit(void (*function)(void) __attribute__ ((unused)))
+void gcov_rtio_init(void)
 {
     uint32_t capabilities = 0;
     ESP_EARLY_LOGV(TAG, "%s", __FUNCTION__);
@@ -112,7 +112,6 @@ int gcov_rtio_atexit(void (*function)(void) __attribute__ ((unused)))
         esp_dbg_stub_entry_set(ESP_DBG_STUB_ENTRY_CAPABILITIES, capabilities | ESP_DBG_STUB_CAP_GCOV_TASK);
     }
     esp_register_freertos_tick_hook(gcov_create_task_tick_hook);
-    return ESP_OK;
 }
 
 void esp_gcov_dump(void)
@@ -172,4 +171,19 @@ long gcov_rtio_ftell(void *stream)
     ESP_EARLY_LOGV(TAG, "%s(%p) = %ld", __FUNCTION__, stream, ret);
     return ret;
 }
+
+void gcov_rtio_setbuf(void *arg1 __attribute__ ((unused)), void *arg2 __attribute__ ((unused)))
+{
+    return;
+}
+
+/* Wrappers for Gcov functions */
+
+extern void __real___gcov_init(void *info);
+void __wrap___gcov_init(void *info)
+{
+    __real___gcov_init(info);
+    gcov_rtio_init();
+}
+
 #endif

components/app_trace/gcov/io_sym.map

@@ -0,0 +1,7 @@
+fopen          gcov_rtio_fopen
+fclose         gcov_rtio_fclose
+fwrite         gcov_rtio_fwrite
+fread          gcov_rtio_fread
+fseek          gcov_rtio_fseek
+ftell          gcov_rtio_ftell
+setbuf         gcov_rtio_setbuf

components/bt/esp_ble_mesh/api/core/esp_ble_mesh_provisioning_api.c

@@ -494,7 +494,7 @@ esp_err_t esp_ble_mesh_set_fast_prov_info(esp_ble_mesh_fast_prov_info_t *fast_pr
     arg.set_fast_prov_info.iv_index = fast_prov_info->iv_index;
     arg.set_fast_prov_info.offset = fast_prov_info->offset;
     arg.set_fast_prov_info.match_len = fast_prov_info->match_len;
-    if (fast_prov_info->match_len && fast_prov_info->match_val) {
+    if (fast_prov_info->match_len) {
         memcpy(arg.set_fast_prov_info.match_val, fast_prov_info->match_val, fast_prov_info->match_len);
     }
     return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_mesh_prov_args_t), NULL, NULL)

components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c

@@ -50,7 +50,7 @@ static void btc_ble_mesh_ble_free_req_data(btc_msg_t *msg)
 #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
     esp_ble_mesh_ble_cb_param_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -116,7 +116,7 @@ void btc_ble_mesh_ble_call_handler(btc_msg_t *msg)
     esp_ble_mesh_ble_cb_param_t param = {0};
     btc_ble_mesh_ble_args_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }

components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c

@@ -87,7 +87,7 @@ void btc_ble_mesh_config_client_arg_deep_free(btc_msg_t *msg)
 {
     btc_ble_mesh_config_client_args_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -232,7 +232,7 @@ static void btc_ble_mesh_config_client_free_req_data(btc_msg_t *msg)
 {
     esp_ble_mesh_cfg_client_cb_param_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -618,7 +618,7 @@ void btc_ble_mesh_config_client_call_handler(btc_msg_t *msg)
     btc_ble_mesh_config_client_args_t *arg = NULL;
     esp_ble_mesh_cfg_client_cb_param_t cb = {0};
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -656,7 +656,7 @@ void btc_ble_mesh_config_client_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_cfg_client_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -748,7 +748,7 @@ void btc_ble_mesh_config_server_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_cfg_server_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }

components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c

@@ -111,7 +111,7 @@ void btc_ble_mesh_generic_client_arg_deep_free(btc_msg_t *msg)
 {
     btc_ble_mesh_generic_client_args_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -295,7 +295,7 @@ static void btc_ble_mesh_generic_client_free_req_data(btc_msg_t *msg)
 {
     esp_ble_mesh_generic_client_cb_param_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -447,7 +447,7 @@ void btc_ble_mesh_generic_client_call_handler(btc_msg_t *msg)
     esp_ble_mesh_generic_client_cb_param_t cb = {0};
     bt_mesh_client_common_param_t common = {0};
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -507,7 +507,7 @@ void btc_ble_mesh_generic_client_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_generic_client_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -629,7 +629,7 @@ static void btc_ble_mesh_generic_server_free_req_data(btc_msg_t *msg)
 {
     esp_ble_mesh_generic_server_cb_param_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -738,7 +738,7 @@ void btc_ble_mesh_generic_server_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_generic_server_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }

components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c

@@ -551,7 +551,7 @@ void btc_ble_mesh_health_server_call_handler(btc_msg_t *msg)
     esp_ble_mesh_health_server_cb_param_t param = {0};
     btc_ble_mesh_health_server_args_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -577,7 +577,7 @@ void btc_ble_mesh_health_server_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_health_server_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }

components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c

@@ -452,7 +452,7 @@ static void btc_ble_mesh_lighting_server_free_req_data(btc_msg_t *msg)
 {
     esp_ble_mesh_lighting_server_cb_param_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -553,7 +553,7 @@ void btc_ble_mesh_lighting_server_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_lighting_server_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }

components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c

@@ -124,7 +124,7 @@ void btc_ble_mesh_prov_arg_deep_free(btc_msg_t *msg)
 {
     btc_ble_mesh_prov_args_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -200,7 +200,7 @@ void btc_ble_mesh_model_arg_deep_free(btc_msg_t *msg)
 {
     btc_ble_mesh_model_args_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -309,7 +309,7 @@ static void btc_ble_mesh_model_free_req_data(btc_msg_t *msg)
 {
     esp_ble_mesh_model_cb_param_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -2278,9 +2278,7 @@ void btc_ble_mesh_prov_call_handler(btc_msg_t *msg)
     /* Callback operation completion events */
     btc_ble_mesh_prov_set_complete_cb(&param, act);
 
-    if (msg->arg) {
-        btc_ble_mesh_prov_arg_deep_free(msg);
-    }
+    btc_ble_mesh_prov_arg_deep_free(msg);
     return;
 }
 
@@ -2307,7 +2305,7 @@ void btc_ble_mesh_model_call_handler(btc_msg_t *msg)
     btc_ble_mesh_model_args_t *arg = NULL;
     int err = 0;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -2403,7 +2401,7 @@ void btc_ble_mesh_model_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_model_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }

components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c

@@ -179,7 +179,7 @@ void btc_ble_mesh_sensor_client_arg_deep_free(btc_msg_t *msg)
 {
     btc_ble_mesh_sensor_client_args_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -378,7 +378,7 @@ static void btc_ble_mesh_sensor_client_free_req_data(btc_msg_t *msg)
 {
     esp_ble_mesh_sensor_client_cb_param_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -529,7 +529,7 @@ void btc_ble_mesh_sensor_client_call_handler(btc_msg_t *msg)
     esp_ble_mesh_sensor_client_cb_param_t cb = {0};
     bt_mesh_client_common_param_t common = {0};
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -589,7 +589,7 @@ void btc_ble_mesh_sensor_client_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_sensor_client_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -761,7 +761,7 @@ static void btc_ble_mesh_sensor_server_free_req_data(btc_msg_t *msg)
 {
     esp_ble_mesh_sensor_server_cb_param_t *arg = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
@@ -870,7 +870,7 @@ void btc_ble_mesh_sensor_server_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_sensor_server_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }

components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c

@@ -456,7 +456,7 @@ void btc_ble_mesh_time_scene_server_cb_handler(btc_msg_t *msg)
 {
     esp_ble_mesh_time_scene_server_cb_param_t *param = NULL;
 
-    if (!msg || !msg->arg) {
+    if (!msg) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }

components/bt/host/bluedroid/bta/gatt/bta_gatts_act.c

@@ -699,7 +699,7 @@ void bta_gatts_indicate_handle (tBTA_GATTS_CB *p_cb, tBTA_GATTS_DATA *p_msg)
             cb_data.req_data.data_len = 0;
             cb_data.req_data.handle = p_msg->api_indicate.attr_id;
 
-            if (p_msg->api_indicate.value && (p_msg->api_indicate.len > 0)) {
+            if (p_msg->api_indicate.len > 0) {
                 cb_data.req_data.value = (uint8_t *) osi_malloc(p_msg->api_indicate.len);
                 if (cb_data.req_data.value != NULL) {
                     memset(cb_data.req_data.value, 0, p_msg->api_indicate.len);
@@ -709,9 +709,7 @@ void bta_gatts_indicate_handle (tBTA_GATTS_CB *p_cb, tBTA_GATTS_DATA *p_msg)
                     APPL_TRACE_ERROR("%s, malloc failed", __func__);
                 }
             } else {
-                if (p_msg->api_indicate.value) {
-                    APPL_TRACE_ERROR("%s, incorrect length", __func__);
-                }
+                APPL_TRACE_ERROR("%s, incorrect length", __func__);
             }
             (*p_rcb->p_cback)(BTA_GATTS_CONF_EVT, &cb_data);
             if (cb_data.req_data.value != NULL) {

components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c

@@ -1472,10 +1472,10 @@ void btc_hf_cb_handler(btc_msg_t *msg)
         case BTA_AG_AT_D_EVT:
         {
             do {
-                if (event == BTA_AG_AT_D_EVT && p_data->val.str) {           // dial_number_or_memory
+                if (event == BTA_AG_AT_D_EVT) {           // dial_number_or_memory
                     memset(&param, 0, sizeof(esp_hf_cb_param_t));
                     param.out_call.num_or_loc = osi_malloc((strlen(p_data->val.str) + 1) * sizeof(char));
-                    sprintf(param.out_call.num_or_loc, p_data->val.str);
+                    sprintf(param.out_call.num_or_loc, "%s", p_data->val.str);
                     btc_hf_cb_to_app(ESP_HF_DIAL_EVT, &param);
                     send_indicator_update(BTA_AG_IND_CALLSETUP,BTA_AG_CALLSETUP_OUTGOING);
                     osi_free(param.out_call.num_or_loc);

components/bt/host/bluedroid/stack/smp/smp_l2c.c

@@ -111,7 +111,7 @@ static void smp_connect_callback (UINT16 channel, BD_ADDR bd_addr, BOOLEAN conne
     if (transport == BT_TRANSPORT_BR_EDR || memcmp(bd_addr, dummy_bda, BD_ADDR_LEN) == 0) {
         return;
     }
-    if(!connected && &p_cb->rsp_timer_ent) {
+    if(!connected) {
         //free timer
         btu_free_timer(&p_cb->rsp_timer_ent);
     }

components/esp_event/esp_event.c

@@ -631,6 +631,7 @@ esp_err_t esp_event_loop_run(esp_event_loop_handle_t event_loop, TickType_t tick
 esp_err_t esp_event_loop_delete(esp_event_loop_handle_t event_loop)
 {
     assert(event_loop);
+    ESP_LOGD(TAG, "deleting loop %p", (void*) event_loop);
 
     esp_event_loop_instance_t* loop = (esp_event_loop_instance_t*) event_loop;
     SemaphoreHandle_t loop_mutex = loop->mutex;
@@ -677,8 +678,6 @@ esp_err_t esp_event_loop_delete(esp_event_loop_handle_t event_loop)
 #endif
     vSemaphoreDelete(loop_mutex);
 
-    ESP_LOGD(TAG, "deleted loop %p", (void*) event_loop);
-
     return ESP_OK;
 }
 

components/esp_hid/src/bt_hidd.c

@@ -569,7 +569,7 @@ void bt_hidd_cb(esp_hidd_cb_event_t event, esp_hidd_cb_param_t *param)
     case ESP_HIDD_REGISTER_APP_EVT: {
         if (param->register_app.status == ESP_HIDD_SUCCESS) {
             ESP_LOGD(TAG, "Setting hid parameters success!");
-            if (param->register_app.in_use && param->register_app.bd_addr != NULL) {
+            if (param->register_app.in_use) {
                 ESP_LOGI(TAG, "Start virtual cable plug!");
                 esp_bt_hid_device_connect(param->register_app.bd_addr);
             }

components/esp_hw_support/sleep_retention.c

@@ -198,16 +198,14 @@ void sleep_retention_entries_show_memories(void)
 void * sleep_retention_find_link_by_id(int id)
 {
     void *link = NULL;
-    if (&s_retention.lock) {
-        _lock_acquire_recursive(&s_retention.lock);
-        if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY &&
-            s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) {
-            for (int entry = 0; (link == NULL && entry < ARRAY_SIZE(s_retention.lists[s_retention.highpri].entries)); entry++) {
-                link = regdma_find_link_by_id(s_retention.lists[s_retention.highpri].entries[entry], entry, id);
-            }
+    _lock_acquire_recursive(&s_retention.lock);
+    if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY &&
+        s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) {
+        for (int entry = 0; (link == NULL && entry < ARRAY_SIZE(s_retention.lists[s_retention.highpri].entries)); entry++) {
+            link = regdma_find_link_by_id(s_retention.lists[s_retention.highpri].entries[entry], entry, id);
         }
-        _lock_release_recursive(&s_retention.lock);
     }
+    _lock_release_recursive(&s_retention.lock);
     return link;
 }
 
@@ -331,23 +329,21 @@ static void sleep_retention_entries_all_destroy_wrapper(uint32_t module)
 void sleep_retention_entries_destroy(int module)
 {
     assert(module != 0);
-    if (&s_retention.lock) {
-        _lock_acquire_recursive(&s_retention.lock);
-        sleep_retention_entries_join();
-        sleep_retention_entries_stats();
-        sleep_retention_entries_all_destroy_wrapper(module);
-        if (s_retention.modules == 0) {
-            sleep_retention_entries_check_and_distroy_final_default();
-            pmu_sleep_disable_regdma_backup();
-            memset((void *)s_retention.lists, 0, sizeof(s_retention.lists));
-            s_retention.highpri = (uint8_t)-1;
-            _lock_release_recursive(&s_retention.lock);
-            _lock_close_recursive(&s_retention.lock);
-            s_retention.lock = NULL;
-            return;
-        }
-        _lock_acquire_recursive(&s_retention.lock);
+    _lock_acquire_recursive(&s_retention.lock);
+    sleep_retention_entries_join();
+    sleep_retention_entries_stats();
+    sleep_retention_entries_all_destroy_wrapper(module);
+    if (s_retention.modules == 0) {
+        sleep_retention_entries_check_and_distroy_final_default();
+        pmu_sleep_disable_regdma_backup();
+        memset((void *)s_retention.lists, 0, sizeof(s_retention.lists));
+        s_retention.highpri = (uint8_t)-1;
+        _lock_release_recursive(&s_retention.lock);
+        _lock_close_recursive(&s_retention.lock);
+        s_retention.lock = NULL;
+        return;
     }
+    _lock_acquire_recursive(&s_retention.lock);
 }
 
 static esp_err_t sleep_retention_entries_create_impl(const sleep_retention_entries_config_t retent[], int num, regdma_link_priority_t priority, int module)
@@ -447,14 +443,12 @@ error:
 void sleep_retention_entries_get(sleep_retention_entries_t *entries)
 {
     memset(entries, 0, sizeof(sleep_retention_entries_t));
-    if (&s_retention.lock) {
-        _lock_acquire_recursive(&s_retention.lock);
-        if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY &&
-            s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) {
-            memcpy(entries, &s_retention.lists[s_retention.highpri].entries, sizeof(sleep_retention_entries_t));
-        }
-        _lock_release_recursive(&s_retention.lock);
+    _lock_acquire_recursive(&s_retention.lock);
+    if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY &&
+        s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) {
+        memcpy(entries, &s_retention.lists[s_retention.highpri].entries, sizeof(sleep_retention_entries_t));
     }
+    _lock_release_recursive(&s_retention.lock);
 }
 
 uint32_t IRAM_ATTR sleep_retention_get_modules(void)

components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c

@@ -40,8 +40,12 @@
 
 #define DEFAULT_SEND_DELAY_MS 1000
 
+#define IN_BUFFER_SIZE 1500
+
 static const char *TAG = "l2tap_test";
 
+char *in_buffer;
+
 typedef struct {
     esp_netif_t *eth_netif;
     esp_eth_mac_t *mac;
@@ -67,6 +71,19 @@ typedef struct {
 /* =============================================================================
  *                              Common Routines
  * ============================================================================= */
+
+void setUp(void) {
+    in_buffer = calloc(IN_BUFFER_SIZE, sizeof(*in_buffer));
+    if (!in_buffer) {
+        abort();
+    }
+}
+
+void tearDown(void) {
+    free(in_buffer);
+    in_buffer = NULL;
+}
+
 /**
  * @brief Event handler for Ethernet events
  *
@@ -286,7 +303,7 @@ typedef struct {
 
 static void open_read_task(void *task_param)
 {
-    char in_buffer[300] = { 0 };
+    const size_t in_buf_size = 300;
     open_close_task_ctrl_t *task_control = (open_close_task_ctrl_t *)task_param;
 
     task_control->eth_tap_fd = open("/dev/net/tap", 0);
@@ -321,11 +338,11 @@ static void open_read_task(void *task_param)
         ESP_LOGI(TAG, "task1: select timeout");
 
         // get an error when try to use closed fd
-        TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, sizeof(in_buffer)));
+        TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, in_buf_size));
     } else {
         ESP_LOGI(TAG, "task1: going to block on read...");
         // it is expected that blocking read is unblocked by close
-        TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, sizeof(in_buffer)));
+        TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, in_buf_size));
         ESP_LOGI(TAG, "task1: unblocked");
     }
     xSemaphoreGive(task_control->sem);
@@ -419,7 +436,6 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]")
     test_vfs_eth_network_t eth_network_hndls;
     int eth_tap_fd;
     int n;
-    char in_buffer[1500] = { 0 };
     int loop_cnt = 0;
 
     TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL));
@@ -452,7 +468,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]")
 
     // Verify the read does not block
     while (loop_cnt < 100) {
-        if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) {
+        if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) {
             ESP_LOG_BUFFER_HEX(TAG, in_buffer, n);
             ESP_LOGI(TAG, "recv test string: %s", ((test_vfs_eth_tap_msg_t *)in_buffer)->str);
             TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
@@ -473,7 +489,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]")
     // Verify non-blocking successful read operations used along with select
     // ==========================================================
     ESP_LOGI(TAG, "Verify non-blocking successful read operations used along with select...");
-    memset(in_buffer, 0, sizeof(in_buffer));
+    memset(in_buffer, 0, IN_BUFFER_SIZE);
     // Wait up to x seconds
     struct timeval tv;
     tv.tv_sec = 4;
@@ -491,7 +507,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]")
     TEST_ASSERT_GREATER_THAN(-1, FD_ISSET(eth_tap_fd, &rfds));
     loop_cnt = 0;
     while (loop_cnt < 100) {
-        if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) {
+        if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) {
             ESP_LOG_BUFFER_HEX(TAG, in_buffer, n);
             ESP_LOGI(TAG, "recv test string: %s", ((test_vfs_eth_tap_msg_t *)in_buffer)->str);
             TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
@@ -508,7 +524,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]")
     // Verify non-blocking unsuccessful read operations used along with select
     // ==========================================================
     ESP_LOGI(TAG, "Verify non-blocking unsuccessful read operations used along with select...");
-    memset(in_buffer, 0, sizeof(in_buffer));
+    memset(in_buffer, 0, IN_BUFFER_SIZE);
     // Wait up to x seconds
     tv.tv_sec = 2;
     tv.tv_usec = 0;
@@ -521,7 +537,7 @@ TEST_CASE("esp32 l2tap - non blocking read", "[ethernet]")
     TEST_ASSERT_EQUAL(0, select(eth_tap_fd + 1, &rfds, NULL, NULL, &tv));
     TEST_ASSERT_EQUAL(EAGAIN, errno);
 
-    n = read(eth_tap_fd, in_buffer, sizeof(in_buffer));
+    n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE);
     TEST_ASSERT_EQUAL(EAGAIN, errno);
     TEST_ASSERT_EQUAL(-1, n);
 
@@ -540,7 +556,6 @@ TEST_CASE("esp32 l2tap - blocking read", "[ethernet]")
     test_vfs_eth_network_t eth_network_hndls;
     int eth_tap_fd;
     int n;
-    char in_buffer[1500] = { 0 };
     int loop_cnt = 0;
 
     TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL));
@@ -573,7 +588,7 @@ TEST_CASE("esp32 l2tap - blocking read", "[ethernet]")
 
     // Verify the read does block
     while (loop_cnt < 100) {
-        if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) {
+        if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) {
             ESP_LOG_BUFFER_HEX(TAG, in_buffer, n);
             ESP_LOGI(TAG, "recv test string: %s", ((test_vfs_eth_tap_msg_t *)in_buffer)->str);
             TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
@@ -660,6 +675,7 @@ static void multi_fds_task (void *task_param)
     uint16_t eth_filter = task_info->eth_filter;
 
     int eth_tap_fds[NUM_OF_FDS];
+    test_vfs_eth_tap_msg_t recv_msg;
     test_vfs_eth_tap_msg_t test_msg = {
         .header = {
             .src.addr = {0},
@@ -667,7 +683,6 @@ static void multi_fds_task (void *task_param)
             .type = 0,
         }
     };
-    char in_buffer[sizeof(test_msg)] = { 0 };
 
     for (int i = 0; i < sizeof(eth_tap_fds) / sizeof(int); i++) {
         eth_tap_fds[i] = open("/dev/net/tap", O_NONBLOCK);
@@ -691,7 +706,7 @@ static void multi_fds_task (void *task_param)
             test_msg.cnt = msg_cnt;
             TEST_ASSERT_NOT_EQUAL(-1, write(eth_tap_fds[i], &test_msg, sizeof(test_msg)));
 
-            memset(in_buffer, 0, sizeof(in_buffer));
+            memset(&recv_msg, 0, sizeof(recv_msg));
 
             struct timeval tv;
             tv.tv_sec = 0;
@@ -702,9 +717,9 @@ static void multi_fds_task (void *task_param)
             FD_SET(eth_tap_fds[i], &rfds);
             if (select(eth_tap_fds[i] + 1, &rfds, NULL, NULL, &tv) > -1) {
                 if (FD_ISSET(eth_tap_fds[i], &rfds)) {
-                    int n = read(eth_tap_fds[i], in_buffer, sizeof(in_buffer));
+                    int n = read(eth_tap_fds[i], &recv_msg, sizeof(recv_msg));
                     TEST_ASSERT_GREATER_THAN(0, n);
-                    TEST_ASSERT_EQUAL(msg_cnt, ((test_vfs_eth_tap_msg_t *)in_buffer)->cnt);
+                    TEST_ASSERT_EQUAL(msg_cnt, recv_msg.cnt);
                 } else {
                     TEST_FAIL_MESSAGE("time out, frame was not successfully written (due to possible race condition)");
                 }
@@ -755,7 +770,6 @@ TEST_CASE("esp32 l2tap - ioctl - RCV_FILTER", "[ethernet]")
 {
     test_vfs_eth_network_t eth_network_hndls;
     int eth_tap_fd;
-    char in_buffer[1500] = { 0 };
 
     TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL));
     ethernet_init(&eth_network_hndls);
@@ -791,7 +805,7 @@ TEST_CASE("esp32 l2tap - ioctl - RCV_FILTER", "[ethernet]")
         .send_delay_ms = DEFAULT_SEND_DELAY_MS,
     };
     xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL);
-    int n = read(eth_tap_fd, in_buffer, sizeof(in_buffer));
+    int n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE);
     TEST_ASSERT_GREATER_THAN(0, n);
     TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
 
@@ -816,7 +830,7 @@ TEST_CASE("esp32 l2tap - ioctl - RCV_FILTER", "[ethernet]")
     send_task_ctrl.eth_type = eth_type_filter;
     xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL);
     ESP_LOGI(TAG, "Verify that the message with new Etherbet type is received...");
-    n = read(eth_tap_fd, in_buffer, sizeof(in_buffer));
+    n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE);
     TEST_ASSERT_GREATER_THAN(0, n);
     TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
 
@@ -852,7 +866,6 @@ TEST_CASE("esp32 l2tap - ioctl - INTF_DEVICE/DEVICE_DRV_HNDL", "[ethernet]")
 {
     test_vfs_eth_network_t eth_network_hndls;
     int eth_tap_fd;
-    char in_buffer[1500] = { 0 };
 
     TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL));
     ethernet_init(&eth_network_hndls);
@@ -886,7 +899,7 @@ TEST_CASE("esp32 l2tap - ioctl - INTF_DEVICE/DEVICE_DRV_HNDL", "[ethernet]")
         .send_delay_ms = DEFAULT_SEND_DELAY_MS,
     };
     xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL);
-    int n = read(eth_tap_fd, in_buffer, sizeof(in_buffer));
+    int n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE);
     TEST_ASSERT_GREATER_THAN(0, n);
     TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
 
@@ -897,7 +910,7 @@ TEST_CASE("esp32 l2tap - ioctl - INTF_DEVICE/DEVICE_DRV_HNDL", "[ethernet]")
     TEST_ASSERT_NOT_EQUAL(-1, ioctl(eth_tap_fd, L2TAP_G_INTF_DEVICE, &if_key_str));
     TEST_ASSERT_EQUAL_STRING("ETH_DEF", if_key_str);
     xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 10, NULL); // set higher priority, we need to be sure that "send" task closes FD prior main task
-    n = read(eth_tap_fd, in_buffer, sizeof(in_buffer));
+    n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE);
     TEST_ASSERT_GREATER_THAN(0, n);
     TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
 
@@ -922,7 +935,7 @@ TEST_CASE("esp32 l2tap - ioctl - INTF_DEVICE/DEVICE_DRV_HNDL", "[ethernet]")
     TEST_ASSERT_EQUAL(eth_type_filter, eth_type_filter_get);
 
     xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL);
-    n = read(eth_tap_fd, in_buffer, sizeof(in_buffer));
+    n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE);
     TEST_ASSERT_GREATER_THAN(0, n);
     TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
 
@@ -967,7 +980,6 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]")
 {
     test_vfs_eth_network_t eth_network_hndls;
     int eth_tap_fd;
-    char in_buffer[1500] = { 0 };
 
     TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL));
     ethernet_init(&eth_network_hndls);
@@ -996,7 +1008,7 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]")
     };
     // Confirm the read blocks by default
     xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL);
-    int n = read(eth_tap_fd, in_buffer, sizeof(in_buffer));
+    int n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE);
     TEST_ASSERT_GREATER_THAN(0, n);
     TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
 
@@ -1012,7 +1024,7 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]")
     int loop_cnt = 0;
     xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL);
     while (loop_cnt < 100) {
-        if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) {
+        if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) {
             TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
             break;
         } else {
@@ -1039,7 +1051,7 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]")
     loop_cnt = 0;
     xTaskCreate(send_task, "raw_eth_send_task", 1024, &send_task_ctrl, tskIDLE_PRIORITY + 2, NULL);
     while (loop_cnt < 100) {
-        if ((n = read(eth_tap_fd, in_buffer, sizeof(in_buffer))) > 0) {
+        if ((n = read(eth_tap_fd, in_buffer, IN_BUFFER_SIZE)) > 0) {
             TEST_ASSERT_EQUAL_UINT8_ARRAY(&s_test_msg, in_buffer, n);
             break;
         } else {

components/esp_rom/include/esp32/rom/cache.h

@@ -65,7 +65,7 @@ void mmu_init(int cpu_no);
   *                   4 : mmu table to be written is out of range
   *                   5 : vaddr is out of range
   */
-static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num)
+static inline __attribute__((always_inline)) unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num)
 {
     extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num);
 
@@ -118,7 +118,7 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vadd
   *
   * @return None
   */
-static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
+static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Init(int cpu_no)
 {
     extern void Cache_Read_Init_rom(int cpu_no);
     DPORT_STALL_OTHER_CPU_START();
@@ -134,7 +134,7 @@ static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
   *
   * @return None
   */
-static inline void IRAM_ATTR Cache_Flush(int cpu_no)
+static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Flush(int cpu_no)
 {
     extern void Cache_Flush_rom(int cpu_no);
     DPORT_STALL_OTHER_CPU_START();
@@ -150,7 +150,7 @@ static inline void IRAM_ATTR Cache_Flush(int cpu_no)
   *
   * @return None
   */
-static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
+static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Disable(int cpu_no)
 {
     extern void Cache_Read_Disable_rom(int cpu_no);
     DPORT_STALL_OTHER_CPU_START();
@@ -166,7 +166,7 @@ static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
   *
   * @return None
   */
-static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
+static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Enable(int cpu_no)
 {
     extern void Cache_Read_Enable_rom(int cpu_no);
     DPORT_STALL_OTHER_CPU_START();

components/esp_system/debug_stubs.c

@@ -55,7 +55,6 @@ static void esp_dbg_stubs_data_free(void *addr)
 {
     ESP_LOGV(TAG, "%s %p", __func__, addr);
     free(addr);
-    ESP_LOGV(TAG, "%s EXIT %p", __func__, addr);
 }
 
 void esp_dbg_stubs_init(void)

components/esp_system/port/arch/riscv/panic_arch.c

@@ -348,7 +348,6 @@ void panic_arch_fill_info(void *frame, panic_info_t *info)
     info->description = "Exception was unhandled.";
 
     info->addr = (void *) regs->mepc;
-    info->frame = &regs;
 }
 
 static void panic_print_basic_backtrace(const void *frame, int core)

components/esp_system/test/test_backtrace.c

@@ -19,6 +19,7 @@
 #include "esp_intr_alloc.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_uart.h"
+#include "hal/misc.h"
 
 #define SW_ISR_LEVEL_1          7
 #define SW_ISR_LEVEL_3          29
@@ -83,7 +84,7 @@ TEST_CASE("Test backtrace from interrupt watchdog timeout", "[reset_reason][rese
 static void write_char_crash(char c)
 {
     esp_rom_uart_putc(c);
-    *(char*) 0x00000001 = 0;
+    hal_memset((void *)0x00000001, 0, 1);
 }
 
 TEST_CASE("Test backtrace with a ROM function", "[reset_reason][reset=StoreProhibited,SW_CPU_RESET]")

components/hal/esp32/include/hal/clk_tree_ll.h

@@ -127,7 +127,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
 /**
  * @brief Power up APLL circuit
  */
-static inline void clk_ll_apll_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
@@ -136,7 +136,7 @@ static inline void clk_ll_apll_enable(void)
 /**
  * @brief Power down APLL circuit
  */
-static inline void clk_ll_apll_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_apll_disable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
@@ -147,7 +147,7 @@ static inline void clk_ll_apll_disable(void)
  *
  * @return True if APLL is under force power down; otherwise false
  */
-static inline bool clk_ll_apll_is_fpd(void)
+static inline __attribute__((always_inline)) bool clk_ll_apll_is_fpd(void)
 {
     return REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
 }
@@ -160,7 +160,7 @@ static inline bool clk_ll_apll_is_fpd(void)
  * @param[out] sdm1  Frequency adjustment parameter, 0..255
  * @param[out] sdm2  Frequency adjustment parameter, 0..63
  */
-static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
+static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
 {
     *o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV);
     *sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0);
@@ -177,7 +177,7 @@ static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint3
  * @param sdm1  Frequency adjustment parameter, 0..255
  * @param sdm2  Frequency adjustment parameter, 0..63
  */
-static inline void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
+static inline __attribute__((always_inline)) void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
 {
     uint8_t sdm_stop_val_2 = CLK_LL_APLL_SDM_STOP_VAL_2_REV1;
     if (is_rev0) {
@@ -196,7 +196,7 @@ static inline void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t
 /**
  * @brief Set APLL calibration parameters
  */
-static inline void clk_ll_apll_set_calibration(void)
+static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void)
 {
     REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1);
     REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2);
@@ -208,7 +208,7 @@ static inline void clk_ll_apll_set_calibration(void)
  *
  * @return True if calibration is done; otherwise false
  */
-static inline bool clk_ll_apll_calibration_is_done(void)
+static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void)
 {
     return REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END);
 }
@@ -218,7 +218,7 @@ static inline bool clk_ll_apll_calibration_is_done(void)
  *
  * @param mode Used to determine the xtal32k configuration parameters
  */
-static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 {
     // Configure xtal32k
     // Default mode as CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL
@@ -244,7 +244,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 /**
  * @brief Disable the 32kHz crystal oscillator
  */
-static inline void clk_ll_xtal32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
 {
     // Disable xtal32k xpd status
     CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
@@ -255,7 +255,7 @@ static inline void clk_ll_xtal32k_disable(void)
  *
  * @return True if the 32kHz XTAL is enabled
  */
-static inline bool clk_ll_xtal32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
 }
@@ -283,7 +283,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
 }
@@ -296,7 +296,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void)
  * so is not exposed in the code.
  * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
  */
-static inline void clk_ll_rc_fast_d256_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -307,7 +307,7 @@ static inline void clk_ll_rc_fast_d256_enable(void)
  *
  * Disabling this divider could reduce power consumption.
  */
-static inline void clk_ll_rc_fast_d256_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -317,7 +317,7 @@ static inline void clk_ll_rc_fast_d256_disable(void)
  *
  * @return True if the divided output is enabled
  */
-static inline bool clk_ll_rc_fast_d256_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
 }
@@ -325,7 +325,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -333,7 +333,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -343,7 +343,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  *
  * @return True if the digital RC_FAST_CLK is enabled
  */
-static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -351,7 +351,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -359,7 +359,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -367,7 +367,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void)
 /**
  * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -375,7 +375,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
 /**
  * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -385,7 +385,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
  *
  * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
 }
@@ -395,7 +395,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void)
  *
  * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid.
  */
-static inline uint32_t clk_ll_bbpll_get_freq_mhz(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
 {
     // ESP32 BBPLL frequency is determined by the cpu freq sel
     uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
@@ -641,7 +641,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
  *
  * @return Divider. Returns 0 means invalid.
  */
-static inline uint32_t clk_ll_cpu_get_divider_from_apll(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_from_apll(void)
 {
     // APLL path divider choice shares the same register with CPUPERIOD_SEL
     uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
@@ -695,7 +695,7 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so
  *
  * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
  */
-static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -718,7 +718,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -739,7 +739,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
  */
-static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_FAST_CLK_SRC_XTAL_D4:
@@ -759,7 +759,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
  */
-static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -788,7 +788,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  *
  * @return Divider. Divider = (CK8M_DIV_SEL + 1).
  */
-static inline uint32_t clk_ll_rc_fast_get_divider(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1;
 }
@@ -804,7 +804,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  * otherwise there will be a conflict with the low bit, which is used to disable logs
  * in the ROM code.
  */
-static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
     // Read the status of whether disabling logging from ROM code
     uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
@@ -857,7 +857,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3
  *
  * @return The stored APB frequency, in Hz
  */
-static inline uint32_t clk_ll_apb_load_freq_hz(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void)
 {
     // Read from RTC storage register
     uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12;
@@ -875,7 +875,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void)
  *
  * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
     REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
@@ -887,7 +887,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  *
  * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
 {
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }

components/hal/esp32c2/include/hal/clk_tree_ll.h

@@ -82,7 +82,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
 }
@@ -95,7 +95,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void)
  * so is not exposed in the code.
  * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
  */
-static inline void clk_ll_rc_fast_d256_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -106,7 +106,7 @@ static inline void clk_ll_rc_fast_d256_enable(void)
  *
  * Disabling this divider could reduce power consumption.
  */
-static inline void clk_ll_rc_fast_d256_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -116,7 +116,7 @@ static inline void clk_ll_rc_fast_d256_disable(void)
  *
  * @return True if the divided output is enabled
  */
-static inline bool clk_ll_rc_fast_d256_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
 }
@@ -124,7 +124,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -132,7 +132,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -142,7 +142,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  *
  * @return True if the digital RC_FAST_CLK is enabled
  */
-static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -150,7 +150,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -158,7 +158,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -166,7 +166,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void)
 /**
  * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -174,7 +174,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
 /**
  * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -184,7 +184,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
  *
  * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
 }
@@ -388,7 +388,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
  *
  * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
  */
-static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -411,7 +411,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -432,7 +432,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
  */
-static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
@@ -452,7 +452,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
  */
-static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -470,7 +470,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
  *
  * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
@@ -483,7 +483,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  *
  * @return Divider. Divider = (CK8M_DIV_SEL + 1).
  */
-static inline uint32_t clk_ll_rc_fast_get_divider(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1;
 }
@@ -493,7 +493,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  *
  * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
@@ -512,7 +512,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * otherwise there will be a conflict with the low bit, which is used to disable logs
  * in the ROM code.
  */
-static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
     // Read the status of whether disabling logging from ROM code
     uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
@@ -565,7 +565,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3
  *
  * @return The stored APB frequency, in Hz
  */
-static inline uint32_t clk_ll_apb_load_freq_hz(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void)
 {
     // Read from RTC storage register
     uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12;
@@ -583,7 +583,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void)
  *
  * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
     REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
@@ -595,7 +595,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  *
  * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
 {
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }
@@ -605,7 +605,7 @@ static inline uint32_t clk_ll_rtc_slow_load_cal(void)
  *
  * @param rtc_fix_us The value used to correct the time obtained from the rtc timer when the calibration value changes
  */
-static inline void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us)
 {
     REG_WRITE(RTC_FIX_US_LOW_REG, rtc_fix_us);
     REG_WRITE(RTC_FIX_US_HIGH_REG, rtc_fix_us >> 32);
@@ -616,7 +616,7 @@ static inline void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us)
  *
  * @return The value used to correct the time obtained from the rtc timer when the calibration value changes
  */
-static inline uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void)
+static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void)
 {
     return REG_READ(RTC_FIX_US_LOW_REG) | ((uint64_t)REG_READ(RTC_FIX_US_HIGH_REG) << 32);
 }

components/hal/esp32c3/include/hal/clk_tree_ll.h

@@ -81,7 +81,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
  *
  * @param mode Used to determine the xtal32k configuration parameters
  */
-static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 {
     // Configure xtal32k
     clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT();
@@ -100,7 +100,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 /**
  * @brief Disable the 32kHz crystal oscillator
  */
-static inline void clk_ll_xtal32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
 {
     // Set xtal32k xpd to be controlled by software
     SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
@@ -113,7 +113,7 @@ static inline void clk_ll_xtal32k_disable(void)
  *
  * @return True if the 32kHz XTAL is enabled
  */
-static inline bool clk_ll_xtal32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
 {
     uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
     /* If xtal xpd is controlled by software */
@@ -148,7 +148,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
 }
@@ -161,7 +161,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void)
  * so is not exposed in the code.
  * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
  */
-static inline void clk_ll_rc_fast_d256_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -172,7 +172,7 @@ static inline void clk_ll_rc_fast_d256_enable(void)
  *
  * Disabling this divider could reduce power consumption.
  */
-static inline void clk_ll_rc_fast_d256_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -182,7 +182,7 @@ static inline void clk_ll_rc_fast_d256_disable(void)
  *
  * @return True if the divided output is enabled
  */
-static inline bool clk_ll_rc_fast_d256_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
 }
@@ -190,7 +190,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -198,7 +198,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -208,7 +208,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  *
  * @return True if the digital RC_FAST_CLK is enabled
  */
-static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -216,7 +216,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -224,7 +224,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -232,7 +232,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void)
 /**
  * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -240,7 +240,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
 /**
  * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -250,7 +250,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
  *
  * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
 }
@@ -495,7 +495,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
  *
  * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
  */
-static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -518,7 +518,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -539,7 +539,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
  */
-static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
@@ -559,7 +559,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
  */
-static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -577,7 +577,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
  *
  * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
@@ -590,7 +590,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  *
  * @return Divider. Divider = (CK8M_DIV_SEL + 1).
  */
-static inline uint32_t clk_ll_rc_fast_get_divider(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1;
 }
@@ -600,7 +600,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  *
  * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
@@ -619,7 +619,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * otherwise there will be a conflict with the low bit, which is used to disable logs
  * in the ROM code.
  */
-static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
     // Read the status of whether disabling logging from ROM code
     uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
@@ -672,7 +672,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3
  *
  * @return The stored APB frequency, in Hz
  */
-static inline uint32_t clk_ll_apb_load_freq_hz(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void)
 {
     // Read from RTC storage register
     uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12;
@@ -690,7 +690,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void)
  *
  * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
     REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
@@ -702,7 +702,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  *
  * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
 {
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }

components/hal/esp32c6/include/hal/clk_tree_ll.h

@@ -83,7 +83,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
  *
  * @param mode Used to determine the xtal32k configuration parameters
  */
-static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 {
     if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) {
         // No need to configure anything for OSC_SLOW_CLK
@@ -102,7 +102,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 /**
  * @brief Disable the 32kHz crystal oscillator
  */
-static inline void clk_ll_xtal32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
 {
     // Disable xtal32k xpd
     CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
@@ -113,7 +113,7 @@ static inline void clk_ll_xtal32k_disable(void)
  *
  * @return True if the 32kHz XTAL is enabled
  */
-static inline bool clk_ll_xtal32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
 {
     return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1;
 }
@@ -121,7 +121,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void)
 /**
  * @brief Enable the internal oscillator output for RC32K_CLK
  */
-static inline void clk_ll_rc32k_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void)
 {
     // Enable rc32k xpd status
     SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K);
@@ -130,7 +130,7 @@ static inline void clk_ll_rc32k_enable(void)
 /**
  * @brief Disable the internal oscillator output for RC32K_CLK
  */
-static inline void clk_ll_rc32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void)
 {
     // Disable rc32k xpd status
     CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K);
@@ -141,7 +141,7 @@ static inline void clk_ll_rc32k_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void)
 {
     return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1;
 }
@@ -167,7 +167,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
 {
     return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1;
 }
@@ -175,7 +175,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_fosc = 1;
 }
@@ -183,7 +183,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_fosc = 0;
 }
@@ -193,7 +193,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  *
  * @return True if the digital RC_FAST_CLK is enabled
  */
-static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
 {
     return LP_CLKRST.clk_to_hp.icg_hp_fosc;
 }
@@ -201,7 +201,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 /**
  * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1;
 }
@@ -209,7 +209,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
 /**
  * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0;
 }
@@ -219,7 +219,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
  *
  * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
 {
     return LP_CLKRST.clk_to_hp.icg_hp_xtal32k;
 }
@@ -227,7 +227,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void)
 /**
  * @brief Enable the digital RC32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1;
 }
@@ -235,7 +235,7 @@ static inline void clk_ll_rc32k_digi_enable(void)
 /**
  * @brief Disable the digital RC32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0;
 }
@@ -245,7 +245,7 @@ static inline void clk_ll_rc32k_digi_disable(void)
  *
  * @return True if the digital RC32K_CLK is enabled
  */
-static inline bool clk_ll_rc32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void)
 {
     return LP_CLKRST.clk_to_hp.icg_hp_osc32k;
 }
@@ -566,7 +566,7 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divide
  *
  * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK)
  */
-static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC32K:
@@ -589,7 +589,7 @@ static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_s
  *
  * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
 {
     uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel;
     switch (clk_sel) {
@@ -609,7 +609,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
  */
-static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -635,7 +635,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
     uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel;
     switch (clk_sel) {
@@ -657,7 +657,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
  */
-static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_FAST_CLK_SRC_RC_FAST:
@@ -677,7 +677,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
  */
-static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
     uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel;
     switch (clk_sel) {
@@ -695,7 +695,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
  *
  * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
 {
     // No divider on the target
     HAL_ASSERT(divider == 1);
@@ -706,7 +706,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  *
  * @return Divider. Divider = (CK8M_DIV_SEL + 1).
  */
-static inline uint32_t clk_ll_rc_fast_get_divider(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
 {
     // No divider on the target, always return divider = 1
     return 1;
@@ -717,7 +717,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  *
  * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
 {
     // No divider on the target
     HAL_ASSERT(divider == 1);
@@ -734,7 +734,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * otherwise there will be a conflict with the low bit, which is used to disable logs
  * in the ROM code.
  */
-static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
     // Read the status of whether disabling logging from ROM code
     uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
@@ -773,7 +773,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
  *
  * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
     REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
@@ -785,7 +785,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  *
  * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
 {
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }

components/hal/esp32h2/include/hal/clk_tree_ll.h

@@ -80,7 +80,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
 /**
  * @brief Enable the internal oscillator output for LP_PLL_CLK
  */
-static inline void clk_ll_lp_pll_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_lp_pll_enable(void)
 {
     // Enable lp_pll xpd status
     SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_LPPLL);
@@ -89,7 +89,7 @@ static inline void clk_ll_lp_pll_enable(void)
 /**
  * @brief Disable the internal oscillator output for LP_PLL_CLK
  */
-static inline void clk_ll_lp_pll_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_lp_pll_disable(void)
 {
     // Disable lp_pll xpd status
     CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_LPPLL);
@@ -100,7 +100,7 @@ static inline void clk_ll_lp_pll_disable(void)
  *
  * @param mode Used to determine the xtal32k configuration parameters
  */
-static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 {
     if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) {
         // No need to configure anything for OSC_SLOW_CLK
@@ -119,7 +119,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 /**
  * @brief Disable the 32kHz crystal oscillator
  */
-static inline void clk_ll_xtal32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
 {
     // Disable xtal32k xpd
     CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
@@ -130,7 +130,7 @@ static inline void clk_ll_xtal32k_disable(void)
  *
  * @return True if the 32kHz XTAL is enabled
  */
-static inline bool clk_ll_xtal32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
 {
     return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1;
 }
@@ -138,7 +138,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void)
 /**
  * @brief Enable the internal oscillator output for RC32K_CLK
  */
-static inline void clk_ll_rc32k_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void)
 {
     // Enable rc32k xpd status
     SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K);
@@ -147,7 +147,7 @@ static inline void clk_ll_rc32k_enable(void)
 /**
  * @brief Disable the internal oscillator output for RC32K_CLK
  */
-static inline void clk_ll_rc32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void)
 {
     // Disable rc32k xpd status
     CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K);
@@ -158,7 +158,7 @@ static inline void clk_ll_rc32k_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void)
 {
     return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1;
 }
@@ -184,7 +184,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
 {
     return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1;
 }
@@ -192,7 +192,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_fosc = 1;
 }
@@ -200,7 +200,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_fosc = 0;
 }
@@ -210,7 +210,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  *
  * @return True if the digital RC_FAST_CLK is enabled
  */
-static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
 {
     return LP_CLKRST.clk_to_hp.icg_hp_fosc;
 }
@@ -218,7 +218,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 /**
  * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1;
 }
@@ -226,7 +226,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
 /**
  * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0;
 }
@@ -236,7 +236,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
  *
  * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
 {
     return LP_CLKRST.clk_to_hp.icg_hp_xtal32k;
 }
@@ -244,7 +244,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void)
 /**
  * @brief Enable the digital RC32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1;
 }
@@ -252,7 +252,7 @@ static inline void clk_ll_rc32k_digi_enable(void)
 /**
  * @brief Disable the digital RC32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void)
 {
     LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0;
 }
@@ -262,7 +262,7 @@ static inline void clk_ll_rc32k_digi_disable(void)
  *
  * @return True if the digital RC32K_CLK is enabled
  */
-static inline bool clk_ll_rc32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void)
 {
     return LP_CLKRST.clk_to_hp.icg_hp_osc32k;
 }
@@ -455,7 +455,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
  *
  * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK)
  */
-static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC32K:
@@ -478,7 +478,7 @@ static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_s
  *
  * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
 {
     uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel;
     switch (clk_sel) {
@@ -498,7 +498,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
  */
-static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -524,7 +524,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
     uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel;
     switch (clk_sel) {
@@ -546,7 +546,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  *
  * @param in_sel One of the clock sources in soc_lp_pll_clk_src_t
  */
-static inline void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel)
 {
     uint32_t field_value;
     switch (in_sel) {
@@ -568,7 +568,7 @@ static inline void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_lp_pll_clk_src_t values)
  */
-static inline soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void)
+static inline __attribute__((always_inline)) soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void)
 {
     uint32_t clk_sel = REGI2C_READ_MASK(I2C_PMU, I2C_PMU_SEL_PLL8M_REF);
     switch (clk_sel) {
@@ -586,7 +586,7 @@ static inline soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void)
  *
  * @return LP_PLL clock frequency, in MHz
  */
-static inline uint32_t clk_ll_lp_pll_get_freq_mhz(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_lp_pll_get_freq_mhz(void)
 {
     // The target has a fixed 8MHz LP_PLL
     return CLK_LL_PLL_8M_FREQ_MHZ;
@@ -597,7 +597,7 @@ static inline uint32_t clk_ll_lp_pll_get_freq_mhz(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
  */
-static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_FAST_CLK_SRC_RC_FAST:
@@ -620,7 +620,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
  */
-static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
     uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel;
     switch (clk_sel) {
@@ -640,7 +640,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
  *
  * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
 {
     // No divider on the target
     HAL_ASSERT(divider == 1);
@@ -651,7 +651,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  *
  * @return Divider. Divider = (CK8M_DIV_SEL + 1).
  */
-static inline uint32_t clk_ll_rc_fast_get_divider(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
 {
     // No divider on the target, always return divider = 1
     return 1;
@@ -662,7 +662,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  *
  * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
 {
     // No divider on the target
     HAL_ASSERT(divider == 1);
@@ -679,7 +679,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * otherwise there will be a conflict with the low bit, which is used to disable logs
  * in the ROM code.
  */
-static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
     // Read the status of whether disabling logging from ROM code
     uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
@@ -718,7 +718,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
  *
  * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
     REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
@@ -730,7 +730,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  *
  * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
 {
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }

components/hal/esp32h2/include/hal/mmu_ll.h

@@ -119,6 +119,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
  * @return
  *         True for valid
  */
+__attribute__((always_inline))
 static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
 {
     (void)mmu_id;

components/hal/esp32h4/include/hal/clk_tree_ll.h

@@ -77,7 +77,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
  *
  * @param mode Used to determine the xtal32k configuration parameters
  */
-static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 {
     // Configure xtal32k (or only for mode == CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL?)
     clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT();
@@ -96,7 +96,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 /**
  * @brief Disable the 32kHz crystal oscillator
  */
-static inline void clk_ll_xtal32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
 {
     // Set xtal32k xpd to be controlled by software
     SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
@@ -109,7 +109,7 @@ static inline void clk_ll_xtal32k_disable(void)
  *
  * @return True if the 32kHz XTAL is enabled
  */
-static inline bool clk_ll_xtal32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
 {
     uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
     /* If xtal xpd is controlled by software */
@@ -124,7 +124,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void)
 /**
  * @brief Enable the internal oscillator output for RC32K_CLK
  */
-static inline void clk_ll_rc32k_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void)
 {
     // Configure rc32k
     REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, CLK_LL_RC32K_DFREQ_DEFAULT);
@@ -135,7 +135,7 @@ static inline void clk_ll_rc32k_enable(void)
 /**
  * @brief Disable the internal oscillator output for RC32k_CLK
  */
-static inline void clk_ll_rc32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void)
 {
     // Configure rc32k
     REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, CLK_LL_RC32K_DFREQ_DEFAULT);
@@ -146,7 +146,7 @@ static inline void clk_ll_rc32k_disable(void)
 /**
  * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -154,7 +154,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -164,7 +164,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  *
  * @return True if the digital RC_FAST_CLK is enabled
  */
-static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -172,7 +172,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 /**
  * @brief Enable the digital RC32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN_M);
 }
@@ -180,7 +180,7 @@ static inline void clk_ll_rc32k_digi_enable(void)
 /**
  * @brief Disable the digital RC32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN_M);
 }
@@ -190,7 +190,7 @@ static inline void clk_ll_rc32k_digi_disable(void)
  *
  * @return True if the digital RC32K_CLK is enabled
  */
-static inline bool clk_ll_rc32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN);
 }
@@ -198,7 +198,7 @@ static inline bool clk_ll_rc32k_digi_is_enabled(void)
 /**
  * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -206,7 +206,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
 /**
  * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -216,7 +216,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
  *
  * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
 }
@@ -383,7 +383,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
  *
  * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
  */
-static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -406,7 +406,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -427,7 +427,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
  */
-static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
@@ -447,7 +447,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
  */
-static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -465,7 +465,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
  *
  * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
@@ -478,7 +478,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  *
  * @return Divider. Divider = (CK8M_DIV_SEL + 1).
  */
-static inline uint32_t clk_ll_rc_fast_get_divider(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1;
 }
@@ -488,7 +488,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  *
  * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
@@ -507,7 +507,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * otherwise there will be a conflict with the low bit, which is used to disable logs
  * in the ROM code.
  */
-static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
     // Read the status of whether disabling logging from ROM code
     uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
@@ -558,7 +558,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3
  *
  * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
     REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
@@ -570,7 +570,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  *
  * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
 {
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }

components/hal/esp32s2/include/hal/clk_tree_ll.h

@@ -94,7 +94,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
 /**
  * @brief Power up APLL circuit
  */
-static inline void clk_ll_apll_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
@@ -103,7 +103,7 @@ static inline void clk_ll_apll_enable(void)
 /**
  * @brief Power down APLL circuit
  */
-static inline void clk_ll_apll_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_apll_disable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
@@ -117,7 +117,7 @@ static inline void clk_ll_apll_disable(void)
  * @param[out] sdm1  Frequency adjustment parameter, 0..255
  * @param[out] sdm2  Frequency adjustment parameter, 0..63
  */
-static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
+static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
 {
     *o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV);
     *sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0);
@@ -133,7 +133,7 @@ static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint3
  * @param sdm1  Frequency adjustment parameter, 0..255
  * @param sdm2  Frequency adjustment parameter, 0..63
  */
-static inline void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
+static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
 {
     REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
     REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
@@ -146,7 +146,7 @@ static inline void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_
 /**
  * @brief Set APLL calibration parameters
  */
-static inline void clk_ll_apll_set_calibration(void)
+static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void)
 {
     REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1);
     REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2);
@@ -158,7 +158,7 @@ static inline void clk_ll_apll_set_calibration(void)
  *
  * @return True if calibration is done; otherwise false
  */
-static inline bool clk_ll_apll_calibration_is_done(void)
+static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void)
 {
     return REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END);
 }
@@ -168,7 +168,7 @@ static inline bool clk_ll_apll_calibration_is_done(void)
  *
  * @param mode Used to determine the xtal32k configuration parameters
  */
-static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 {
     // Configure xtal32k
     clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT();
@@ -187,7 +187,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 /**
  * @brief Disable the 32kHz crystal oscillator
  */
-static inline void clk_ll_xtal32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
 {
     // Set xtal32k xpd to be controlled by software
     SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
@@ -200,7 +200,7 @@ static inline void clk_ll_xtal32k_disable(void)
  *
  * @return True if the 32kHz XTAL is enabled
  */
-static inline bool clk_ll_xtal32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
 {
     uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
     /* If xtal xpd is controlled by software */
@@ -235,7 +235,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
 }
@@ -248,7 +248,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void)
  * so is not exposed in the code.
  * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
  */
-static inline void clk_ll_rc_fast_d256_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -259,7 +259,7 @@ static inline void clk_ll_rc_fast_d256_enable(void)
  *
  * Disabling this divider could reduce power consumption.
  */
-static inline void clk_ll_rc_fast_d256_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -269,7 +269,7 @@ static inline void clk_ll_rc_fast_d256_disable(void)
  *
  * @return True if the divided output is enabled
  */
-static inline bool clk_ll_rc_fast_d256_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
 }
@@ -277,7 +277,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -285,7 +285,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -295,7 +295,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  *
  * @return True if the digital RC_FAST_CLK is enabled
  */
-static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -303,7 +303,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -311,7 +311,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -319,7 +319,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void)
 /**
  * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -327,7 +327,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
 /**
  * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -337,7 +337,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
  *
  * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
 }
@@ -565,7 +565,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
  *
  * @return Divider. Returns 0 means invalid.
  */
-static inline uint32_t clk_ll_cpu_get_divider_from_apll(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_from_apll(void)
 {
     // APLL path divider choice depends on PLL_FREQ_SEL and CPUPERIOD_SEL
     uint32_t pll_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
@@ -611,7 +611,7 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so
  *
  * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
  */
-static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -634,7 +634,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -655,7 +655,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
  */
-static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_FAST_CLK_SRC_XTAL_D4:
@@ -675,7 +675,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
  */
-static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -693,7 +693,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
  *
  * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
@@ -706,7 +706,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  *
  * @return Divider. Divider = (CK8M_DIV_SEL + 1).
  */
-static inline uint32_t clk_ll_rc_fast_get_divider(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1;
 }
@@ -716,7 +716,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  *
  * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
@@ -747,7 +747,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3
  *
  * @return The stored APB frequency, in Hz
  */
-static inline uint32_t clk_ll_apb_load_freq_hz(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void)
 {
     // Read from RTC storage register
     uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12;
@@ -765,7 +765,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void)
  *
  * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
     REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
@@ -777,7 +777,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  *
  * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
 {
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }

components/hal/esp32s3/include/hal/clk_tree_ll.h

@@ -82,7 +82,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
  *
  * @param mode Used to determine the xtal32k configuration parameters
  */
-static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 {
     // Configure xtal32k
     clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT();
@@ -101,7 +101,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 /**
  * @brief Disable the 32kHz crystal oscillator
  */
-static inline void clk_ll_xtal32k_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
 {
     // Set xtal32k xpd to be controlled by software
     SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
@@ -114,7 +114,7 @@ static inline void clk_ll_xtal32k_disable(void)
  *
  * @return True if the 32kHz XTAL is enabled
  */
-static inline bool clk_ll_xtal32k_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
 {
     uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
     /* If xtal xpd is controlled by software */
@@ -149,7 +149,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
 }
@@ -162,7 +162,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void)
  * so is not exposed in the code.
  * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
  */
-static inline void clk_ll_rc_fast_d256_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -173,7 +173,7 @@ static inline void clk_ll_rc_fast_d256_enable(void)
  *
  * Disabling this divider could reduce power consumption.
  */
-static inline void clk_ll_rc_fast_d256_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
 }
@@ -183,7 +183,7 @@ static inline void clk_ll_rc_fast_d256_disable(void)
  *
  * @return True if the divided output is enabled
  */
-static inline bool clk_ll_rc_fast_d256_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
 }
@@ -191,7 +191,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -199,7 +199,7 @@ static inline void clk_ll_rc_fast_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -209,7 +209,7 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  *
  * @return True if the digital RC_FAST_CLK is enabled
  */
-static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
 {
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
 }
@@ -217,7 +217,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 /**
  * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -225,7 +225,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void)
 /**
  * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M);
 }
@@ -233,7 +233,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void)
 /**
  * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -241,7 +241,7 @@ static inline void clk_ll_xtal32k_digi_enable(void)
 /**
  * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M);
 }
@@ -251,7 +251,7 @@ static inline void clk_ll_xtal32k_digi_disable(void)
  *
  * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
 }
@@ -501,7 +501,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
  *
  * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
  */
-static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
@@ -524,7 +524,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
  */
-static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -546,7 +546,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  *
  * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
  */
-static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
     switch (in_sel) {
     case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
@@ -566,7 +566,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  *
  * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
  */
-static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
     uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
     switch (clk_sel) {
@@ -584,7 +584,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
  *
  * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
@@ -597,7 +597,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  *
  * @return Divider. Divider = (CK8M_DIV_SEL + 1).
  */
-static inline uint32_t clk_ll_rc_fast_get_divider(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
 {
     return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1;
 }
@@ -607,7 +607,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  *
  * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
  */
-static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
 {
     HAL_ASSERT(divider > 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
@@ -626,7 +626,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * otherwise there will be a conflict with the low bit, which is used to disable logs
  * in the ROM code.
  */
-static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
     // Read the status of whether disabling logging from ROM code
     uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
@@ -665,7 +665,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
  *
  * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
     REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
@@ -677,7 +677,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  *
  * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
  */
-static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
 {
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }

components/heap/test_apps/main/test_realloc.c

@@ -20,10 +20,11 @@
 
 TEST_CASE("realloc shrink buffer in place", "[heap]")
 {
-    void *x = malloc(64);
+    // pointers converted to int to avoid warning -Wuse-after-free
+    int x = (int) malloc(64);
     TEST_ASSERT(x);
-    void *y = realloc(x, 48);
-    TEST_ASSERT_EQUAL_PTR(x, y);
+    int y = (int) realloc((void *) x, 48);
+    TEST_ASSERT_EQUAL_UINT32((uint32_t) x, (uint32_t) y);
 }
 
 #endif

components/newlib/port/CMakeLists.txt

@@ -1 +1,5 @@
 target_sources(${COMPONENT_LIB} PRIVATE "${CMAKE_CURRENT_LIST_DIR}/esp_time_impl.c")
+
+if(CONFIG_IDF_TARGET_ARCH_RISCV)
+    target_sources(${COMPONENT_LIB} PRIVATE "${CMAKE_CURRENT_LIST_DIR}/riscv/port_stdatomic.S")
+endif()

components/newlib/port/riscv/port_stdatomic.S

@@ -0,0 +1,659 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#if __riscv_atomic == 1
+
+.macro ALIGNED_PTR_2 ptr, offset
+    andi    \ptr, a0, -4         // aligned ptr
+    sub     \offset, a0, \ptr
+    slli    \offset, \offset, 3  // offset (in bits) between ptr and aligned ptr
+    li      t6, 24
+    bne     \offset, t6, 1f      // do atomic operation in case var is not splited between 2 words
+    lr.w    t2, (a0)             // invokes 'Load access fault!'
+1:
+.endm
+
+    .global __atomic_load_2
+    .type   __atomic_load_2, @function
+__atomic_load_2:
+    ALIGNED_PTR_2 t0, t1
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t4, t2, t1
+    slli    a0, t4, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_load_2, . - __atomic_load_2
+
+
+    .global __atomic_store_2
+    .type   __atomic_store_2, @function
+__atomic_store_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t6, 0xffff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+    sll     t5, a1, t1   // t5 - shifted new value to easy place into aligned memory
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    and     t3, t2, t6   // t3 - masked aliged memory. Atomic variable part is zeroed here
+    or      t4, t5, t3   // t4 - combine desire half-word with half-word from origin aligned memory
+    sc.w    t3, t4, (t0) // t3 - atomic write result (0 - success)
+    bnez    t3, 1b
+    ret
+    .size   __atomic_store_2, . - __atomic_store_2
+
+
+    .global __atomic_exchange_2
+    .type   __atomic_exchange_2, @function
+__atomic_exchange_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t6, 0xffff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+    sll     t5, a1, t1   // t5 - shifted new value to easy place into aligned memory
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    and     t3, t2, t6   // t3 - masked aliged memory. Atomic variable part is zeroed here
+    or      t4, t5, t3   // t4 - combine desire half-word with half-word from origin aligned memory
+    sc.w    t3, t4, (t0) // t3 - atomic write result (0 - success)
+    bnez    t3, 1b
+    srl     t4, t2, t1
+    slli    a0, t4, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_exchange_2, . - __atomic_exchange_2
+
+
+    .global __atomic_compare_exchange_2
+    .type   __atomic_compare_exchange_2, @function
+__atomic_compare_exchange_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t6, 0xffff0000
+    srl     t6, t6, t1   // t6 - bitwise mask (0xffff0000/0x0000ffff)
+    lhu     t5, (a1)
+    sll     t5, t5, t1   // t5 - shifted expect value to easy compare with aligned memory
+    sll     t4, a2, t1   // t4 - shifted desired value to easy place into aligned memory
+1:                       // do not change registers (t0, t1, t4, t5) after this label
+    not     t6, t6
+    lr.w    t2, (t0)     // t2 - load atomic
+    and     t3, t2, t6   // t3 - prepare half-word from aligned memory to compare with expected (t5)
+    bne     t3, t5, 2f
+    not     t6, t6
+    and     t2, t2, t6
+    or      t3, t4, t2   // t3 - combine desire half-word with half-word from origin aligned memory
+    sc.w    t2, t3, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    li      a0, 1
+    ret
+2:
+    srl     t3, t3, t1
+    sh      t3, (a1)     // store atomic value into expect variable
+    li      a0, 0
+    ret
+    .size   __atomic_compare_exchange_2, . - __atomic_compare_exchange_2
+
+
+    .global __atomic_fetch_or_2
+    .type   __atomic_fetch_or_2, @function
+__atomic_fetch_or_2:
+    ALIGNED_PTR_2 t0, t1
+    sll     t2, a1, t1   // t2 - shifted value half-word.
+    amoor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t0, t0, t1
+    slli    a0, t0, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_fetch_or_2, . - __atomic_fetch_or_2
+
+
+    .global __atomic_or_fetch_2
+    .type   __atomic_or_fetch_2, @function
+__atomic_or_fetch_2:
+    ALIGNED_PTR_2 t0, t1
+    sll     t2, a1, t1   // t2 - shifted value half-word.
+    amoor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t2, t2, t1
+    slli    a0, t2, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_or_fetch_2, . - __atomic_or_fetch_2
+
+
+    .global __atomic_fetch_xor_2
+    .type   __atomic_fetch_xor_2, @function
+__atomic_fetch_xor_2:
+    ALIGNED_PTR_2 t0, t1
+    sll     t2, a1, t1    // t2 - shifted value half-word.
+    amoxor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t0, t0, t1
+    slli    a0, t0, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_fetch_xor_2, . - __atomic_fetch_xor_2
+
+
+    .global __atomic_xor_fetch_2
+    .type   __atomic_xor_fetch_2, @function
+__atomic_xor_fetch_2:
+    ALIGNED_PTR_2 t0, t1
+    sll     t2, a1, t1    // t2 - shifted value half-word.
+    amoxor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t2, t2, t1
+    slli    a0, t2, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_xor_fetch_2, . - __atomic_xor_fetch_2
+
+
+    .global __atomic_fetch_and_2
+    .type   __atomic_fetch_and_2, @function
+__atomic_fetch_and_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t6, 0xffff0000  // t6 - bitwise mask
+    srl     t6, t6, t1      // t6 - using to fill non-atomic bytes with 0xff in aligned memory
+    sll     t2, a1, t1      // t2 - shifted value half-word.
+    or      t2, t2, t6      // t2 - 0xXXXXffff or 0xffffXXXX where is value halfword
+    amoand.w   t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t0, t0, t1
+    slli    a0, t0, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_fetch_and_2, . - __atomic_fetch_and_2
+
+
+    .global __atomic_and_fetch_2
+    .type   __atomic_and_fetch_2, @function
+__atomic_and_fetch_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t6, 0xffff0000  // t6 - bitwise mask
+    srl     t6, t6, t1      // t6 - using to fill non-atomic bytes with 0xff in aligned memory
+    sll     t2, a1, t1      // t2 - shifted value half-word.
+    or      t2, t2, t6      // t2 - 0xXXXXffff or 0xffffXXXX where XXXX is value halfword
+    amoand.w   t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t2, t2, t1
+    slli    a0, t2, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_and_fetch_2, . - __atomic_and_fetch_2
+
+
+    .global __atomic_fetch_nand_2
+    .type   __atomic_fetch_nand_2, @function
+__atomic_fetch_nand_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t5, 0xffff
+    sll     t5, t5, t1   // t5 - bitwise mask
+    not     t6, t5       // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t3, t2, t1
+    and     t3, t3, a1
+    not     t3, t3       // t3 - atomic value to write
+    sll     t3, t3, t1
+    and     t4, t2, t6   // t4 - masked aliged memory. Atomic variable part is zeroed here
+    or      t4, t4, t3   // t4 - combine desire byte-word with origin aligned memory
+    sc.w    t4, t4, (t0) // t3 - atomic write result (0 - success)
+    bnez    t4, 1b
+    srl     t4, t2, t1
+    slli    a0, t4, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_fetch_nand_2, . - __atomic_fetch_nand_2
+
+
+    .global __atomic_nand_fetch_2
+    .type   __atomic_nand_fetch_2, @function
+__atomic_nand_fetch_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t5, 0xffff
+    sll     t5, t5, t1   // t5 - bitwise mask
+    not     t6, t5       // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t3, t2, t1
+    and     t3, t3, a1
+    not     t3, t3       // t3 - atomic value to write
+    sll     t3, t3, t1
+    and     t4, t2, t6   // t4 - masked aliged memory. Atomic variable part is zeroed here
+    or      t4, t4, t3   // t4 - combine desire byte-word with origin aligned memory
+    sc.w    t4, t4, (t0) // t3 - atomic write result (0 - success)
+    bnez    t4, 1b
+    srl     t4, t2, t1
+    slli    a0, t3, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_nand_fetch_2, . - __atomic_nand_fetch_2
+
+
+    .global __atomic_fetch_sub_2
+    .type   __atomic_fetch_sub_2, @function
+__atomic_fetch_sub_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t5, 0xffff   // t5 - bitwise mask
+    not     t6, t5
+    srl     t6, t6, t1   // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     a0, t2, t1
+    and     a0, a0, t5   // a0 - value in atomic before performing operation
+    sub     t3, a0, a1
+    and     t3, t3, t5   // t3 - value to be written to atomic
+    sll     t3, t3, t1
+    and     t2, t2, t6
+    or      t3, t3, t2   // t3 - value to be written into aligned memory
+    sc.w    t2, t3, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    ret
+    .size   __atomic_fetch_sub_2, . - __atomic_fetch_sub_2
+
+
+    .global __atomic_sub_fetch_2
+    .type   __atomic_sub_fetch_2, @function
+__atomic_sub_fetch_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t5, 0xffff   // t5 - bitwise mask
+    not     t6, t5
+    srl     t6, t6, t1   // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t4, t2, t1
+    and     t4, t4, t5
+    sub     t4, t4, a1
+    and     t4, t4, t5   // t4 - value to be written to atomic
+    sll     t4, t4, t1
+    and     t2, t2, t6
+    or      t4, t4, t2   // t4 - value to be written into aligned memory
+    sc.w    t2, t4, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    srl     t4, t4, t1
+    slli    a0, t4, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_sub_fetch_2, . - __atomic_sub_fetch_2
+
+
+    .global __atomic_fetch_add_2
+    .type   __atomic_fetch_add_2, @function
+__atomic_fetch_add_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t5, 0xffff   // t5 - bitwise mask
+    not     t6, t5
+    srl     t6, t6, t1   // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t4, t2, t1
+    and     t4, t4, t5   // t4 - half-word value in atomic before performing operation
+    add     t3, t4, a1
+    and     t4, t4, t5   // t3 - half-word value to be written to atomic
+    sll     t3, t3, t1
+    and     t2, t2, t6
+    or      t3, t3, t2   // t3 - value to be written into aligned memory
+    sc.w    t2, t3, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    slli    a0, t4, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_fetch_add_2, . - __atomic_fetch_add_2
+
+
+    .global __atomic_add_fetch_2
+    .type   __atomic_add_fetch_2, @function
+__atomic_add_fetch_2:
+    ALIGNED_PTR_2 t0, t1
+    li      t5, 0xffff   // t5 - bitwise mask
+    not     t6, t5
+    srl     t6, t6, t1   // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t4, t2, t1
+    and     t4, t4, t5
+    add     t4, t4, a1
+    and     t4, t4, t5   // t4 - value to be written to atomic
+    sll     t4, t4, t1
+    and     t2, t2, t6
+    or      t4, t4, t2   // t4 - value to be written into aligned memory
+    sc.w    t2, t4, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    srl     t4, t4, t1
+    slli    a0, t4, 0x10
+    srli    a0, a0, 0x10
+    ret
+    .size   __atomic_add_fetch_2, . - __atomic_add_fetch_2
+
+
+    .global __atomic_load_1
+    .type   __atomic_load_1, @function
+__atomic_load_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t4, t2, t1
+    andi    a0, t4, 0xff
+    ret
+    .size   __atomic_load_1, . - __atomic_load_1
+
+
+    .global __atomic_store_1
+    .type   __atomic_store_1, @function
+__atomic_store_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+    sll     t5, a1, t1   // t5 - shifted new value to easy place into aligned memory
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    and     t3, t2, t6   // t3 - masked aliged memory. Atomic variable part is zeroed here
+    or      t4, t5, t3   // t4 - combine desire byte-word with origin aligned memory
+    sc.w    t3, t4, (t0) // t3 - atomic write result (0 - success)
+    bnez    t3, 1b
+    ret
+    .size   __atomic_store_1, . - __atomic_store_1
+
+
+    .global __atomic_exchange_1
+    .type   __atomic_exchange_1, @function
+__atomic_exchange_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+    sll     t5, a1, t1   // t5 - shifted new value to easy place into aligned memory
+1:                       // do not change registers (t0, t1, t5, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    and     t3, t2, t6   // t3 - masked aliged memory. Atomic variable part is zeroed here
+    or      t4, t5, t3   // t4 - combine desire byte-word with origin aligned memory
+    sc.w    t3, t4, (t0) // t3 - atomic write result (0 - success)
+    bnez    t3, 1b
+    srl     t4, t2, t1
+    andi    a0, t4, 0xff
+    ret
+    .size   __atomic_exchange_1, . - __atomic_exchange_1
+
+
+    .global __atomic_compare_exchange_1
+    .type   __atomic_compare_exchange_1, @function
+__atomic_compare_exchange_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+    lbu     t5, (a1)
+    sll     t5, t5, t1   // t5 - shifted expect value to easy compare with aligned memory
+    sll     t4, a2, t1   // t4 - shifted desired value to easy place into aligned memory
+1:                       // do not change registers (t0, t1, t4, t5) after this label
+    not     t6, t6
+    lr.w    t2, (t0)     // t2 - load atomic
+    and     t3, t2, t6   // t3 - prepare half-word from aligned memory to compare with expected (t5)
+    bne     t3, t5, 2f   // goto fail
+    not     t6, t6
+    and     t2, t2, t6
+    or      t3, t4, t2   // t3 - combine desire half-word with half-word from origin aligned memory
+    sc.w    t2, t3, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b       // retry
+    li      a0, 1
+    ret
+2:
+    srl     t3, t3, t1
+    sb      t3, (a1)     // store atomic value into expect variable
+    li      a0, 0
+    ret
+    .size   __atomic_compare_exchange_1, . - __atomic_compare_exchange_1
+
+
+    .global __atomic_fetch_or_1
+    .type   __atomic_fetch_or_1, @function
+__atomic_fetch_or_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    sll     t2, a1, t1   // t2 - shifted value half-word.
+    amoor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t0, t0, t1
+    andi    a0, t0, 0xff
+    ret
+    .size   __atomic_fetch_or_1, . - __atomic_fetch_or_1
+
+
+    .global __atomic_or_fetch_1
+    .type   __atomic_or_fetch_1, @function
+__atomic_or_fetch_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    sll     t2, a1, t1   // t2 - shifted byte-word value.
+    amoor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t2, t2, t1
+    andi    a0, t2, 0xff
+    ret
+    .size   __atomic_or_fetch_1, . - __atomic_or_fetch_1
+
+
+    .global __atomic_fetch_xor_1
+    .type   __atomic_fetch_xor_1, @function
+__atomic_fetch_xor_1:
+    andi    t0, a0, -4    // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3     // t1 - offset (in bits) between ptr and aligned ptr
+    sll     t2, a1, t1    // t2 - shifted value byte-word.
+    amoxor.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t0, t0, t1
+    andi    a0, t0, 0xff
+    ret
+    .size   __atomic_fetch_xor_1, . - __atomic_fetch_xor_1
+
+
+    .global __atomic_xor_fetch_1
+    .type   __atomic_xor_fetch_1, @function
+__atomic_xor_fetch_1:
+    andi    t0, a0, -4     // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3      // t1 - offset (in bits) between ptr and aligned ptr
+    sll     t2, a1, t1     // t2 - shifted value byte-word.
+    amoxor.w t0, t2, (t0)  // t0 - shifted value before atomic operation performed
+    srl     t2, t2, t1
+    andi    a0, t2, 0xff
+    ret
+    .size   __atomic_xor_fetch_1, . - __atomic_xor_fetch_1
+
+
+    .global __atomic_fetch_and_1
+    .type   __atomic_fetch_and_1, @function
+__atomic_fetch_and_1:
+    andi    t0, a0, -4    // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3
+    li      t6, 0xff      // t6 - bitwise mask
+    sll     t6, t6, t1    // t6 - using to fill non-atomic bytes with 0xff in aligned memory
+    not     t6, t6
+    sll     t2, a1, t1    // t2 - shifted value byte-word.
+    or      t2, t2, t6    // t2 - (0xXXffffff or 0xffXXffff ...) where XX - new value to write
+    amoand.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t0, t0, t1
+    andi    a0, t0, 0xff
+    ret
+    .size   __atomic_fetch_and_1, . - __atomic_fetch_and_1
+
+
+    .global __atomic_and_fetch_1
+    .type   __atomic_and_fetch_1, @function
+__atomic_and_fetch_1:
+    andi    t0, a0, -4    // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3
+    li      t6, 0xff      // t6 - bitwise mask
+    sll     t6, t6, t1    // t6 - using to fill non-atomic bytes with 0xff in aligned memory
+    not     t6, t6
+    sll     t2, a1, t1    // t2 - shifted value byte-word.
+    or      t2, t2, t6    // t2 - (0xXXffffff or 0xffXXffff ...) where XX - new value to write
+    amoand.w t0, t2, (t0) // t0 - shifted value before atomic operation performed
+    srl     t2, t2, t1
+    andi    a0, t2, 0xff
+    ret
+    .size   __atomic_and_fetch_1, . - __atomic_and_fetch_1
+
+
+    .global __atomic_nand_fetch_1
+    .type   __atomic_nand_fetch_1, @function
+__atomic_nand_fetch_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t3, t2, t1
+    and     t3, t3, a1
+    not     t3, t3       // t3 - atomic value to write
+    sll     t3, t3, t1
+    and     t4, t2, t6   // t4 - masked aliged memory. Atomic variable part is zeroed here
+    or      t4, t4, t3   // t4 - combine desire byte-word with origin aligned memory
+    sc.w    t3, t4, (t0) // t3 - atomic write result (0 - success)
+    bnez    t3, 1b
+    srl     t4, t4, t1
+    andi    a0, t4, 0xff
+    ret
+    .size   __atomic_nand_fetch_1, . - __atomic_nand_fetch_1
+
+
+    .global __atomic_fetch_nand_1
+    .type   __atomic_fetch_nand_1, @function
+__atomic_fetch_nand_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t3, t2, t1
+    and     t3, t3, a1
+    not     t3, t3       // t3 - atomic value to write
+    sll     t3, t3, t1
+    and     t4, t2, t6   // t4 - masked aliged memory. Atomic variable part is zeroed here
+    or      t4, t4, t3   // t4 - combine desire byte-word with origin aligned memory
+    sc.w    t3, t4, (t0) // t3 - atomic write result (0 - success)
+    bnez    t3, 1b
+    srl     t4, t2, t1
+    andi    a0, t4, 0xff
+    ret
+    .size   __atomic_fetch_nand_1, . - __atomic_fetch_nand_1
+
+
+    .global __atomic_fetch_sub_1
+    .type   __atomic_fetch_sub_1, @function
+__atomic_fetch_sub_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t4, t2, t1
+    andi    t4, t4, 0xff // t4 - value in atomic before performing operation
+    sub     t3, t4, a1
+    andi    t3, t3, 0xff // t3 - value to be written to atomic
+    sll     t3, t3, t1
+    and     t2, t2, t6
+    or      t3, t3, t2   // t3 - value to be written into aligned memory
+    sc.w    t2, t3, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    andi    a0, t4, 0xff
+    ret
+    .size   __atomic_fetch_sub_1, . - __atomic_fetch_sub_1
+
+
+    .global __atomic_sub_fetch_1
+    .type   __atomic_sub_fetch_1, @function
+__atomic_sub_fetch_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t3, t2, t1
+    andi    t3, t3, 0xff // t3 - value in atomic before performing operation
+    sub     t3, t3, a1
+    andi    t3, t3, 0xff // t3 - value to be written to atomic
+    sll     t3, t3, t1
+    and     t2, t2, t6
+    or      t3, t3, t2   // t3 - value to be written into aligned memory
+    sc.w    t2, t3, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    srl     t3, t3, t1
+    andi    a0, t3, 0xff
+    ret
+    .size   __atomic_sub_fetch_1, . - __atomic_sub_fetch_1
+
+
+    .global __atomic_fetch_add_1
+    .type   __atomic_fetch_add_1, @function
+__atomic_fetch_add_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t4, t2, t1
+    andi    t4, t4, 0xff // t4 - value in atomic before performing operation
+    add     t3, t4, a1
+    andi    t3, t3, 0xff // t3 - value to be written to atomic
+    sll     t3, t3, t1
+    and     t2, t2, t6
+    or      t3, t3, t2   // t3 - value to be written into aligned memory
+    sc.w    t2, t3, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    andi    a0, t4, 0xff
+    ret
+    .size   __atomic_fetch_add_1, . - __atomic_fetch_add_1
+
+
+    .global __atomic_add_fetch_1
+    .type   __atomic_add_fetch_1, @function
+__atomic_add_fetch_1:
+    andi    t0, a0, -4   // t0 - aligned ptr
+    sub     t1, a0, t0
+    slli    t1, t1, 3    // t1 - offset (in bits) between ptr and aligned ptr
+    li      t6, 0xff
+    sll     t6, t6, t1
+    not     t6, t6       // t6 - bitwise mask
+1:                       // do not change registers (t0, t1, t6) after this label
+    lr.w    t2, (t0)     // t2 - load atomic
+    srl     t3, t2, t1
+    andi    t3, t3, 0xff // t3 - value in atomic before performing operation
+    add     t3, t3, a1
+    andi    t3, t3, 0xff // t3 - value to be written to atomic
+    sll     t3, t3, t1
+    and     t2, t2, t6
+    or      t3, t3, t2   // t3 - value to be written into aligned memory
+    sc.w    t2, t3, (t0) // t2 - atomic write result (0 - success)
+    bnez    t2, 1b
+    srl     t3, t3, t1
+    andi    a0, t3, 0xff
+    ret
+    .size   __atomic_add_fetch_1, . - __atomic_add_fetch_1
+
+#endif // if __riscv_atomic == 1

components/newlib/stdatomic.c

@@ -434,6 +434,18 @@ ATOMIC_STORE(1, unsigned char)
 ATOMIC_STORE(2, short unsigned int)
 ATOMIC_STORE(4, unsigned int)
 
+#elif __riscv_atomic == 1
+
+bool CLANG_ATOMIC_SUFFIX(__atomic_always_lock_free) (unsigned int size, const volatile void *) {
+  return size <= sizeof(int);
+}
+CLANG_DECLARE_ALIAS( __atomic_always_lock_free)
+
+bool CLANG_ATOMIC_SUFFIX(__atomic_is_lock_free) (unsigned int size, const volatile void *) {
+  return size <= sizeof(int);
+}
+CLANG_DECLARE_ALIAS( __atomic_is_lock_free)
+
 #endif // !HAS_ATOMICS_32
 
 #if !HAS_ATOMICS_64
@@ -520,3 +532,17 @@ void CLANG_ATOMIC_SUFFIX( __atomic_store ) (size_t size, volatile void *dest, vo
     _ATOMIC_EXIT_CRITICAL(state);
 }
 CLANG_DECLARE_ALIAS( __atomic_store)
+
+bool CLANG_ATOMIC_SUFFIX(__atomic_compare_exchange) (size_t size, volatile void *ptr, void *expected, void *desired, int success_memorder, int failure_memorder) {
+    bool ret = false;
+    unsigned state = _ATOMIC_ENTER_CRITICAL();
+    if (!memcmp((void *)ptr, expected, size)) {
+        memcpy((void *)ptr, (const void *)desired, size);
+        ret = true;
+    } else {
+        memcpy((void *)expected, (const void *)ptr, size);
+    }
+    _ATOMIC_EXIT_CRITICAL(state);
+    return ret;
+}
+CLANG_DECLARE_ALIAS( __atomic_compare_exchange)

components/newlib/test_apps/main/CMakeLists.txt

@@ -3,5 +3,5 @@ idf_component_register(SRCS
                         "test_stdatomic.c"
                         "test_misc.c"
                         "test_file.c"
-                       REQUIRES test_utils
+                       REQUIRES pthread test_utils
                        PRIV_REQUIRES unity vfs)

components/newlib/test_apps/main/test_stdatomic.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -10,6 +10,8 @@
 #include <stdatomic.h>
 #include <stdio.h>
 #include <pthread.h>
+#include "esp_pthread.h"
+#include "freertos/portmacro.h"
 #include "unity.h"
 #include "unity_fixture.h"
 
@@ -30,7 +32,7 @@ TEST_TEAR_DOWN(stdatomic)
 {
 }
 
-TEST(stdatomic, test_64bit_atomics)
+TEST(stdatomic, test_64bit_atomics_fetch_op)
 {
     unsigned long long x64 = 0;
     g_atomic64 = 0;  // calls atomic_store
@@ -40,12 +42,18 @@ TEST(stdatomic, test_64bit_atomics)
     x64 += atomic_fetch_and(&g_atomic64, 0xf0f0f0f0f0f0f0f0ULL);
     x64 += atomic_fetch_sub(&g_atomic64, 0x0f0f0f0f0f0f0f0fULL);
     x64 += atomic_fetch_add(&g_atomic64, 0x2222222222222222ULL);
+#ifndef __clang__
+    x64 += __atomic_fetch_nand_8 (&g_atomic64, 0xAAAAAAAAAAAAAAAAULL, 0);
 
+    TEST_ASSERT_EQUAL_HEX64(0x9797979797979797ULL, x64);
+    TEST_ASSERT_EQUAL_HEX64(0xDDDDDDDDDDDDDDDDULL, g_atomic64);  // calls atomic_load
+#else
     TEST_ASSERT_EQUAL_HEX64(0x6464646464646464ULL, x64);
     TEST_ASSERT_EQUAL_HEX64(0x3333333333333333ULL, g_atomic64);  // calls atomic_load
+#endif
 }
 
-TEST(stdatomic, test_32bit_atomics)
+TEST(stdatomic, test_32bit_atomics_fetch_op)
 {
     unsigned int x32 = 0;
     g_atomic32 = 0;
@@ -55,12 +63,18 @@ TEST(stdatomic, test_32bit_atomics)
     x32 += atomic_fetch_and(&g_atomic32, 0xf0f0f0f0U);
     x32 += atomic_fetch_sub(&g_atomic32, 0x0f0f0f0fU);
     x32 += atomic_fetch_add(&g_atomic32, 0x22222222U);
+#ifndef __clang__
+    x32 += __atomic_fetch_nand_4 (&g_atomic32, 0xAAAAAAAAU, 0);
 
-    TEST_ASSERT_EQUAL_HEX32(0x64646464, x32);
-    TEST_ASSERT_EQUAL_HEX32(0x33333333, g_atomic32);
+    TEST_ASSERT_EQUAL_HEX32(0x97979797U, x32);
+    TEST_ASSERT_EQUAL_HEX32(0xDDDDDDDDU, g_atomic32);
+#else
+    TEST_ASSERT_EQUAL_HEX32(0x64646464U, x32);
+    TEST_ASSERT_EQUAL_HEX32(0x33333333U, g_atomic32);  // calls atomic_load
+#endif
 }
 
-TEST(stdatomic, test_16bit_atomics)
+TEST(stdatomic, test_16bit_atomics_fetch_op)
 {
     unsigned int x16 = 0;
     g_atomic16 = 0;
@@ -70,12 +84,18 @@ TEST(stdatomic, test_16bit_atomics)
     x16 += atomic_fetch_and(&g_atomic16, 0xf0f0);
     x16 += atomic_fetch_sub(&g_atomic16, 0x0f0f);
     x16 += atomic_fetch_add(&g_atomic16, 0x2222);
+#ifndef __clang__
+    x16 += __atomic_fetch_nand_2 (&g_atomic16, 0xAAAA, 0);
 
+    TEST_ASSERT_EQUAL_HEX16(0x9797, x16);
+    TEST_ASSERT_EQUAL_HEX16(0xDDDD, g_atomic16);
+#else
     TEST_ASSERT_EQUAL_HEX16(0x6464, x16);
-    TEST_ASSERT_EQUAL_HEX16(0x3333, g_atomic16);
+    TEST_ASSERT_EQUAL_HEX16(0x3333, g_atomic16);  // calls atomic_load
+#endif
 }
 
-TEST(stdatomic, test_8bit_atomics)
+TEST(stdatomic, test_8bit_atomics_fetch_op)
 {
     unsigned int x8 = 0;
     g_atomic8 = 0;
@@ -85,52 +105,322 @@ TEST(stdatomic, test_8bit_atomics)
     x8 += atomic_fetch_and(&g_atomic8, 0xf0);
     x8 += atomic_fetch_sub(&g_atomic8, 0x0f);
     x8 += atomic_fetch_add(&g_atomic8, 0x22);
+#ifndef __clang__
+    x8 += __atomic_fetch_nand_1 (&g_atomic8, 0xAA, 0);
 
+    TEST_ASSERT_EQUAL_HEX8(0x97, x8);
+    TEST_ASSERT_EQUAL_HEX8(0xDD, g_atomic8);
+#else
     TEST_ASSERT_EQUAL_HEX8(0x64, x8);
-    TEST_ASSERT_EQUAL_HEX16(0x33, g_atomic8);
+    TEST_ASSERT_EQUAL_HEX8(0x33, g_atomic8);  // calls atomic_load
+#endif
 }
 
-static void *exclusion_test_task(void *arg);
-
-TEST(stdatomic, test_exclusion)
+#ifndef __clang__
+TEST(stdatomic, test_64bit_atomics_op_fetch)
 {
-    /* Check 64-bit atomics for exclusion.
-     * Only atomic_fetch_add/sub are checked, since all 64-bit atomics use the
-     * same locking implementation.
-     */
-    g_atomic64 = 0;
-    pthread_t thread1;
-    pthread_t thread2;
-    pthread_create(&thread1, NULL, exclusion_test_task, (void*) 1);
-    pthread_create(&thread2, NULL, exclusion_test_task, (void*) 0);
-    pthread_join(thread1, NULL);
-    pthread_join(thread2, NULL);
+    unsigned long long x64 = 0;
+    g_atomic64 = 0;  // calls atomic_store
 
-    TEST_ASSERT_EQUAL(0, g_atomic64);
+    x64 += __atomic_or_fetch_8 (&g_atomic64, 0x1111111111111111ULL, 0);
+    x64 += __atomic_xor_fetch_8(&g_atomic64, 0x3333333333333333ULL, 0);
+    x64 += __atomic_and_fetch_8(&g_atomic64, 0xf0f0f0f0f0f0f0f0ULL, 0);
+    x64 += __atomic_sub_fetch_8(&g_atomic64, 0x0f0f0f0f0f0f0f0fULL, 0);
+    x64 += __atomic_add_fetch_8(&g_atomic64, 0x2222222222222222ULL, 0);
+    x64 += __atomic_nand_fetch_8(&g_atomic64, 0xAAAAAAAAAAAAAAAAULL, 0);
+
+    TEST_ASSERT_EQUAL_HEX64(0x7575757575757574ULL, x64);
+    TEST_ASSERT_EQUAL_HEX64(0xDDDDDDDDDDDDDDDDULL, g_atomic64);  // calls atomic_load
 }
 
-/* Two threads run in parallel, incrementing and decrementing
- * a single 64-bit variable. In the end the variable should
- * have the same value as at the start.
- */
-static void* exclusion_test_task(void *varg)
+TEST(stdatomic, test_32bit_atomics_op_fetch)
 {
-    int arg = (int) varg;
-    for (int i = 0; i < 1000000; ++i) {
-        if (arg == 0) {
-            atomic_fetch_add(&g_atomic64, 1ULL);
-        } else {
-            atomic_fetch_sub(&g_atomic64, 1ULL);
-        }
-    }
-    return NULL;
+    unsigned int x32 = 0;
+    g_atomic32 = 0;
+
+    x32 += __atomic_or_fetch_4 (&g_atomic32, 0x11111111U, 0);
+    x32 += __atomic_xor_fetch_4(&g_atomic32, 0x33333333U, 0);
+    x32 += __atomic_and_fetch_4(&g_atomic32, 0xf0f0f0f0U, 0);
+    x32 += __atomic_sub_fetch_4(&g_atomic32, 0x0f0f0f0fU, 0);
+    x32 += __atomic_add_fetch_4(&g_atomic32, 0x22222222U, 0);
+    x32 += __atomic_nand_fetch_4 (&g_atomic32, 0xAAAAAAAAU, 0);
+
+    TEST_ASSERT_EQUAL_HEX32(0x75757574U, x32);
+    TEST_ASSERT_EQUAL_HEX32(0xDDDDDDDDU, g_atomic32);
 }
 
+TEST(stdatomic, test_16bit_atomics_op_fetch)
+{
+    unsigned int x16 = 0;
+    g_atomic16 = 0;
+
+    x16 += __atomic_or_fetch_2 (&g_atomic16, 0x1111, 0);
+    x16 += __atomic_xor_fetch_2(&g_atomic16, 0x3333, 0);
+    x16 += __atomic_and_fetch_2(&g_atomic16, 0xf0f0, 0);
+    x16 += __atomic_sub_fetch_2(&g_atomic16, 0x0f0f, 0);
+    x16 += __atomic_add_fetch_2(&g_atomic16, 0x2222, 0);
+    x16 += __atomic_nand_fetch_2 (&g_atomic16, 0xAAAA, 0);
+
+    TEST_ASSERT_EQUAL_HEX16(0x7574, x16);
+    TEST_ASSERT_EQUAL_HEX16(0xDDDD, g_atomic16);
+}
+
+TEST(stdatomic, test_8bit_atomics_op_fetch)
+{
+    unsigned int x8 = 0;
+    g_atomic8 = 0;
+
+    x8 += __atomic_or_fetch_1 (&g_atomic8, 0x11, 0);
+    x8 += __atomic_xor_fetch_1(&g_atomic8, 0x33, 0);
+    x8 += __atomic_and_fetch_1(&g_atomic8, 0xf0, 0);
+    x8 += __atomic_sub_fetch_1(&g_atomic8, 0x0f, 0);
+    x8 += __atomic_add_fetch_1(&g_atomic8, 0x22, 0);
+    x8 += __atomic_nand_fetch_1 (&g_atomic8, 0xAA, 0);
+
+    TEST_ASSERT_EQUAL_HEX8(0x74, x8);
+    TEST_ASSERT_EQUAL_HEX8(0xDD, g_atomic8);
+}
+
+#endif // #ifndef __clang__
+
+
+#define TEST_EXCLUSION(n) TEST(stdatomic, test_ ## n ## bit_exclusion)       \
+{                                                                            \
+    g_atomic ## n = 0;                                                       \
+    pthread_t thread1;                                                       \
+    pthread_t thread2;                                                       \
+    esp_pthread_cfg_t cfg = esp_pthread_get_default_config();                \
+    cfg.pin_to_core = (xPortGetCoreID() + 1) % portNUM_PROCESSORS;           \
+    esp_pthread_set_cfg(&cfg);                                               \
+    pthread_create(&thread1, NULL, exclusion_task_ ## n, (void*) 1);         \
+    cfg.pin_to_core = xPortGetCoreID();                                      \
+    esp_pthread_set_cfg(&cfg);                                               \
+    pthread_create(&thread2, NULL, exclusion_task_ ## n, (void*) 0);         \
+    pthread_join(thread1, NULL);                                             \
+    pthread_join(thread2, NULL);                                             \
+    TEST_ASSERT_EQUAL(0, g_atomic ## n);                                     \
+}
+
+#define TEST_EXCLUSION_TASK(n) static void* exclusion_task_ ## n(void *varg) \
+{                                                                            \
+    int arg = (int) varg;                                                    \
+    for (int i = 0; i < 1000000; ++i) {                                      \
+        if (arg == 0) {                                                      \
+            atomic_fetch_add(&g_atomic ## n, 1ULL);                          \
+        } else {                                                             \
+            atomic_fetch_sub(&g_atomic ## n, 1ULL);                          \
+        }                                                                    \
+    }                                                                        \
+    return NULL;                                                             \
+}
+
+TEST_EXCLUSION_TASK(64)
+TEST_EXCLUSION(64)
+
+TEST_EXCLUSION_TASK(32)
+TEST_EXCLUSION(32)
+
+TEST_EXCLUSION_TASK(16)
+TEST_EXCLUSION(16)
+
+TEST_EXCLUSION_TASK(8)
+TEST_EXCLUSION(8)
+
+
+#define ITER_COUNT 20000
+
+#define TEST_RACE_OPERATION(NAME, LHSTYPE, PRE, POST, INIT, FINAL)           \
+                                                                             \
+static _Atomic LHSTYPE var_##NAME = (INIT);                                  \
+                                                                             \
+static void *test_thread_##NAME (void *arg)                                  \
+{                                                                            \
+  for (int i = 0; i < ITER_COUNT; i++)                                       \
+    {                                                                        \
+      PRE var_##NAME POST;                                                   \
+    }                                                                        \
+  return NULL;                                                               \
+}                                                                            \
+                                                                             \
+TEST(stdatomic, test_ ##NAME)                                                \
+{                                                                            \
+  pthread_t thread_id1;                                                      \
+  pthread_t thread_id2;                                                      \
+  esp_pthread_cfg_t cfg = esp_pthread_get_default_config();                  \
+  cfg.pin_to_core = (xPortGetCoreID() + 1) % portNUM_PROCESSORS;             \
+  esp_pthread_set_cfg(&cfg);                                                 \
+  pthread_create (&thread_id1, NULL, test_thread_##NAME, NULL);              \
+  cfg.pin_to_core = xPortGetCoreID();                                        \
+  esp_pthread_set_cfg(&cfg);                                                 \
+  pthread_create (&thread_id2, NULL, test_thread_##NAME, NULL);              \
+  pthread_join (thread_id1, NULL);                                           \
+  pthread_join (thread_id2, NULL);                                           \
+  TEST_ASSERT_EQUAL((FINAL), var_##NAME);                                    \
+}
+
+TEST_RACE_OPERATION (uint8_add, uint8_t, , += 1, 0, (uint8_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint8_add_3, uint8_t, , += 3, 0, (uint8_t) (6*ITER_COUNT))
+TEST_RACE_OPERATION (uint8_postinc, uint8_t, , ++, 0, (uint8_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint8_preinc, uint8_t, ++, , 0, (uint8_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint8_sub, uint8_t, , -= 1, 0, (uint8_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint8_sub_3, uint8_t, , -= 3, 0, (uint8_t) -(6*ITER_COUNT))
+TEST_RACE_OPERATION (uint8_postdec, uint8_t, , --, 0, (uint8_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint8_predec, uint8_t, --, , 0, (uint8_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint8_mul, uint8_t, , *= 3, 1, (uint8_t) 0x1)
+
+TEST_RACE_OPERATION (uint16_add, uint16_t, , += 1, 0, (uint16_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint16_add_3, uint16_t, , += 3, 0, (uint16_t) (6*ITER_COUNT))
+TEST_RACE_OPERATION (uint16_postinc, uint16_t, , ++, 0, (uint16_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint16_preinc, uint16_t, ++, , 0, (uint16_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint16_sub, uint16_t, , -= 1, 0, (uint16_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint16_sub_3, uint16_t, , -= 3, 0, (uint16_t) -(6*ITER_COUNT))
+TEST_RACE_OPERATION (uint16_postdec, uint16_t, , --, 0, (uint16_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint16_predec, uint16_t, --, , 0, (uint16_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint16_mul, uint16_t, , *= 3, 1, (uint16_t) 0x6D01)
+
+TEST_RACE_OPERATION (uint32_add, uint32_t, , += 1, 0, (uint32_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint32_add_3, uint32_t, , += 3, 0, (uint32_t) (6*ITER_COUNT))
+TEST_RACE_OPERATION (uint32_postinc, uint32_t, , ++, 0, (uint32_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint32_preinc, uint32_t, ++, , 0, (uint32_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint32_sub, uint32_t, , -= 1, 0, (uint32_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint32_sub_3, uint32_t, , -= 3, 0, (uint32_t) -(6*ITER_COUNT))
+TEST_RACE_OPERATION (uint32_postdec, uint32_t, , --, 0, (uint32_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint32_predec, uint32_t, --, , 0, (uint32_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint32_mul, uint32_t, , *= 3, 1, (uint32_t) 0xC1E36D01U)
+
+TEST_RACE_OPERATION (uint64_add, uint64_t, , += 1, 0, (uint64_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint64_add_3, uint64_t, , += 3, 0, (uint64_t) (6*ITER_COUNT))
+TEST_RACE_OPERATION (uint64_add_neg, uint64_t, , += 1, -10000, (uint64_t) (2*ITER_COUNT-10000))
+TEST_RACE_OPERATION (uint64_postinc, uint64_t, , ++, 0, (uint64_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint64_postinc_neg, uint64_t, , ++, -10000, (uint64_t) (2*ITER_COUNT-10000))
+TEST_RACE_OPERATION (uint64_preinc, uint64_t, ++, , 0, (uint64_t) (2*ITER_COUNT))
+TEST_RACE_OPERATION (uint64_preinc_neg, uint64_t, ++, , -10000, (uint64_t) (2*ITER_COUNT-10000))
+TEST_RACE_OPERATION (uint64_sub, uint64_t, , -= 1, 0, (uint64_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint64_sub_3, uint64_t, , -= 3, 0, (uint64_t) -(6*ITER_COUNT))
+TEST_RACE_OPERATION (uint64_sub_neg, uint64_t, , -= 1, 10000, (uint64_t) ((-2*ITER_COUNT)+10000))
+TEST_RACE_OPERATION (uint64_postdec, uint64_t, , --, 0, (uint64_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint64_postdec_neg, uint64_t, , --, 10000, (uint64_t) ((-2*ITER_COUNT)+10000))
+TEST_RACE_OPERATION (uint64_predec, uint64_t, --, , 0, (uint64_t) -(2*ITER_COUNT))
+TEST_RACE_OPERATION (uint64_predec_neg, uint64_t, --, , 10000, (uint64_t) ((-2*ITER_COUNT)+10000))
+TEST_RACE_OPERATION (uint64_mul, uint64_t, , *= 3, 1, (uint64_t) 0x988EE974C1E36D01ULL)
+
+TEST_RACE_OPERATION (float_add, float, , += 1, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (complex_float_add, _Complex float, , += 1, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (float_postinc, float, , ++, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (float_preinc, float, ++, , 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (float_sub, float, , -= 1, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (complex_float_sub, _Complex float, , -= 1, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (float_postdec, float, , --, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (float_predec, float, --, , 0, -(2*ITER_COUNT))
+
+TEST_RACE_OPERATION (double_add, double, , += 1, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (complex_double_add, _Complex double, , += 1, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (double_postinc, double, , ++, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (double_preinc, double, ++, , 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (double_sub, double, , -= 1, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (complex_double_sub, _Complex double, , -= 1, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (double_postdec, double, , --, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (double_predec, double, --, , 0, -(2*ITER_COUNT))
+
+TEST_RACE_OPERATION (long_double_add, long double, , += 1, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (complex_long_double_add, _Complex long double, , += 1, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (long_double_postinc, long double, , ++, 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (long_double_sub, long double, , -= 1, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (long_double_preinc, long double, ++, , 0, (2*ITER_COUNT))
+TEST_RACE_OPERATION (complex_long_double_sub, _Complex long double, , -= 1, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (long_double_postdec, long double, , --, 0, -(2*ITER_COUNT))
+TEST_RACE_OPERATION (long_double_predec, long double, --, , 0, -(2*ITER_COUNT))
+
+
 TEST_GROUP_RUNNER(stdatomic)
 {
-    RUN_TEST_CASE(stdatomic, test_64bit_atomics)
-    RUN_TEST_CASE(stdatomic, test_32bit_atomics)
-    RUN_TEST_CASE(stdatomic, test_16bit_atomics)
-    RUN_TEST_CASE(stdatomic, test_8bit_atomics)
-    RUN_TEST_CASE(stdatomic, test_exclusion)
+    RUN_TEST_CASE(stdatomic, test_64bit_atomics_fetch_op)
+    RUN_TEST_CASE(stdatomic, test_32bit_atomics_fetch_op)
+    RUN_TEST_CASE(stdatomic, test_16bit_atomics_fetch_op)
+    RUN_TEST_CASE(stdatomic, test_8bit_atomics_fetch_op)
+
+#ifndef __clang__
+    RUN_TEST_CASE(stdatomic, test_64bit_atomics_op_fetch)
+    RUN_TEST_CASE(stdatomic, test_32bit_atomics_op_fetch)
+    RUN_TEST_CASE(stdatomic, test_16bit_atomics_op_fetch)
+    RUN_TEST_CASE(stdatomic, test_8bit_atomics_op_fetch)
+#endif
+
+    RUN_TEST_CASE(stdatomic, test_64bit_exclusion)
+    RUN_TEST_CASE(stdatomic, test_32bit_exclusion)
+    RUN_TEST_CASE(stdatomic, test_16bit_exclusion)
+    RUN_TEST_CASE(stdatomic, test_8bit_exclusion)
+
+    RUN_TEST_CASE(stdatomic, test_uint8_add)
+    RUN_TEST_CASE(stdatomic, test_uint8_add_3);
+    RUN_TEST_CASE(stdatomic, test_uint8_postinc);
+    RUN_TEST_CASE(stdatomic, test_uint8_preinc);
+    RUN_TEST_CASE(stdatomic, test_uint8_sub);
+    RUN_TEST_CASE(stdatomic, test_uint8_sub_3);
+    RUN_TEST_CASE(stdatomic, test_uint8_postdec);
+    RUN_TEST_CASE(stdatomic, test_uint8_predec);
+    RUN_TEST_CASE(stdatomic, test_uint8_mul);
+
+    RUN_TEST_CASE(stdatomic, test_uint16_add);
+    RUN_TEST_CASE(stdatomic, test_uint16_add_3);
+    RUN_TEST_CASE(stdatomic, test_uint16_postinc);
+    RUN_TEST_CASE(stdatomic, test_uint16_preinc);
+    RUN_TEST_CASE(stdatomic, test_uint16_sub);
+    RUN_TEST_CASE(stdatomic, test_uint16_sub_3);
+    RUN_TEST_CASE(stdatomic, test_uint16_postdec);
+    RUN_TEST_CASE(stdatomic, test_uint16_predec);
+    RUN_TEST_CASE(stdatomic, test_uint16_mul);
+
+    RUN_TEST_CASE(stdatomic, test_uint32_add);
+    RUN_TEST_CASE(stdatomic, test_uint32_add_3);
+    RUN_TEST_CASE(stdatomic, test_uint32_postinc);
+    RUN_TEST_CASE(stdatomic, test_uint32_preinc);
+    RUN_TEST_CASE(stdatomic, test_uint32_sub);
+    RUN_TEST_CASE(stdatomic, test_uint32_sub_3);
+    RUN_TEST_CASE(stdatomic, test_uint32_postdec);
+    RUN_TEST_CASE(stdatomic, test_uint32_predec);
+    RUN_TEST_CASE(stdatomic, test_uint32_mul);
+
+    RUN_TEST_CASE(stdatomic, test_uint64_add);
+    RUN_TEST_CASE(stdatomic, test_uint64_add_3);
+    RUN_TEST_CASE(stdatomic, test_uint64_add_neg);
+    RUN_TEST_CASE(stdatomic, test_uint64_sub);
+    RUN_TEST_CASE(stdatomic, test_uint64_sub_3);
+    RUN_TEST_CASE(stdatomic, test_uint64_sub_neg);
+    RUN_TEST_CASE(stdatomic, test_uint64_postinc);
+    RUN_TEST_CASE(stdatomic, test_uint64_postinc_neg);
+    RUN_TEST_CASE(stdatomic, test_uint64_preinc);
+    RUN_TEST_CASE(stdatomic, test_uint64_preinc_neg);
+    RUN_TEST_CASE(stdatomic, test_uint64_postdec);
+    RUN_TEST_CASE(stdatomic, test_uint64_postdec_neg);
+    RUN_TEST_CASE(stdatomic, test_uint64_predec);
+    RUN_TEST_CASE(stdatomic, test_uint64_predec_neg);
+    RUN_TEST_CASE(stdatomic, test_uint64_mul);
+
+    RUN_TEST_CASE(stdatomic, test_float_add);
+    RUN_TEST_CASE(stdatomic, test_complex_float_add);
+    RUN_TEST_CASE(stdatomic, test_float_postinc);
+    RUN_TEST_CASE(stdatomic, test_float_preinc);
+    RUN_TEST_CASE(stdatomic, test_float_sub);
+    RUN_TEST_CASE(stdatomic, test_complex_float_sub);
+    RUN_TEST_CASE(stdatomic, test_float_postdec);
+    RUN_TEST_CASE(stdatomic, test_float_predec);
+
+    RUN_TEST_CASE(stdatomic, test_double_add);
+    RUN_TEST_CASE(stdatomic, test_complex_double_add);
+    RUN_TEST_CASE(stdatomic, test_double_postinc);
+    RUN_TEST_CASE(stdatomic, test_double_preinc);
+    RUN_TEST_CASE(stdatomic, test_double_sub);
+    RUN_TEST_CASE(stdatomic, test_complex_double_sub);
+    RUN_TEST_CASE(stdatomic, test_double_postdec);
+    RUN_TEST_CASE(stdatomic, test_double_predec);
+
+    RUN_TEST_CASE(stdatomic, test_long_double_add);
+    RUN_TEST_CASE(stdatomic, test_complex_long_double_add);
+    RUN_TEST_CASE(stdatomic, test_long_double_postinc);
+    RUN_TEST_CASE(stdatomic, test_long_double_preinc);
+    RUN_TEST_CASE(stdatomic, test_long_double_sub);
+    RUN_TEST_CASE(stdatomic, test_complex_long_double_sub);
+    RUN_TEST_CASE(stdatomic, test_long_double_postdec);
+    RUN_TEST_CASE(stdatomic, test_long_double_predec);
 }

components/newlib/test_apps/sdkconfig.defaults

@@ -1,3 +1,5 @@
 CONFIG_UNITY_ENABLE_FIXTURE=y
 CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=n
 CONFIG_UNITY_ENABLE_64BIT=y
+CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=n
+CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=n

components/protocomm/src/transports/protocomm_ble.c

@@ -484,7 +484,7 @@ static void protocomm_ble_cleanup(void)
 
 esp_err_t protocomm_ble_start(protocomm_t *pc, const protocomm_ble_config_t *config)
 {
-    if (!pc || !config || !config->device_name || !config->nu_lookup) {
+    if (!pc || !config || !config->nu_lookup) {
         return ESP_ERR_INVALID_ARG;
     }
 

components/protocomm/src/transports/protocomm_nimble.c

@@ -844,7 +844,7 @@ static void free_gatt_ble_misc_memory(simple_ble_cfg_t *ble_config)
 
 esp_err_t protocomm_ble_start(protocomm_t *pc, const protocomm_ble_config_t *config)
 {
-    if (!pc || !config || !config->device_name || !config->nu_lookup) {
+    if (!pc || !config || !config->nu_lookup) {
         return ESP_ERR_INVALID_ARG;
     }
 

components/ulp/cmake/CMakeLists.txt

@@ -69,6 +69,7 @@ if(ULP_COCPU_IS_RISCV)
     target_include_directories(${ULP_APP_NAME} PRIVATE "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/include"
                                                        "${IDF_PATH}/components/ulp/ulp_riscv/shared/include")
     target_link_options(${ULP_APP_NAME} PRIVATE SHELL:-T ${IDF_PATH}/components/ulp/ld/${IDF_TARGET}.peripherals.ld)
+    target_link_options(${ULP_APP_NAME} PRIVATE "-Wl,--no-warn-rwx-segments")
     target_compile_definitions(${ULP_APP_NAME} PRIVATE IS_ULP_COCPU)
 
 else()

components/ulp/cmake/toolchain-ulp-riscv.cmake

@@ -5,11 +5,11 @@ set(CMAKE_C_COMPILER "riscv32-esp-elf-gcc")
 set(CMAKE_CXX_COMPILER "riscv32-esp-elf-g++")
 set(CMAKE_ASM_COMPILER "riscv32-esp-elf-gcc")
 
-set(CMAKE_C_FLAGS "-Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections"
+set(CMAKE_C_FLAGS "-Os -march=rv32imc_zicsr_zifencei -mdiv -fdata-sections -ffunction-sections"
     CACHE STRING "C Compiler Base Flags")
-set(CMAKE_CXX_FLAGS "-Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections"
+set(CMAKE_CXX_FLAGS "-Os -march=rv32imc_zicsr_zifencei -mdiv -fdata-sections -ffunction-sections"
     CACHE STRING "C++ Compiler Base Flags")
 set(CMAKE_ASM_FLAGS "-march=rv32imc -x assembler-with-cpp"
     CACHE STRING "Assembler Base Flags")
-set(CMAKE_EXE_LINKER_FLAGS "-march=rv32imc --specs=nano.specs --specs=nosys.specs"
+set(CMAKE_EXE_LINKER_FLAGS "-march=rv32imc_zicsr_zifencei --specs=nano.specs --specs=nosys.specs"
     CACHE STRING "Linker Base Flags")

components/vfs/vfs_semihost.c

@@ -326,7 +326,7 @@ static DIR* vfs_semihost_opendir(void* ctx, const char *restrict path)
         return NULL;
     }
 
-    strncpy(semihost_dirp->path, path, MIN(strlen(path), sizeof(semihost_dirp->path) - 1));
+    strncpy(semihost_dirp->path, path, sizeof(semihost_dirp->path) - 1);
     ESP_LOGV(TAG, "%s: '%s'", __func__, path);
     int ret_fd = semihosting_opendir(path, (int)&semihost_dirp->id);
     if (ret_fd < 0) {

components/wpa_supplicant/src/common/bss.c

@@ -109,7 +109,7 @@ static int wpa_bss_known(struct wpa_supplicant *wpa_s, struct wpa_bss *bss)
 {
 	struct wifi_ssid *ssid = esp_wifi_sta_get_prof_ssid_internal();
 
-	if (ssid->ssid == NULL || ssid->len == 0)
+	if (ssid->len == 0)
 		return 0;
 	if (ssid->len == bss->ssid_len &&
 	    os_memcmp(ssid->ssid, bss->ssid, ssid->len) == 0)

components/wpa_supplicant/src/tls/pkcs1.c

@@ -322,8 +322,6 @@ int pkcs1_v15_sig_ver(struct crypto_public_key *pk,
 		return -1;
 	}
 
-	os_free(decrypted);
-
 	if (hdr.payload + hdr.length != decrypted + decrypted_len) {
 		wpa_printf(MSG_INFO,
 			   "PKCS #1: Extra data after signature - reject");
@@ -332,8 +330,10 @@ int pkcs1_v15_sig_ver(struct crypto_public_key *pk,
 			    hdr.payload + hdr.length,
 			    decrypted + decrypted_len - hdr.payload -
 			    hdr.length);
+		os_free(decrypted);
 		return -1;
 	}
 
+	os_free(decrypted);
 	return 0;
 }