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xtensa: update header file
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@@ -42,8 +42,10 @@ const xtensa_perfmon_select_t xtensa_perfmon_select_table[] = {
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{XTPERF_CNT_OUTBOUND_PIF, "Outbound PIF"},
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{XTPERF_CNT_INBOUND_PIF, "Inbound PIF"},
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{XTPERF_CNT_PREFETCH, "Prefetch"},
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#if XCHAL_HW_VERSION >= 270004
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{XTPERF_CNT_IDMA, "iDMA"},
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{XTPERF_CNT_INSN_LENGTH, "Length of Instructions"},
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#endif
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{-1, ""},
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};
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@@ -157,6 +159,7 @@ const xtensa_perfmon_masks_t xtensa_perfmon_masks_table[] = {
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{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_MISS, "I prefetch-buffer-lookup miss"},
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{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_MISS, "D prefetch-buffer-lookup miss"},
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{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_L1_FILL, "Direct fill to (L1) Data Cache (unused)"},
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#if XCHAL_HW_VERSION >= 270004
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{XTPERF_CNT_IDMA, XTPERF_MASK_IDMA_ACTIVE_CYCLES, "active cycles"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_16, "16-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_24, "24-bit"},
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@@ -173,6 +176,7 @@ const xtensa_perfmon_masks_t xtensa_perfmon_masks_table[] = {
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_112, "112-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_120, "120-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_128, "128-bit"},
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#endif
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{-1, 0, ""},
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};
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@@ -281,6 +285,7 @@ const uint32_t xtensa_perfmon_select_mask_all[MAX_PERFMON_EVENTS * 2] = {
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XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_MISS,
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XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_MISS,
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XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_L1_FILL,
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#if XCHAL_HW_VERSION >= 270004
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XTPERF_CNT_IDMA, XTPERF_MASK_IDMA_ALL,
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XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_16,
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XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_24,
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@@ -297,4 +302,5 @@ const uint32_t xtensa_perfmon_select_mask_all[MAX_PERFMON_EVENTS * 2] = {
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XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_112,
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XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_120,
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XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_128
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#endif
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};
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