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feat(esp_tee): Support for ESP32-H2 - the rest of the components

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Laukik Hase
2025-05-20 16:31:23 +05:30
parent 958f4b8900
commit 12e2df2d74
14 changed files with 136 additions and 19 deletions
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components/soc/esp32h2/include/soc/interrupt_reg.h
+21 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,16 +9,36 @@
#include "soc/plic_reg.h"
#include "soc/soc_caps.h"
#ifdef __has_include
# if __has_include("sdkconfig.h")
# include "sdkconfig.h"
# endif
#endif
#if CONFIG_SECURE_ENABLE_TEE
#define INTERRUPT_PRIO_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_UXINT_THRESH_REG
#else
#define INTERRUPT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_MXINT_THRESH_REG
#endif
/**
* ESP32H2 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y)
* Keep the following macros for backward compatibility reasons
*/
#if CONFIG_SECURE_ENABLE_TEE
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_UXINT_ENABLE_REG
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_UXINT_THRESH_REG
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_UXINT_CLEAR_REG
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_UXINT_TYPE_REG
#define INTC_INT_PRIO_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
#else
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG
#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#endif
#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE