feat(esp_hal_rtc_timer): introduce new RTC timer component and refactor existing timer functions

components/esp_hal_pmu/CMakeLists.txt

@@ -23,5 +23,5 @@ endif()
 
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS ${public_include}
-                       REQUIRES soc hal esp_rom
+                       REQUIRES soc hal esp_rom esp_hal_rtc_timer
                        LDFRAGMENTS linker.lf)

components/esp_hal_pmu/esp32/include/hal/rtc_cntl_ll.h

@@ -11,16 +11,14 @@
 #include "hal/clk_tree_ll.h"
 #include "esp_rom_sys.h"
 #include "hal/assert.h"
+#include "hal/rtc_timer_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
-{
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_set_wakeup_timer(t)    rtc_timer_ll_set_wakeup_timer(t)
 
 FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
 {
@@ -87,23 +85,8 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
     SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
 }
 
-FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
-{
-    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
-    int attempts = 1000;
-    while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
-        esp_rom_delay_us(1);
-        if (attempts) {
-            if (--attempts == 0 && clk_ll_xtal32k_digi_is_enabled()) {
-                esp_rom_printf("32KHz xtal has been stopped\n");
-            }
-        }
-    }
-    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR);
-    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
-    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
-    return t;
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_get_rtc_time()         rtc_timer_ll_get_rtc_time()
 
 FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
 {

components/esp_hal_pmu/esp32c2/include/hal/rtc_cntl_ll.h

@@ -10,19 +10,14 @@
 #include "soc/rtc_cntl_reg.h"
 #include "soc/syscon_reg.h"
 #include "esp_attr.h"
+#include "hal/rtc_timer_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
-{
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
-
-    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
-    SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_set_wakeup_timer(t)    rtc_timer_ll_set_wakeup_timer(t)
 
 FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
 {
@@ -65,13 +60,8 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
     SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
 }
 
-FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
-{
-    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
-    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
-    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
-    return t;
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_get_rtc_time()         rtc_timer_ll_get_rtc_time()
 
 FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
 {

components/esp_hal_pmu/esp32c3/include/hal/rtc_cntl_ll.h

@@ -10,19 +10,14 @@
 #include "soc/rtc_cntl_reg.h"
 #include "soc/syscon_reg.h"
 #include "esp_attr.h"
+#include "hal/rtc_timer_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
-{
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
-
-    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
-    SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_set_wakeup_timer(t)    rtc_timer_ll_set_wakeup_timer(t)
 
 FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
 {
@@ -71,13 +66,8 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
     SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
 }
 
-FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
-{
-    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
-    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
-    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
-    return t;
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_get_rtc_time()         rtc_timer_ll_get_rtc_time()
 
 FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
 {

components/esp_hal_pmu/esp32s2/include/hal/rtc_cntl_ll.h

@@ -10,19 +10,14 @@
 #include "soc/rtc_cntl_reg.h"
 #include "esp_attr.h"
 #include "hal/assert.h"
+#include "hal/rtc_timer_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
-{
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
-
-    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
-    SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_set_wakeup_timer(t)    rtc_timer_ll_set_wakeup_timer(t)
 
 FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
 {
@@ -85,13 +80,8 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
     SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
 }
 
-FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
-{
-    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
-    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
-    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
-    return t;
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_get_rtc_time()         rtc_timer_ll_get_rtc_time()
 
 FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
 {

components/esp_hal_pmu/esp32s3/include/hal/rtc_cntl_ll.h

@@ -11,6 +11,7 @@
 #include "soc/syscon_reg.h"
 #include "esp_attr.h"
 #include "hal/assert.h"
+#include "hal/rtc_timer_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -19,14 +20,8 @@ extern "C" {
 #define RTC_CNTL_LL_RETENTION_TARGET_CPU         (BIT(0))
 #define RTC_CNTL_LL_RETENTION_TARGET_TAGMEM      (BIT(1))
 
-FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
-{
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
-    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
-
-    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
-    SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_set_wakeup_timer(t)    rtc_timer_ll_set_wakeup_timer(t)
 
 FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
 {
@@ -166,13 +161,8 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
     SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
 }
 
-FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
-{
-    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
-    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
-    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
-    return t;
-}
+// RTC timer functions moved to esp_hal_rtc_timer component
+#define rtc_cntl_ll_get_rtc_time()         rtc_timer_ll_get_rtc_time()
 
 FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
 {

components/esp_hal_pmu/include/hal/rtc_hal.h

@@ -83,31 +83,20 @@ typedef struct rtc_cntl_sleep_retent {
 #endif // SOC_PM_SUPPORT_EXT1_WAKEUP
 
 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0) && SOC_DEEP_SLEEP_SUPPORTED
-
 #define rtc_hal_gpio_get_wakeup_status()                  rtc_cntl_ll_gpio_get_wakeup_status()
-
 #define rtc_hal_gpio_clear_wakeup_status()                rtc_cntl_ll_gpio_clear_wakeup_status()
-
 #endif
 
-#define rtc_hal_set_wakeup_timer(ticks)                   rtc_cntl_ll_set_wakeup_timer(ticks)
-
 void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next);
 
 #if SOC_PM_SUPPORT_CPU_PD
-
 void rtc_cntl_hal_enable_cpu_retention(void *addr);
-
 void rtc_cntl_hal_disable_cpu_retention(void *addr);
-
 #endif
 
 #if SOC_PM_SUPPORT_TAGMEM_PD
-
 void rtc_cntl_hal_enable_tagmem_retention(void *addr);
-
 void rtc_cntl_hal_disable_tagmem_retention(void *addr);
-
 #endif
 
 /*

components/esp_hal_rtc_timer/CMakeLists.txt

@@ -0,0 +1,11 @@
+idf_build_get_property(target IDF_TARGET)
+if(${target} STREQUAL "linux")
+    return() # This component is not supported by the POSIX/Linux simulator
+endif()
+
+set(srcs)
+set(public_include "include" "${target}/include")
+
+idf_component_register(SRCS ${srcs}
+                       INCLUDE_DIRS ${public_include}
+                       REQUIRES soc hal esp_rom)

components/esp_hal_rtc_timer/README.md

@@ -0,0 +1,29 @@
+# ESP Hardware Abstraction Layer for RTC Timer Peripherals
+
+> [!NOTE]
+> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
+
+## Overview
+
+The `esp_hal_rtc_timer` component provides a **unified Hardware Abstraction Layer** for RTC Timer peripherals across all ESP-IDF supported targets. This HAL abstracts hardware differences between legacy RTC timer implementations (in RTC_CNTL peripheral) and modern low-power timer implementations, providing a consistent API for wakeup timer configuration and RTC time reading across different ESP chip families.
+
+The component consolidates timer functionality from two different hardware implementations:
+- **RTC_TIMER_LL_HARDWARE_V1**: Legacy RTC timer functionality in RTC_CNTL peripheral (ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3)
+- **RTC_TIMER_LL_HARDWARE_V2**: Newer LP timer peripheral
+
+## Hardware Version Abstraction
+
+The component uses hardware version macros defined in LL headers to automatically select the correct implementation:
+
+- **RTC_TIMER_LL_HARDWARE_V1**: Defined in LL headers for legacy chips (ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3)
+- **RTC_TIMER_LL_HARDWARE_V2**: Defined in LL headers for modern chips (ESP32C5, ESP32C6, ESP32C61, ESP32H2, ESP32H21, ESP32H4, ESP32P4)
+
+### Unified HAL API (All Chips)
+- Wakeup timer configuration via `rtc_timer_hal_set_wakeup_timer()`
+- RTC time reading via `rtc_timer_hal_get_cycle_count()`
+
+### Hardware-Specific LL API
+- **V1 Chips**: Direct register access in RTC_CNTL peripheral
+- **V2 Chips**: LP Timer peripheral with alarm target configuration and counter snapshot operations
+
+Please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change.

components/esp_hal_rtc_timer/esp32/include/hal/rtc_timer_ll.h

@@ -0,0 +1,45 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "esp_attr.h"
+#include "hal/clk_tree_ll.h"
+#include "esp_rom_sys.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
+{
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
+}
+
+FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
+{
+    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
+    int attempts = 1000;
+    while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
+        esp_rom_delay_us(1);
+        if (attempts) {
+            if (--attempts == 0 && clk_ll_xtal32k_digi_is_enabled()) {
+                esp_rom_printf("32KHz xtal has been stopped\n");
+            }
+        }
+    }
+    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR);
+    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
+    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
+    return t;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_rtc_timer/esp32c2/include/hal/rtc_timer_ll.h

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/syscon_reg.h"
+#include "esp_attr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
+{
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
+
+    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
+    SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
+}
+
+FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
+{
+    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
+    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
+    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
+    return t;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_rtc_timer/esp32c3/include/hal/rtc_timer_ll.h

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/syscon_reg.h"
+#include "esp_attr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
+{
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
+
+    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
+    SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
+}
+
+FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
+{
+    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
+    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
+    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
+    return t;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_rtc_timer/esp32s2/include/hal/rtc_timer_ll.h

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "esp_attr.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
+{
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
+
+    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
+    SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
+}
+
+FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
+{
+    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
+    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
+    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
+    return t;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_rtc_timer/esp32s3/include/hal/rtc_timer_ll.h

@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/syscon_reg.h"
+#include "esp_attr.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
+{
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
+
+    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
+    SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
+}
+
+FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
+{
+    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
+    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
+    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
+    return t;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_rtc_timer/include/hal/rtc_timer_hal.h

@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
+#include "hal/rtc_timer_ll.h"
+#endif
+
+#if SOC_LP_TIMER_SUPPORTED
+#include "hal/lp_timer_hal.h"
+#include "hal/lp_timer_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set wakeup timer value (for legacy chips with RTC_CNTL)
+ *
+ * @param ticks Timer value in RTC slow clock ticks
+ */
+#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
+#define rtc_timer_hal_set_wakeup_timer(ticks)                   rtc_timer_ll_set_wakeup_timer(ticks)
+#elif SOC_LP_TIMER_SUPPORTED
+#define rtc_timer_hal_set_wakeup_timer(ticks)                   lp_timer_hal_set_alarm_target(0, ticks)
+#else
+#error "RTC timer not supported on this target"
+#endif
+
+/**
+ * @brief Get current RTC time (for legacy chips with RTC_CNTL)
+ *
+ * @return Current RTC time in RTC slow clock ticks
+ */
+#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
+#define rtc_timer_hal_get_rtc_time()                            rtc_timer_ll_get_rtc_time()
+#elif SOC_LP_TIMER_SUPPORTED
+#define rtc_timer_hal_get_rtc_time()                            lp_timer_hal_get_cycle_count()
+#else
+#error "RTC timer not supported on this target"
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_rtc_timer/linker.lf

@@ -0,0 +1,5 @@
+[mapping:esp_hal_rtc_timer]
+archive: libesp_hal_rtc_timer.a
+entries:
+    if SOC_LP_TIMER_SUPPORTED = y:
+        lp_timer_hal (noflash)

components/esp_hw_support/CMakeLists.txt

@@ -9,7 +9,7 @@ if(${target} STREQUAL "linux")
     return()
 endif()
 
-set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu)
+set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_rtc_timer)
 # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
 set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_security)
 

components/hal/CMakeLists.txt

@@ -15,10 +15,6 @@ if(CONFIG_SOC_EFUSE_SUPPORTED)
     list(APPEND srcs "efuse_hal.c" "${target}/efuse_hal.c")
 endif()
 
-if(CONFIG_SOC_LP_TIMER_SUPPORTED)
-    list(APPEND srcs "lp_timer_hal.c")
-endif()
-
 if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
     if(CONFIG_SOC_MMU_PERIPH_NUM)
         list(APPEND srcs "mmu_hal.c")

components/ulp/CMakeLists.txt

@@ -98,5 +98,5 @@ idf_component_register(
     SRCS ${srcs}
     INCLUDE_DIRS ${includes}
     REQUIRES esp_adc esp_driver_gpio esp_driver_uart esp_driver_i2s
-             esp_hal_i2c esp_hal_touch_sens esp_hal_gpspi esp_hal_pmu
+             esp_hal_i2c esp_hal_touch_sens esp_hal_gpspi esp_hal_pmu esp_hal_rtc_timer
 )