Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feature/move_esp_timer_related_inits_into_component' into 'master'

Browse Source 
feat(esp_timer): Move esp_timer-related init steps into the component

Closes IDF-8755

See merge request espressif/esp-idf!28664
This commit is contained in:
Konstantin Kondrashov
2024-02-20 16:49:31 +08:00
parent 9605f9be3f d348258f2c
commit 1253ab6e27
12 changed files with 91 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tools/test_apps/system/esp_intr_dump/expected_output/esp32.txt
+5 -5
View File
@@ -3,17 +3,17 @@ CPU 0 interrupt status:
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: TG0_LACT_LEVEL
3 1 Level Used: FROM_CPU0
4 1 Level Reserved
5 1 Level Reserved
6 1 Level Reserved
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: FROM_CPU0
9 1 Level Used: TG0_WDT_LEVEL
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: TG0_WDT_LEVEL
13 1 Level Used: UART0
12 1 Level Used: UART0
13 1 Level Free
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
@@ -66,5 +66,5 @@ CPU 1 interrupt status:
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 17
Interrupts available for general use: 18
Shared interrupts: 0
tools/test_apps/system/esp_intr_dump/expected_output/esp32c3.txt
+6 -6
View File
@@ -3,14 +3,14 @@ CPU 0 interrupt status:
0 * * Reserved
1 * * Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: SYSTIMER_TARGET2_EDGE
4 1 Level Used: FROM_CPU_INTR0
3 1 Level Used: FROM_CPU_INTR0
4 1 Level Used: SYSTIMER_TARGET0_EDGE
5 * * Reserved
6 * * Reserved
7 1 Level Used: SYSTIMER_TARGET0_EDGE
7 1 Level Used: TG0_WDT_LEVEL
8 * * Reserved
9 1 Level Used: TG0_WDT_LEVEL
10 1 Level Used: UART0
9 1 Level Used: UART0
10 * * Free
11 * * Free
12 * * Free
13 * * Free
@@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 17
Interrupts available for general use: 18
Shared interrupts: 0
tools/test_apps/system/esp_intr_dump/expected_output/esp32c6.txt
+6 -6
View File
@@ -9,11 +9,11 @@ CPU 0 interrupt status:
6 * * Reserved
7 * * Reserved
8 * * Reserved
9 1 Level Used: SYSTIMER_TARGET2
10 1 Level Used: CPU_FROM_CPU_0
11 1 Level Used: SYSTIMER_TARGET0
12 1 Level Used: TG0_WDT
13 1 Level Used: UART0
9 1 Level Used: CPU_FROM_CPU_0
10 1 Level Used: SYSTIMER_TARGET0
11 1 Level Used: TG0_WDT
12 1 Level Used: UART0
13 * * Free
14 * * Free
15 * * Free
16 * * Free
@@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 15
Interrupts available for general use: 16
Shared interrupts: 0
tools/test_apps/system/esp_intr_dump/expected_output/esp32h2.txt
+6 -6
View File
@@ -9,11 +9,11 @@ CPU 0 interrupt status:
6 * * Reserved
7 * * Reserved
8 * * Reserved
9 1 Level Used: SYSTIMER_TARGET2
10 1 Level Used: CPUFROM_CPU_0
11 1 Level Used: SYSTIMER_TARGET0
12 1 Level Used: TG0_WDT
13 1 Level Used: UART0
9 1 Level Used: CPUFROM_CPU_0
10 1 Level Used: SYSTIMER_TARGET0
11 1 Level Used: TG0_WDT
12 1 Level Used: UART0
13 * * Free
14 * * Free
15 * * Free
16 * * Free
@@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 15
Interrupts available for general use: 16
Shared interrupts: 0
tools/test_apps/system/esp_intr_dump/expected_output/esp32s2.txt
+1 -1
View File
@@ -10,7 +10,7 @@ CPU 0 interrupt status:
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: TG0_WDT_LEVEL
10 1 Edge Used: SYSTIMER_TARGET2
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: UART0
13 1 Level Free
tools/test_apps/system/esp_intr_dump/expected_output/esp32s3.txt
+6 -6
View File
@@ -3,21 +3,21 @@ CPU 0 interrupt status:
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: SYSTIMER_TARGET2
3 1 Level Used: FROM_CPU_INTR0
4 1 Level Reserved
5 1 Level Reserved
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: FROM_CPU_INTR0
9 1 Level Used: SYSTIMER_TARGET0
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: SYSTIMER_TARGET0
13 1 Level Used: TG0_WDT_LEVEL
12 1 Level Used: TG0_WDT_LEVEL
13 1 Level Used: UART0
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Used: UART0
17 1 Level Free
18 1 Level Free
19 2 Level Free
20 2 Level Free
@@ -66,5 +66,5 @@ CPU 1 interrupt status:
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 15
Interrupts available for general use: 16
Shared interrupts: 0
tools/test_apps/system/panic/main/test_panic.c
+11 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@@ -64,10 +64,18 @@ void test_task_wdt_cpu0(void)
}
__attribute__((optimize("-O0")))
static void test_hw_stack_guard_cpu(void* arg)
{
uint32_t buf[256];
test_hw_stack_guard_cpu(arg);
}
void test_hw_stack_guard_cpu0(void)
{
uint32_t buf[128];
test_hw_stack_guard_cpu0();
xTaskCreatePinnedToCore(test_hw_stack_guard_cpu, "HWSG0", 512, NULL, 1, NULL, 0);
while (true) {
vTaskDelay(100);
}
}
#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY