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feat(esp_hw_support): support esp32s31 clock tree management

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This commit is contained in:
wuzhenghui
2026-07-22 16:32:12 +08:00
parent ade59336b6
commit 11ccd4c304
23 changed files with 794 additions and 226 deletions
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components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h
+39
View File
@@ -271,6 +271,19 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_50m_clk_en(bool enable)
_clk_gate_ll_ref_50m_clk_en(__VA_ARGS__); \
} while(0)
/**
* Enable or disable the clock gate for ref_60m.
* @param enable Enable / disable
*/
FORCE_INLINE_ATTR void _clk_gate_ll_ref_60m_clk_en(bool enable)
{
HP_SYS_CLKRST.ref_60m_ctrl0.reg_ref_60m_clk_en = enable;
}
#define clk_gate_ll_ref_60m_clk_en(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_clk_gate_ll_ref_60m_clk_en(__VA_ARGS__); \
} while (0)
/**
* Enable or disable the clock gate for ref_80m (derived from BBPLL).
* @param enable Enable / disable
@@ -286,6 +299,32 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_80m_clk_en(bool enable)
_clk_gate_ll_ref_80m_clk_en(__VA_ARGS__); \
} while(0)
/**
* Enable or disable the ref_80m mux clock gate.
* @param en 0: disable 1: enable
*/
FORCE_INLINE_ATTR void _clk_gate_ll_ref_80m_mux_clk_en(bool en)
{
HP_SYS_CLKRST.ref_80m_ctrl0.reg_ref_80m_mux_clk_en = en;
}
#define clk_gate_ll_ref_80m_mux_clk_en(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_clk_gate_ll_ref_80m_mux_clk_en(__VA_ARGS__); \
} while (0)
/**
* Enable or disable the clock gate for ref_120m.
* @param enable Enable / disable
*/
FORCE_INLINE_ATTR void _clk_gate_ll_ref_120m_clk_en(bool enable)
{
HP_SYS_CLKRST.ref_120m_ctrl0.reg_ref_120m_clk_en = enable;
}
#define clk_gate_ll_ref_120m_clk_en(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_clk_gate_ll_ref_120m_clk_en(__VA_ARGS__); \
} while (0)
/**
* Enable or disable the clock gate for ref_160m (derived from BBPLL).
* @param enable Enable / disable
components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h
+73
View File
@@ -29,7 +29,9 @@
#define CLK_LL_PLL_8M_FREQ_MHZ (8)
#define CLK_LL_PLL_60M_FREQ_MHZ (60)
#define CLK_LL_PLL_80M_FREQ_MHZ (80)
#define CLK_LL_PLL_120M_FREQ_MHZ (120)
#define CLK_LL_PLL_160M_FREQ_MHZ (160)
#define CLK_LL_PLL_240M_FREQ_MHZ (240)
#define CLK_LL_PLL_320M_FREQ_MHZ (320)
@@ -105,6 +107,47 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void)
CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN);
}
/**
* @brief Power up XTALX2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtalx2_enable(void)
{
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_0_REG, PMU_TIE_HIGH_XPD_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_0_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN);
}
/**
* @brief Power down XTALX2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtalx2_disable(void)
{
CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_0_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_0_REG, PMU_TIE_LOW_XPD_XTALX2);
}
/**
* @brief Get ref_80m clock source mux selection
*
* @return false: BBPLL divided path, true: XTALx2 80MHz (`clk_xtalx2_80m`)
*/
static inline __attribute__((always_inline)) bool clk_ll_ref_80m_get_src(void)
{
return (bool)HP_SYS_CLKRST.ref_80m_ctrl0.reg_ref_80m_sel;
}
/**
* @brief Select REF_80M_CLK source
*
* @param in_sel 0 selects BBPLL divided 80MHz, 1 selects XTALx2 80MHz.
*/
static inline __attribute__((always_inline)) void clk_ll_ref_80m_set_src(uint8_t in_sel)
{
HAL_ASSERT(in_sel == 0 || in_sel == 1);
HP_SYS_CLKRST.ref_80m_ctrl0.reg_ref_80m_sel = in_sel;
}
/**
* @brief Power up BBPLL circuit
*/
@@ -710,6 +753,16 @@ static inline __attribute__((always_inline)) void clk_ll_ref_500m_set_src(uint8_
HP_SYS_CLKRST.ref_500m_ctrl0.reg_ref_500m_sel = in_sel;
}
/**
* @brief Get ref_500m clock source mux selection
*
* @return false: CPLL (320MHz), true: MPLL (500MHz)
*/
static inline __attribute__((always_inline)) bool clk_ll_ref_500m_get_src(void)
{
return (bool)HP_SYS_CLKRST.ref_500m_ctrl0.reg_ref_500m_sel;
}
/**
* @brief Set PLL_F50M_CLK divider. freq of PLL_F50M_CLK = freq of MPLL_CLK / divider
*
@@ -753,6 +806,26 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f20m_get_divide
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_20m_ctrl0, reg_ref_20m_clk_div_num) + 1;
}
/**
* @brief Get PLL_F50M_CLK divider
*
* @return Divider. Divider = (CLK_DIV_NUM + 1).
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f50m_get_divider(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_50m_ctrl0, reg_ref_50m_clk_div_num) + 1;
}
/**
* @brief Get PLL_F25M_CLK divider
*
* @return Divider. Divider = (CLK_DIV_NUM + 1).
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f25m_get_divider(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_25m_ctrl0, reg_ref_25m_clk_div_num) + 1;
}
/**
* @brief Select the frequency calculation clock source for timergroup0
*