Merge branch 'esp32p4/add_adc_support_v5.3' into 'release/v5.3'

feat(adc): support ADC oneshot/continuous mode on ESP32P4(v5.3)

See merge request espressif/esp-idf!31367

components/esp_hw_support/adc_share_hw_ctrl.c

@@ -12,7 +12,7 @@
  *
  * However, usages of above components are different.
  * Therefore, we put the common used parts into `esp_hw_support`, including:
- * - adc power maintainance
+ * - adc power maintenance
  * - adc hw calibration settings
  * - adc locks, to prevent concurrently using adc hw
  */
@@ -205,10 +205,10 @@ void adc_apb_periph_claim(void)
     portENTER_CRITICAL(&s_spinlock);
     s_adc_digi_ctrlr_cnt++;
     if (s_adc_digi_ctrlr_cnt == 1) {
-        //enable ADC digital part
-        periph_module_enable(PERIPH_SARADC_MODULE);
-        //reset ADC digital part
-        periph_module_reset(PERIPH_SARADC_MODULE);
+        ADC_BUS_CLK_ATOMIC() {
+            adc_ll_enable_bus_clock(true);
+            adc_ll_reset_register();
+        }
     }
 
     portEXIT_CRITICAL(&s_spinlock);
@@ -219,7 +219,9 @@ void adc_apb_periph_free(void)
     portENTER_CRITICAL(&s_spinlock);
     s_adc_digi_ctrlr_cnt--;
     if (s_adc_digi_ctrlr_cnt == 0) {
-        periph_module_disable(PERIPH_SARADC_MODULE);
+        ADC_BUS_CLK_ATOMIC() {
+            adc_ll_enable_bus_clock(false);
+        }
     } else if (s_adc_digi_ctrlr_cnt < 0) {
         portEXIT_CRITICAL(&s_spinlock);
         ESP_LOGE(TAG, "%s called, but `s_adc_digi_ctrlr_cnt == 0`", __func__);

components/esp_hw_support/include/esp_private/adc_share_hw_ctrl.h

@@ -12,7 +12,7 @@
  *
  * However, usages of above components are different.
  * Therefore, we put the common used parts into `esp_hw_support`, including:
- * - adc power maintainance
+ * - adc power maintenance
  * - adc hw calibration settings
  * - adc locks, to prevent concurrently using adc hw
  */
@@ -26,6 +26,12 @@
 extern "C" {
 #endif
 
+#if SOC_RCC_IS_INDEPENDENT || CONFIG_IDF_TARGET_ESP32
+#define ADC_BUS_CLK_ATOMIC()
+#else
+#define ADC_BUS_CLK_ATOMIC()       PERIPH_RCC_ATOMIC()
+#endif
+
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
 /*---------------------------------------------------------------
             ADC Hardware Calibration

components/esp_hw_support/port/esp32p4/CMakeLists.txt

@@ -10,7 +10,8 @@ set(srcs "rtc_clk_init.c"
          )
 
 if(NOT BOOTLOADER_BUILD)
-    list(APPEND srcs "esp_crypto_lock.c")
+    list(APPEND srcs "sar_periph_ctrl.c"
+                     "esp_crypto_lock.c")
 
     if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
         list(APPEND srcs "mspi_timing_config.c")

components/esp_hw_support/port/esp32p4/sar_periph_ctrl.c

@@ -0,0 +1,116 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ */
+
+#include "sdkconfig.h"
+#include "esp_log.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+#include "esp_private/esp_modem_clock.h"
+#include "hal/sar_ctrl_ll.h"
+
+static const char *TAG = "sar_periph_ctrl";
+extern portMUX_TYPE rtc_spinlock;
+
+
+void sar_periph_ctrl_init(void)
+{
+    //Put SAR control mux to FSM state
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+}
+
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+/**
+ * This gets incremented when s_sar_power_acquire() is called,
+ * and decremented when s_sar_power_release() is called.
+ * PWDET is powered down when the value reaches zero.
+ * Should be modified within critical section.
+ */
+static int s_sar_power_on_cnt;
+
+static void s_sar_power_acquire(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_sar_power_on_cnt++;
+    if (s_sar_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+static void s_sar_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_sar_power_on_cnt--;
+    if (s_sar_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_sar_power_on_cnt == 0) {
+        sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    s_sar_power_release();
+}
+
+
+/*------------------------------------------------------------------------------
+* ADC Power
+*----------------------------------------------------------------------------*/
+void sar_periph_ctrl_adc_oneshot_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_adc_oneshot_power_release(void)
+{
+    s_sar_power_release();
+}
+
+void sar_periph_ctrl_adc_continuous_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_adc_continuous_power_release(void)
+{
+    s_sar_power_release();
+}

components/esp_hw_support/sleep_modes.c

@@ -663,7 +663,7 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep)
 #endif
     }
 
-#if !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-6496
+#if !CONFIG_IDF_TARGET_ESP32P4
     // TODO: IDF-7370
     if (!(deep_sleep && s_adc_tsen_enabled)){
         sar_periph_ctrl_power_disable();
@@ -679,11 +679,7 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(void)
 #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
     sleep_console_usj_pad_restore();
 #endif
-
-#if !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-6496
     sar_periph_ctrl_power_enable();
-#endif
-
 #if CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && SOC_PM_CPU_RETENTION_BY_RTCCNTL
     sleep_disable_cpu_retention();
 #endif