mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 11:10:54 +03:00
rename APB_CTRL ro SYS_CON
save
This commit is contained in:
Wu Zheng Hui
committed by
Jiang Jiang Jian
Jiang Jiang Jian
parent
b59902f4d1
commit
1080e4f6a2
@@ -1,486 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_APB_CTRL_REG_H_
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#define _SOC_APB_CTRL_REG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc.h"
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#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C)
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/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
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#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_S 0
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#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x010)
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/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
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#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_2_S 0
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#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C)
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/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
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/*description: */
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#define APB_CTRL_PERI_IO_SWAP 0x000000FF
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#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
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#define APB_CTRL_PERI_IO_SWAP_V 0xFF
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#define APB_CTRL_PERI_IO_SWAP_S 0
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#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x020)
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/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
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#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
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#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
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#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
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#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x028)
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/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE0_ATTR 0x00000003
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#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
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#define APB_CTRL_FLASH_ACE0_ATTR_V 0x3
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#define APB_CTRL_FLASH_ACE0_ATTR_S 0
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#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x02C)
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/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE1_ATTR 0x00000003
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#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
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#define APB_CTRL_FLASH_ACE1_ATTR_V 0x3
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#define APB_CTRL_FLASH_ACE1_ATTR_S 0
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#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x030)
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/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE2_ATTR 0x00000003
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#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
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#define APB_CTRL_FLASH_ACE2_ATTR_V 0x3
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#define APB_CTRL_FLASH_ACE2_ATTR_S 0
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#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x034)
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/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE3_ATTR 0x00000003
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#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
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#define APB_CTRL_FLASH_ACE3_ATTR_V 0x3
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#define APB_CTRL_FLASH_ACE3_ATTR_S 0
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#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x038)
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/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x03C)
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/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x040)
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/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x044)
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/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x048)
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/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE0_SIZE 0x00001FFF
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#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
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#define APB_CTRL_FLASH_ACE0_SIZE_V 0x1FFF
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#define APB_CTRL_FLASH_ACE0_SIZE_S 0
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#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x04C)
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/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE1_SIZE 0x00001FFF
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#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
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#define APB_CTRL_FLASH_ACE1_SIZE_V 0x1FFF
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#define APB_CTRL_FLASH_ACE1_SIZE_S 0
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#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x050)
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/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE2_SIZE 0x00001FFF
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#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
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#define APB_CTRL_FLASH_ACE2_SIZE_V 0x1FFF
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#define APB_CTRL_FLASH_ACE2_SIZE_S 0
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#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x054)
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/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE3_SIZE 0x00001FFF
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#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
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#define APB_CTRL_FLASH_ACE3_SIZE_V 0x1FFF
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#define APB_CTRL_FLASH_ACE3_SIZE_S 0
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#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x088)
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/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
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/*description: */
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#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
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#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
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#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
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#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
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/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
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#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
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#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
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#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
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/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
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#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
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#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
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#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
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#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x08C)
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/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
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#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
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#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
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#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
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#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x090)
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/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
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/*description: */
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#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
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#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
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#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
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#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
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#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x094)
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/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
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/*description: */
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#define APB_CTRL_REDCY_ANDOR (BIT(31))
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#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
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#define APB_CTRL_REDCY_ANDOR_V 0x1
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#define APB_CTRL_REDCY_ANDOR_S 31
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/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
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/*description: */
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#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
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#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
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#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
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#define APB_CTRL_REDCY_SIG0_S 0
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#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x098)
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/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
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/*description: */
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#define APB_CTRL_REDCY_NANDOR (BIT(31))
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#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
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#define APB_CTRL_REDCY_NANDOR_V 0x1
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#define APB_CTRL_REDCY_NANDOR_S 31
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/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
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/*description: */
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#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
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#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
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#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
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#define APB_CTRL_REDCY_SIG1_S 0
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#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C)
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/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
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#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
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#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
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#define APB_CTRL_DC_MEM_FORCE_PD_S 5
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/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
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#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
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#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
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#define APB_CTRL_DC_MEM_FORCE_PU_S 4
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/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
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#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
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#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
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#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
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/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
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#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
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#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
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#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
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/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
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#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
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#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
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#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
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/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
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#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
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#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
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#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
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#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0)
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/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27))
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#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
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#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
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#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
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#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0x0A4)
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/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
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/*description: */
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#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x0000000F
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#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
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#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0xF
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#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 2
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/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
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/*description: */
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#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000003
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#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
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#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x3
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#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0
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#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0x0A8)
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/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
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||||
/*description: */
|
||||
#define APB_CTRL_SRAM_POWER_DOWN 0x0000000F
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_V 0xF
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_S 2
|
||||
/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_ROM_POWER_DOWN 0x00000003
|
||||
#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
|
||||
#define APB_CTRL_ROM_POWER_DOWN_V 0x3
|
||||
#define APB_CTRL_ROM_POWER_DOWN_S 0
|
||||
|
||||
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0x0AC)
|
||||
/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_POWER_UP 0x0000000F
|
||||
#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
|
||||
#define APB_CTRL_SRAM_POWER_UP_V 0xF
|
||||
#define APB_CTRL_SRAM_POWER_UP_S 2
|
||||
/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_ROM_POWER_UP 0x00000003
|
||||
#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
|
||||
#define APB_CTRL_ROM_POWER_UP_V 0x3
|
||||
#define APB_CTRL_ROM_POWER_UP_S 0
|
||||
|
||||
#define APB_CTRL_RND_DATA_REG (DR_REG_APB_CTRL_BASE + 0x0B0)
|
||||
/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_RND_DATA 0xFFFFFFFF
|
||||
#define APB_CTRL_RND_DATA_M ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
|
||||
#define APB_CTRL_RND_DATA_V 0xFFFFFFFF
|
||||
#define APB_CTRL_RND_DATA_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_CONFIG_REG (DR_REG_APB_CTRL_BASE + 0x0B4)
|
||||
/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ENA (BIT(31))
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_M (BIT(31))
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_S 31
|
||||
/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM (BIT(30))
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_M (BIT(30))
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_S 30
|
||||
/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_START (BIT(29))
|
||||
#define APB_CTRL_PERI_BACKUP_START_M (BIT(29))
|
||||
#define APB_CTRL_PERI_BACKUP_START_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_START_S 29
|
||||
/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE 0x000003FF
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_M ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_V 0x3FF
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_S 19
|
||||
/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES 0x000003FF
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V 0x3FF
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S 9
|
||||
/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT 0x0000001F
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4
|
||||
/* APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE (BIT(3))
|
||||
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3))
|
||||
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_S 3
|
||||
/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000007
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x7
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B8)
|
||||
/* APB_CTRL_PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_M ((APB_CTRL_PERI_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_PERI_BACKUP_APB_START_ADDR_S))
|
||||
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC)
|
||||
/* APB_CTRL_PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_M ((APB_CTRL_PERI_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_PERI_BACKUP_MEM_START_ADDR_S))
|
||||
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_MAP0_REG (DR_REG_APB_CTRL_BASE + 0x0C0)
|
||||
/* APB_CTRL_PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_MAP0 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MAP0_M ((APB_CTRL_PERI_BACKUP_MAP0_V)<<(APB_CTRL_PERI_BACKUP_MAP0_S))
|
||||
#define APB_CTRL_PERI_BACKUP_MAP0_V 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MAP0_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_MAP1_REG (DR_REG_APB_CTRL_BASE + 0x0C4)
|
||||
/* APB_CTRL_PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_MAP1 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MAP1_M ((APB_CTRL_PERI_BACKUP_MAP1_V)<<(APB_CTRL_PERI_BACKUP_MAP1_S))
|
||||
#define APB_CTRL_PERI_BACKUP_MAP1_V 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MAP1_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_MAP2_REG (DR_REG_APB_CTRL_BASE + 0x0C8)
|
||||
/* APB_CTRL_PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_MAP2 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MAP2_M ((APB_CTRL_PERI_BACKUP_MAP2_V)<<(APB_CTRL_PERI_BACKUP_MAP2_S))
|
||||
#define APB_CTRL_PERI_BACKUP_MAP2_V 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MAP2_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_MAP3_REG (DR_REG_APB_CTRL_BASE + 0x0CC)
|
||||
/* APB_CTRL_PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_MAP3 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MAP3_M ((APB_CTRL_PERI_BACKUP_MAP3_V)<<(APB_CTRL_PERI_BACKUP_MAP3_S))
|
||||
#define APB_CTRL_PERI_BACKUP_MAP3_V 0xFFFFFFFF
|
||||
#define APB_CTRL_PERI_BACKUP_MAP3_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_APB_CTRL_BASE + 0x0D0)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_APB_CTRL_BASE + 0x0D4)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_APB_CTRL_BASE + 0x0D8)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_APB_CTRL_BASE + 0x0DC)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0
|
||||
|
||||
#define APB_CTRL_CLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0E0)
|
||||
/* APB_CTRL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK_EN (BIT(0))
|
||||
#define APB_CTRL_CLK_EN_M (BIT(0))
|
||||
#define APB_CTRL_CLK_EN_V 0x1
|
||||
#define APB_CTRL_CLK_EN_S 0
|
||||
|
||||
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
|
||||
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101050 ; */
|
||||
/*description: Version control*/
|
||||
#define APB_CTRL_DATE 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
|
||||
#define APB_CTRL_DATE_V 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_CTRL_REG_H_ */
|
||||
@@ -1,454 +0,0 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_APB_CTRL_STRUCT_H_
|
||||
#define _SOC_APB_CTRL_STRUCT_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct apb_ctrl_dev_s {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
uint32_t wifi_bb_cfg; /**/
|
||||
uint32_t wifi_bb_cfg_2; /**/
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_io_swap: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} host_inf_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_mem_pms_lock: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_pms_lock;
|
||||
uint32_t reserved_24;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_attr;
|
||||
uint32_t flash_ace0_addr; /**/
|
||||
uint32_t flash_ace1_addr; /**/
|
||||
uint32_t flash_ace2_addr; /**/
|
||||
uint32_t flash_ace3_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_size;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_mem_reject_int: 1;
|
||||
uint32_t spi_mem_reject_clr: 1;
|
||||
uint32_t spi_mem_reject_cde: 5;
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_pms_ctrl;
|
||||
uint32_t spi_mem_reject_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_win_access_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0: 31;
|
||||
uint32_t redcy_andor: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig1: 31;
|
||||
uint32_t redcy_nandor: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t agc_mem_force_pu: 1;
|
||||
uint32_t agc_mem_force_pd: 1;
|
||||
uint32_t pbus_mem_force_pu: 1;
|
||||
uint32_t pbus_mem_force_pd: 1;
|
||||
uint32_t dc_mem_force_pu: 1;
|
||||
uint32_t dc_mem_force_pd: 1;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} front_end_mem_pd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t nobypass_cpu_iso_rst: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_clkgate_force_on: 2;
|
||||
uint32_t sram_clkgate_force_on: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} clkgate_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_down: 2;
|
||||
uint32_t sram_power_down: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_down;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_up: 2;
|
||||
uint32_t sram_power_up: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_up;
|
||||
uint32_t rnd_data; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_flow_err: 3;
|
||||
uint32_t peri_backup_addr_map_mode: 1;
|
||||
uint32_t peri_backup_burst_limit: 5;
|
||||
uint32_t peri_backup_tout_thres: 10;
|
||||
uint32_t peri_backup_size: 10;
|
||||
uint32_t peri_backup_start: 1;
|
||||
uint32_t peri_backup_to_mem: 1;
|
||||
uint32_t peri_backup_ena: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_config;
|
||||
uint32_t peri_backup_addr; /**/
|
||||
uint32_t peri_backup_mem_addr; /**/
|
||||
uint32_t peri_backup_map0; /**/
|
||||
uint32_t peri_backup_map1; /**/
|
||||
uint32_t peri_backup_map2; /**/
|
||||
uint32_t peri_backup_map3; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrlclk_conf;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t date; /*Version control*/
|
||||
} apb_ctrl_dev_t;
|
||||
extern apb_ctrl_dev_t APB_CTRL;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_APB_CTRL_STRUCT_H_ */
|
||||
@@ -79,7 +79,6 @@
|
||||
#define DR_REG_SPI2_BASE 0x60024000
|
||||
#define DR_REG_SPI3_BASE 0x60025000
|
||||
#define DR_REG_SYSCON_BASE 0x60026000
|
||||
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
|
||||
#define DR_REG_I2C1_EXT_BASE 0x60027000
|
||||
#define DR_REG_SDMMC_BASE 0x60028000
|
||||
#define DR_REG_CAN_BASE 0x6002B000
|
||||
|
||||
@@ -128,7 +128,7 @@ typedef volatile struct syscon_dev_s {
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_ctrl_sdio_ctrl;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0: 31;
|
||||
@@ -245,7 +245,7 @@ typedef volatile struct syscon_dev_s {
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_ctrlclk_conf;
|
||||
} clk_conf;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
@@ -444,7 +444,7 @@ typedef volatile struct syscon_dev_s {
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t apb_ctrl_date; /*Version control*/
|
||||
uint32_t date; /*Version control*/
|
||||
} syscon_dev_t;
|
||||
extern syscon_dev_t SYSCON;
|
||||
#ifdef __cplusplus
|
||||
|
||||
Reference in New Issue
Block a user