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feat(ulp): add support for ulp on esp32s31

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This commit is contained in:
Marius Vikhammer
2026-04-20 14:45:23 +08:00
parent dfc5bbb58c
commit 10637dbf5e
51 changed files with 536 additions and 101 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
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@@ -1610,3 +1610,7 @@ config SOC_LP_CORE_SUPPORT_ETM
config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
bool
default y
config SOC_LP_CORE_SUPPORT_I2C
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1
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@@ -644,3 +644,4 @@
#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
#define SOC_LP_CORE_SUPPORT_I2C (1) /*!< LP Core supports I2C */
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+4
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@@ -1359,6 +1359,10 @@ config SOC_LP_CORE_SUPPORT_ETM
bool
default y
config SOC_LP_CORE_SUPPORT_I2C
bool
default y
config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+1
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@@ -552,6 +552,7 @@
/*------------------------------------- ULP CAPS -------------------------------------*/
#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_I2C (1) /*!< LP Core supports I2C */
/*------------------------------------- DEBUG CAPS -------------------------------------*/
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+4
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@@ -1918,3 +1918,7 @@ config SOC_LP_CORE_SUPPORT_LP_ADC
config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
bool
default y
config SOC_LP_CORE_SUPPORT_I2C
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+1
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@@ -735,3 +735,4 @@
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */
#define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
#define SOC_LP_CORE_SUPPORT_I2C (1) /*!< LP Core supports I2C */
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+16
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@@ -59,6 +59,14 @@ config SOC_USB_OTG_SUPPORTED
bool
default y
config SOC_ULP_SUPPORTED
bool
default y
config SOC_LP_CORE_SUPPORTED
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@@ -999,6 +1007,14 @@ config SOC_PM_RETENTION_MODULE_NUM
int
default 64
config SOC_LP_CORE_SUPPORT_ETM
bool
default y
config SOC_LP_CORE_CONFIGURABLE_BOOT_ADDR
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
components/soc/esp32s31/include/soc/interrupts.h
+3
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@@ -190,6 +190,9 @@ typedef enum {
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
// ESP32-S31 names the PMU interrupt source ETS_PMT_INTR_SOURCE; alias for cross-chip compatibility
#define ETS_PMU_INTR_SOURCE ETS_PMT_INTR_SOURCE
#ifdef __cplusplus
}
#endif
components/soc/esp32s31/include/soc/soc_caps.h
+8 -2
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@@ -49,8 +49,8 @@
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32S31] IDF-14788
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32S31] IDF-14799
// #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: [ESP32S31] IDF-14629
// #define SOC_ULP_SUPPORTED 1 // TODO: [ESP32S31] IDF-14640
// #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32S31] IDF-14640
#define SOC_ULP_SUPPORTED 1
#define SOC_LP_CORE_SUPPORTED 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32S31] IDF-14688
#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32S31] IDF-14688
#define SOC_RTC_FAST_MEM_SUPPORTED 1
@@ -438,6 +438,12 @@
#define SOC_PM_RETENTION_MODULE_NUM (64)
/*-------------------------- LP_CORE CAPS ------------------------------------*/
// #define SOC_LP_MAILBOX_SUPPORTED (1) // TODO: [ESP32S31] IDF-14637
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM wakeup */
#define SOC_LP_CORE_CONFIGURABLE_BOOT_ADDR (1) /*!< LP Core has no LP ROM; HP must write the reset_vector address (LP_RAM_BASE+0x80) to LP_SYS.lp_core_boot_addr before triggering LP wake */
//#define SOC_LP_CORE_SUPPORT_I2C (1) /*!< LP Core supports I2C */ TODO IDF-14635
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
components/soc/esp32s31/register/soc/lp_mailbox_struct.h
-1
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@@ -856,7 +856,6 @@ typedef struct {
volatile mb_reg_clk_en_reg_t reg_clk_en;
} mb_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(mb_dev_t) == 0x64, "Invalid size of mb_dev_t structure");
#endif
components/soc/esp32s31/register/soc/lp_pwr_struct.h
+2
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@@ -1019,6 +1019,8 @@ typedef struct {
} lp_pwr_dev_t;
extern lp_pwr_dev_t LP_PWR;
#ifndef __cplusplus
_Static_assert(sizeof(lp_pwr_dev_t) == 0xa8, "Invalid size of lp_pwr_dev_t structure");
#endif
components/soc/esp32s31/register/soc/reg_base.h
+1
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@@ -137,6 +137,7 @@
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTR0_BASE
#define DR_REG_INTERRUPT_CORE1_BASE (DR_REG_INTR0_BASE + 0x800)
#define DR_REG_LPPERI_BASE DR_REG_LP_PERICLKRST_BASE
#define DR_REG_LP_PWR_BASE DR_REG_LP_PWR_REG_BASE /* alias used by lp_pwr_reg.h */
#define DR_REG_SDHOST_BASE DR_REG_SDMMC_BASE
#define DR_REG_TRACE_BASE DR_REG_TRACE0_BASE
#define DR_REG_MB_BASE DR_REG_LP_MAILBOX_BASE