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feat(gpio): support LP_IO clock gating management

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wuzhenghui
2024-03-13 11:56:14 +08:00
parent 92849e660e
commit 0fc97f0e84
10 changed files with 128 additions and 10 deletions
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components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+4
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@@ -519,6 +519,10 @@ config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_RTCIO_VALID_RTCIO_MASK
hex
default 0x7F80
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
components/soc/esp32h2/include/soc/soc_caps.h
+1
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@@ -220,6 +220,7 @@
* for hold, wake & 32kHz crystal functions - via LP_AON registers */
#define SOC_RTCIO_PIN_COUNT (8U)
#define SOC_RTCIO_HOLD_SUPPORTED (1)
#define SOC_RTCIO_VALID_RTCIO_MASK (0x7F80)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
components/soc/esp32h2/ld/esp32h2.peripherals.ld
+1 -1
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@@ -66,7 +66,7 @@ PROVIDE ( LP_TIMER = 0x600B0C00 );
PROVIDE ( LP_AON = 0x600B1000 );
PROVIDE ( LP_WDT = 0x600B1C00 );
PROVIDE ( I2C_ANA_MST = 0x600B2400 );
PROVIDE ( LP_PERI = 0x600B2800 );
PROVIDE ( LPPERI = 0x600B2800 );
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
PROVIDE ( LP_APM = 0x600B3800 );
PROVIDE ( OTP_DEBUG = 0x600B3C00 );