feat(esp_security): support s31 security clock management

components/esp_system/CMakeLists.txt

@@ -89,7 +89,7 @@ else()
 
     idf_component_register(SRCS "${srcs}"
                         INCLUDE_DIRS include
-                        PRIV_REQUIRES spi_flash esp_timer esp_mm
+                        PRIV_REQUIRES spi_flash esp_timer esp_mm esp_hal_security
                                       esp_hal_mspi esp_hal_wdt esp_hal_uart esp_hal_clock esp_hal_dma
                                     # [refactor-todo] requirements due to init code,
                                     # should be removable once using component init functions

components/esp_system/port/soc/esp32s31/system_internal.c

@@ -26,6 +26,7 @@
 #endif
 #include "esp_private/cache_err_int.h"
 #include "hal/uart_ll.h"
+#include "hal/sec_ll.h"
 #include "esp_memory_utils.h"
 
 #define ALIGN_DOWN(val, align)  ((val) & ~((align) - 1))
@@ -51,6 +52,9 @@ void esp_system_reset_modules_on_exit(void)
 
     CLEAR_PERI_REG_MASK(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_EN);
     SET_PERI_REG_MASK(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL);
+    // Reset the clock source selection to an always-on source (XTAL), otherwise if the clock source
+    // is disabled, will get stuck in ROM encryption related ops.
+    sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_XTAL);
 }
 
 static void IRAM_ATTR __attribute__((noinline, noreturn)) esp_restart_noos_inner(void)