From 384eba8a1178c1e577f70f88872c77c77fccce44 Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Mon, 15 Dec 2025 14:59:41 +0530 Subject: [PATCH 1/3] refactor(soc): Update the ESP32-P4v3+ PMS header files --- .../register/hw_ver3/soc/dma_pms_eco5_reg.h | 1575 ------------ .../register/hw_ver3/soc/dma_pms_reg.h | 24 + .../register/hw_ver3/soc/dma_pms_struct.h | 1816 ++++---------- .../hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h | 778 ------ .../register/hw_ver3/soc/hp2lp_peri_pms_reg.h | 37 +- .../hw_ver3/soc/hp2lp_peri_pms_struct.h | 724 +++--- .../hw_ver3/soc/hp_peri_pms_eco5_reg.h | 2231 ----------------- .../register/hw_ver3/soc/hp_peri_pms_reg.h | 92 +- .../register/hw_ver3/soc/hp_peri_pms_struct.h | 2095 +++++++--------- .../register/hw_ver3/soc/icm_sys_reg.h | 38 +- .../hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h | 584 ----- .../register/hw_ver3/soc/lp2hp_peri_pms_reg.h | 20 +- .../hw_ver3/soc/lp2hp_peri_pms_struct.h | 699 ++++-- .../hw_ver3/soc/lp_peri_pms_eco5_reg.h | 491 ---- .../register/hw_ver3/soc/lp_peri_pms_reg.h | 210 +- .../register/hw_ver3/soc/lp_peri_pms_struct.h | 655 ++--- 16 files changed, 2761 insertions(+), 9308 deletions(-) delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/dma_pms_eco5_reg.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_eco5_reg.h diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_eco5_reg.h deleted file mode 100644 index 796fcf971c7..00000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_eco5_reg.h +++ /dev/null @@ -1,1575 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 OR MIT - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** TEE_DMA_DATE_REG register - * NA - */ -#define TEE_DMA_DATE_REG (DR_REG_TEE_DMA_BASE + 0x0) -/** TEE_DMA_TEE_DATE : R/W; bitpos: [31:0]; default: 539165460; - * NA - */ -#define TEE_DMA_TEE_DATE 0xFFFFFFFFU -#define TEE_DMA_TEE_DATE_M (TEE_DMA_TEE_DATE_V << TEE_DMA_TEE_DATE_S) -#define TEE_DMA_TEE_DATE_V 0xFFFFFFFFU -#define TEE_DMA_TEE_DATE_S 0 - -/** TEE_DMA_CLK_EN_REG register - * NA - */ -#define TEE_DMA_CLK_EN_REG (DR_REG_TEE_DMA_BASE + 0x4) -/** TEE_DMA_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_DMA_CLK_EN (BIT(0)) -#define TEE_DMA_CLK_EN_M (TEE_DMA_CLK_EN_V << TEE_DMA_CLK_EN_S) -#define TEE_DMA_CLK_EN_V 0x00000001U -#define TEE_DMA_CLK_EN_S 0 - -/** TEE_DMA_REGION0_LOW_REG register - * Region0 address low register. - */ -#define TEE_DMA_REGION0_LOW_REG (DR_REG_TEE_DMA_BASE + 0x8) -/** TEE_DMA_REGION0_LOW : R/W; bitpos: [31:12]; default: 0; - * Region0 address low. - */ -#define TEE_DMA_REGION0_LOW 0x000FFFFFU -#define TEE_DMA_REGION0_LOW_M (TEE_DMA_REGION0_LOW_V << TEE_DMA_REGION0_LOW_S) -#define TEE_DMA_REGION0_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION0_LOW_S 12 - -/** TEE_DMA_REGION0_HIGH_REG register - * Region0 address high register. - */ -#define TEE_DMA_REGION0_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xc) -/** TEE_DMA_REGION0_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region0 address high. - */ -#define TEE_DMA_REGION0_HIGH 0x000FFFFFU -#define TEE_DMA_REGION0_HIGH_M (TEE_DMA_REGION0_HIGH_V << TEE_DMA_REGION0_HIGH_S) -#define TEE_DMA_REGION0_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION0_HIGH_S 12 - -/** TEE_DMA_REGION1_LOW_REG register - * Region1 address low register. - */ -#define TEE_DMA_REGION1_LOW_REG (DR_REG_TEE_DMA_BASE + 0x10) -/** TEE_DMA_REGION1_LOW : R/W; bitpos: [31:12]; default: 0; - * Region1 address low. - */ -#define TEE_DMA_REGION1_LOW 0x000FFFFFU -#define TEE_DMA_REGION1_LOW_M (TEE_DMA_REGION1_LOW_V << TEE_DMA_REGION1_LOW_S) -#define TEE_DMA_REGION1_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION1_LOW_S 12 - -/** TEE_DMA_REGION1_HIGH_REG register - * Region1 address high register. - */ -#define TEE_DMA_REGION1_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x14) -/** TEE_DMA_REGION1_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region1 address high. - */ -#define TEE_DMA_REGION1_HIGH 0x000FFFFFU -#define TEE_DMA_REGION1_HIGH_M (TEE_DMA_REGION1_HIGH_V << TEE_DMA_REGION1_HIGH_S) -#define TEE_DMA_REGION1_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION1_HIGH_S 12 - -/** TEE_DMA_REGION2_LOW_REG register - * Region2 address low register. - */ -#define TEE_DMA_REGION2_LOW_REG (DR_REG_TEE_DMA_BASE + 0x18) -/** TEE_DMA_REGION2_LOW : R/W; bitpos: [31:12]; default: 0; - * Region2 address low. - */ -#define TEE_DMA_REGION2_LOW 0x000FFFFFU -#define TEE_DMA_REGION2_LOW_M (TEE_DMA_REGION2_LOW_V << TEE_DMA_REGION2_LOW_S) -#define TEE_DMA_REGION2_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION2_LOW_S 12 - -/** TEE_DMA_REGION2_HIGH_REG register - * Region2 address high register. - */ -#define TEE_DMA_REGION2_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x1c) -/** TEE_DMA_REGION2_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region2 address high. - */ -#define TEE_DMA_REGION2_HIGH 0x000FFFFFU -#define TEE_DMA_REGION2_HIGH_M (TEE_DMA_REGION2_HIGH_V << TEE_DMA_REGION2_HIGH_S) -#define TEE_DMA_REGION2_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION2_HIGH_S 12 - -/** TEE_DMA_REGION3_LOW_REG register - * Region3 address low register. - */ -#define TEE_DMA_REGION3_LOW_REG (DR_REG_TEE_DMA_BASE + 0x20) -/** TEE_DMA_REGION3_LOW : R/W; bitpos: [31:12]; default: 0; - * Region3 address low. - */ -#define TEE_DMA_REGION3_LOW 0x000FFFFFU -#define TEE_DMA_REGION3_LOW_M (TEE_DMA_REGION3_LOW_V << TEE_DMA_REGION3_LOW_S) -#define TEE_DMA_REGION3_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION3_LOW_S 12 - -/** TEE_DMA_REGION3_HIGH_REG register - * Region3 address high register. - */ -#define TEE_DMA_REGION3_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x24) -/** TEE_DMA_REGION3_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region3 address high. - */ -#define TEE_DMA_REGION3_HIGH 0x000FFFFFU -#define TEE_DMA_REGION3_HIGH_M (TEE_DMA_REGION3_HIGH_V << TEE_DMA_REGION3_HIGH_S) -#define TEE_DMA_REGION3_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION3_HIGH_S 12 - -/** TEE_DMA_REGION4_LOW_REG register - * Region4 address low register. - */ -#define TEE_DMA_REGION4_LOW_REG (DR_REG_TEE_DMA_BASE + 0x28) -/** TEE_DMA_REGION4_LOW : R/W; bitpos: [31:12]; default: 0; - * Region4 address low. - */ -#define TEE_DMA_REGION4_LOW 0x000FFFFFU -#define TEE_DMA_REGION4_LOW_M (TEE_DMA_REGION4_LOW_V << TEE_DMA_REGION4_LOW_S) -#define TEE_DMA_REGION4_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION4_LOW_S 12 - -/** TEE_DMA_REGION4_HIGH_REG register - * Region4 address high register. - */ -#define TEE_DMA_REGION4_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x2c) -/** TEE_DMA_REGION4_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region4 address high. - */ -#define TEE_DMA_REGION4_HIGH 0x000FFFFFU -#define TEE_DMA_REGION4_HIGH_M (TEE_DMA_REGION4_HIGH_V << TEE_DMA_REGION4_HIGH_S) -#define TEE_DMA_REGION4_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION4_HIGH_S 12 - -/** TEE_DMA_REGION5_LOW_REG register - * Region5 address low register. - */ -#define TEE_DMA_REGION5_LOW_REG (DR_REG_TEE_DMA_BASE + 0x30) -/** TEE_DMA_REGION5_LOW : R/W; bitpos: [31:12]; default: 0; - * Region5 address low. - */ -#define TEE_DMA_REGION5_LOW 0x000FFFFFU -#define TEE_DMA_REGION5_LOW_M (TEE_DMA_REGION5_LOW_V << TEE_DMA_REGION5_LOW_S) -#define TEE_DMA_REGION5_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION5_LOW_S 12 - -/** TEE_DMA_REGION5_HIGH_REG register - * Region5 address high register. - */ -#define TEE_DMA_REGION5_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x34) -/** TEE_DMA_REGION5_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region5 address high. - */ -#define TEE_DMA_REGION5_HIGH 0x000FFFFFU -#define TEE_DMA_REGION5_HIGH_M (TEE_DMA_REGION5_HIGH_V << TEE_DMA_REGION5_HIGH_S) -#define TEE_DMA_REGION5_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION5_HIGH_S 12 - -/** TEE_DMA_REGION6_LOW_REG register - * Region6 address low register. - */ -#define TEE_DMA_REGION6_LOW_REG (DR_REG_TEE_DMA_BASE + 0x38) -/** TEE_DMA_REGION6_LOW : R/W; bitpos: [31:12]; default: 0; - * Region6 address low. - */ -#define TEE_DMA_REGION6_LOW 0x000FFFFFU -#define TEE_DMA_REGION6_LOW_M (TEE_DMA_REGION6_LOW_V << TEE_DMA_REGION6_LOW_S) -#define TEE_DMA_REGION6_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION6_LOW_S 12 - -/** TEE_DMA_REGION6_HIGH_REG register - * Region6 address high register. - */ -#define TEE_DMA_REGION6_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x3c) -/** TEE_DMA_REGION6_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region6 address high. - */ -#define TEE_DMA_REGION6_HIGH 0x000FFFFFU -#define TEE_DMA_REGION6_HIGH_M (TEE_DMA_REGION6_HIGH_V << TEE_DMA_REGION6_HIGH_S) -#define TEE_DMA_REGION6_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION6_HIGH_S 12 - -/** TEE_DMA_REGION7_LOW_REG register - * Region7 address low register. - */ -#define TEE_DMA_REGION7_LOW_REG (DR_REG_TEE_DMA_BASE + 0x40) -/** TEE_DMA_REGION7_LOW : R/W; bitpos: [31:12]; default: 0; - * Region7 address low. - */ -#define TEE_DMA_REGION7_LOW 0x000FFFFFU -#define TEE_DMA_REGION7_LOW_M (TEE_DMA_REGION7_LOW_V << TEE_DMA_REGION7_LOW_S) -#define TEE_DMA_REGION7_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION7_LOW_S 12 - -/** TEE_DMA_REGION7_HIGH_REG register - * Region7 address high register. - */ -#define TEE_DMA_REGION7_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x44) -/** TEE_DMA_REGION7_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region7 address high. - */ -#define TEE_DMA_REGION7_HIGH 0x000FFFFFU -#define TEE_DMA_REGION7_HIGH_M (TEE_DMA_REGION7_HIGH_V << TEE_DMA_REGION7_HIGH_S) -#define TEE_DMA_REGION7_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION7_HIGH_S 12 - -/** TEE_DMA_REGION8_LOW_REG register - * Region8 address low register. - */ -#define TEE_DMA_REGION8_LOW_REG (DR_REG_TEE_DMA_BASE + 0x48) -/** TEE_DMA_REGION8_LOW : R/W; bitpos: [31:12]; default: 0; - * Region8 address low. - */ -#define TEE_DMA_REGION8_LOW 0x000FFFFFU -#define TEE_DMA_REGION8_LOW_M (TEE_DMA_REGION8_LOW_V << TEE_DMA_REGION8_LOW_S) -#define TEE_DMA_REGION8_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION8_LOW_S 12 - -/** TEE_DMA_REGION8_HIGH_REG register - * Region8 address high register. - */ -#define TEE_DMA_REGION8_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x4c) -/** TEE_DMA_REGION8_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region8 address high. - */ -#define TEE_DMA_REGION8_HIGH 0x000FFFFFU -#define TEE_DMA_REGION8_HIGH_M (TEE_DMA_REGION8_HIGH_V << TEE_DMA_REGION8_HIGH_S) -#define TEE_DMA_REGION8_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION8_HIGH_S 12 - -/** TEE_DMA_REGION9_LOW_REG register - * Region9 address low register. - */ -#define TEE_DMA_REGION9_LOW_REG (DR_REG_TEE_DMA_BASE + 0x50) -/** TEE_DMA_REGION9_LOW : R/W; bitpos: [31:12]; default: 0; - * Region9 address low. - */ -#define TEE_DMA_REGION9_LOW 0x000FFFFFU -#define TEE_DMA_REGION9_LOW_M (TEE_DMA_REGION9_LOW_V << TEE_DMA_REGION9_LOW_S) -#define TEE_DMA_REGION9_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION9_LOW_S 12 - -/** TEE_DMA_REGION9_HIGH_REG register - * Region9 address high register. - */ -#define TEE_DMA_REGION9_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x54) -/** TEE_DMA_REGION9_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region9 address high. - */ -#define TEE_DMA_REGION9_HIGH 0x000FFFFFU -#define TEE_DMA_REGION9_HIGH_M (TEE_DMA_REGION9_HIGH_V << TEE_DMA_REGION9_HIGH_S) -#define TEE_DMA_REGION9_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION9_HIGH_S 12 - -/** TEE_DMA_REGION10_LOW_REG register - * Region10 address low register. - */ -#define TEE_DMA_REGION10_LOW_REG (DR_REG_TEE_DMA_BASE + 0x58) -/** TEE_DMA_REGION10_LOW : R/W; bitpos: [31:12]; default: 0; - * Region10 address low. - */ -#define TEE_DMA_REGION10_LOW 0x000FFFFFU -#define TEE_DMA_REGION10_LOW_M (TEE_DMA_REGION10_LOW_V << TEE_DMA_REGION10_LOW_S) -#define TEE_DMA_REGION10_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION10_LOW_S 12 - -/** TEE_DMA_REGION10_HIGH_REG register - * Region10 address high register. - */ -#define TEE_DMA_REGION10_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x5c) -/** TEE_DMA_REGION10_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region10 address high. - */ -#define TEE_DMA_REGION10_HIGH 0x000FFFFFU -#define TEE_DMA_REGION10_HIGH_M (TEE_DMA_REGION10_HIGH_V << TEE_DMA_REGION10_HIGH_S) -#define TEE_DMA_REGION10_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION10_HIGH_S 12 - -/** TEE_DMA_REGION11_LOW_REG register - * Region11 address low register. - */ -#define TEE_DMA_REGION11_LOW_REG (DR_REG_TEE_DMA_BASE + 0x60) -/** TEE_DMA_REGION11_LOW : R/W; bitpos: [31:12]; default: 0; - * Region11 address low. - */ -#define TEE_DMA_REGION11_LOW 0x000FFFFFU -#define TEE_DMA_REGION11_LOW_M (TEE_DMA_REGION11_LOW_V << TEE_DMA_REGION11_LOW_S) -#define TEE_DMA_REGION11_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION11_LOW_S 12 - -/** TEE_DMA_REGION11_HIGH_REG register - * Region11 address high register. - */ -#define TEE_DMA_REGION11_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x64) -/** TEE_DMA_REGION11_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region11 address high. - */ -#define TEE_DMA_REGION11_HIGH 0x000FFFFFU -#define TEE_DMA_REGION11_HIGH_M (TEE_DMA_REGION11_HIGH_V << TEE_DMA_REGION11_HIGH_S) -#define TEE_DMA_REGION11_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION11_HIGH_S 12 - -/** TEE_DMA_REGION12_LOW_REG register - * Region12 address low register. - */ -#define TEE_DMA_REGION12_LOW_REG (DR_REG_TEE_DMA_BASE + 0x68) -/** TEE_DMA_REGION12_LOW : R/W; bitpos: [31:12]; default: 0; - * Region12 address low. - */ -#define TEE_DMA_REGION12_LOW 0x000FFFFFU -#define TEE_DMA_REGION12_LOW_M (TEE_DMA_REGION12_LOW_V << TEE_DMA_REGION12_LOW_S) -#define TEE_DMA_REGION12_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION12_LOW_S 12 - -/** TEE_DMA_REGION12_HIGH_REG register - * Region12 address high register. - */ -#define TEE_DMA_REGION12_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x6c) -/** TEE_DMA_REGION12_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region12 address high. - */ -#define TEE_DMA_REGION12_HIGH 0x000FFFFFU -#define TEE_DMA_REGION12_HIGH_M (TEE_DMA_REGION12_HIGH_V << TEE_DMA_REGION12_HIGH_S) -#define TEE_DMA_REGION12_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION12_HIGH_S 12 - -/** TEE_DMA_REGION13_LOW_REG register - * Region13 address low register. - */ -#define TEE_DMA_REGION13_LOW_REG (DR_REG_TEE_DMA_BASE + 0x70) -/** TEE_DMA_REGION13_LOW : R/W; bitpos: [31:12]; default: 0; - * Region13 address low. - */ -#define TEE_DMA_REGION13_LOW 0x000FFFFFU -#define TEE_DMA_REGION13_LOW_M (TEE_DMA_REGION13_LOW_V << TEE_DMA_REGION13_LOW_S) -#define TEE_DMA_REGION13_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION13_LOW_S 12 - -/** TEE_DMA_REGION13_HIGH_REG register - * Region13 address high register. - */ -#define TEE_DMA_REGION13_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x74) -/** TEE_DMA_REGION13_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region13 address high. - */ -#define TEE_DMA_REGION13_HIGH 0x000FFFFFU -#define TEE_DMA_REGION13_HIGH_M (TEE_DMA_REGION13_HIGH_V << TEE_DMA_REGION13_HIGH_S) -#define TEE_DMA_REGION13_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION13_HIGH_S 12 - -/** TEE_DMA_REGION14_LOW_REG register - * Region14 address low register. - */ -#define TEE_DMA_REGION14_LOW_REG (DR_REG_TEE_DMA_BASE + 0x78) -/** TEE_DMA_REGION14_LOW : R/W; bitpos: [31:12]; default: 0; - * Region14 address low. - */ -#define TEE_DMA_REGION14_LOW 0x000FFFFFU -#define TEE_DMA_REGION14_LOW_M (TEE_DMA_REGION14_LOW_V << TEE_DMA_REGION14_LOW_S) -#define TEE_DMA_REGION14_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION14_LOW_S 12 - -/** TEE_DMA_REGION14_HIGH_REG register - * Region14 address high register. - */ -#define TEE_DMA_REGION14_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x7c) -/** TEE_DMA_REGION14_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region14 address high. - */ -#define TEE_DMA_REGION14_HIGH 0x000FFFFFU -#define TEE_DMA_REGION14_HIGH_M (TEE_DMA_REGION14_HIGH_V << TEE_DMA_REGION14_HIGH_S) -#define TEE_DMA_REGION14_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION14_HIGH_S 12 - -/** TEE_DMA_REGION15_LOW_REG register - * Region15 address low register. - */ -#define TEE_DMA_REGION15_LOW_REG (DR_REG_TEE_DMA_BASE + 0x80) -/** TEE_DMA_REGION15_LOW : R/W; bitpos: [31:12]; default: 0; - * Region15 address low. - */ -#define TEE_DMA_REGION15_LOW 0x000FFFFFU -#define TEE_DMA_REGION15_LOW_M (TEE_DMA_REGION15_LOW_V << TEE_DMA_REGION15_LOW_S) -#define TEE_DMA_REGION15_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION15_LOW_S 12 - -/** TEE_DMA_REGION15_HIGH_REG register - * Region15 address high register. - */ -#define TEE_DMA_REGION15_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x84) -/** TEE_DMA_REGION15_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region15 address high. - */ -#define TEE_DMA_REGION15_HIGH 0x000FFFFFU -#define TEE_DMA_REGION15_HIGH_M (TEE_DMA_REGION15_HIGH_V << TEE_DMA_REGION15_HIGH_S) -#define TEE_DMA_REGION15_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION15_HIGH_S 12 - -/** TEE_DMA_REGION16_LOW_REG register - * Region16 address low register. - */ -#define TEE_DMA_REGION16_LOW_REG (DR_REG_TEE_DMA_BASE + 0x88) -/** TEE_DMA_REGION16_LOW : R/W; bitpos: [31:12]; default: 0; - * Region16 address low. - */ -#define TEE_DMA_REGION16_LOW 0x000FFFFFU -#define TEE_DMA_REGION16_LOW_M (TEE_DMA_REGION16_LOW_V << TEE_DMA_REGION16_LOW_S) -#define TEE_DMA_REGION16_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION16_LOW_S 12 - -/** TEE_DMA_REGION16_HIGH_REG register - * Region16 address high register. - */ -#define TEE_DMA_REGION16_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x8c) -/** TEE_DMA_REGION16_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region16 address high. - */ -#define TEE_DMA_REGION16_HIGH 0x000FFFFFU -#define TEE_DMA_REGION16_HIGH_M (TEE_DMA_REGION16_HIGH_V << TEE_DMA_REGION16_HIGH_S) -#define TEE_DMA_REGION16_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION16_HIGH_S 12 - -/** TEE_DMA_REGION17_LOW_REG register - * Region17 address low register. - */ -#define TEE_DMA_REGION17_LOW_REG (DR_REG_TEE_DMA_BASE + 0x90) -/** TEE_DMA_REGION17_LOW : R/W; bitpos: [31:12]; default: 0; - * Region17 address low. - */ -#define TEE_DMA_REGION17_LOW 0x000FFFFFU -#define TEE_DMA_REGION17_LOW_M (TEE_DMA_REGION17_LOW_V << TEE_DMA_REGION17_LOW_S) -#define TEE_DMA_REGION17_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION17_LOW_S 12 - -/** TEE_DMA_REGION17_HIGH_REG register - * Region17 address high register. - */ -#define TEE_DMA_REGION17_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x94) -/** TEE_DMA_REGION17_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region17 address high. - */ -#define TEE_DMA_REGION17_HIGH 0x000FFFFFU -#define TEE_DMA_REGION17_HIGH_M (TEE_DMA_REGION17_HIGH_V << TEE_DMA_REGION17_HIGH_S) -#define TEE_DMA_REGION17_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION17_HIGH_S 12 - -/** TEE_DMA_REGION18_LOW_REG register - * Region18 address low register. - */ -#define TEE_DMA_REGION18_LOW_REG (DR_REG_TEE_DMA_BASE + 0x98) -/** TEE_DMA_REGION18_LOW : R/W; bitpos: [31:12]; default: 0; - * Region18 address low. - */ -#define TEE_DMA_REGION18_LOW 0x000FFFFFU -#define TEE_DMA_REGION18_LOW_M (TEE_DMA_REGION18_LOW_V << TEE_DMA_REGION18_LOW_S) -#define TEE_DMA_REGION18_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION18_LOW_S 12 - -/** TEE_DMA_REGION18_HIGH_REG register - * Region18 address high register. - */ -#define TEE_DMA_REGION18_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x9c) -/** TEE_DMA_REGION18_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region18 address high. - */ -#define TEE_DMA_REGION18_HIGH 0x000FFFFFU -#define TEE_DMA_REGION18_HIGH_M (TEE_DMA_REGION18_HIGH_V << TEE_DMA_REGION18_HIGH_S) -#define TEE_DMA_REGION18_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION18_HIGH_S 12 - -/** TEE_DMA_REGION19_LOW_REG register - * Region19 address low register. - */ -#define TEE_DMA_REGION19_LOW_REG (DR_REG_TEE_DMA_BASE + 0xa0) -/** TEE_DMA_REGION19_LOW : R/W; bitpos: [31:12]; default: 0; - * Region19 address low. - */ -#define TEE_DMA_REGION19_LOW 0x000FFFFFU -#define TEE_DMA_REGION19_LOW_M (TEE_DMA_REGION19_LOW_V << TEE_DMA_REGION19_LOW_S) -#define TEE_DMA_REGION19_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION19_LOW_S 12 - -/** TEE_DMA_REGION19_HIGH_REG register - * Region19 address high register. - */ -#define TEE_DMA_REGION19_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xa4) -/** TEE_DMA_REGION19_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region19 address high. - */ -#define TEE_DMA_REGION19_HIGH 0x000FFFFFU -#define TEE_DMA_REGION19_HIGH_M (TEE_DMA_REGION19_HIGH_V << TEE_DMA_REGION19_HIGH_S) -#define TEE_DMA_REGION19_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION19_HIGH_S 12 - -/** TEE_DMA_REGION20_LOW_REG register - * Region20 address low register. - */ -#define TEE_DMA_REGION20_LOW_REG (DR_REG_TEE_DMA_BASE + 0xa8) -/** TEE_DMA_REGION20_LOW : R/W; bitpos: [31:12]; default: 0; - * Region20 address low. - */ -#define TEE_DMA_REGION20_LOW 0x000FFFFFU -#define TEE_DMA_REGION20_LOW_M (TEE_DMA_REGION20_LOW_V << TEE_DMA_REGION20_LOW_S) -#define TEE_DMA_REGION20_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION20_LOW_S 12 - -/** TEE_DMA_REGION20_HIGH_REG register - * Region20 address high register. - */ -#define TEE_DMA_REGION20_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xac) -/** TEE_DMA_REGION20_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region20 address high. - */ -#define TEE_DMA_REGION20_HIGH 0x000FFFFFU -#define TEE_DMA_REGION20_HIGH_M (TEE_DMA_REGION20_HIGH_V << TEE_DMA_REGION20_HIGH_S) -#define TEE_DMA_REGION20_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION20_HIGH_S 12 - -/** TEE_DMA_REGION21_LOW_REG register - * Region21 address low register. - */ -#define TEE_DMA_REGION21_LOW_REG (DR_REG_TEE_DMA_BASE + 0xb0) -/** TEE_DMA_REGION21_LOW : R/W; bitpos: [31:12]; default: 0; - * Region21 address low. - */ -#define TEE_DMA_REGION21_LOW 0x000FFFFFU -#define TEE_DMA_REGION21_LOW_M (TEE_DMA_REGION21_LOW_V << TEE_DMA_REGION21_LOW_S) -#define TEE_DMA_REGION21_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION21_LOW_S 12 - -/** TEE_DMA_REGION21_HIGH_REG register - * Region21 address high register. - */ -#define TEE_DMA_REGION21_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xb4) -/** TEE_DMA_REGION21_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region21 address high. - */ -#define TEE_DMA_REGION21_HIGH 0x000FFFFFU -#define TEE_DMA_REGION21_HIGH_M (TEE_DMA_REGION21_HIGH_V << TEE_DMA_REGION21_HIGH_S) -#define TEE_DMA_REGION21_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION21_HIGH_S 12 - -/** TEE_DMA_REGION22_LOW_REG register - * Region22 address low register. - */ -#define TEE_DMA_REGION22_LOW_REG (DR_REG_TEE_DMA_BASE + 0xb8) -/** TEE_DMA_REGION22_LOW : R/W; bitpos: [31:12]; default: 0; - * Region22 address low. - */ -#define TEE_DMA_REGION22_LOW 0x000FFFFFU -#define TEE_DMA_REGION22_LOW_M (TEE_DMA_REGION22_LOW_V << TEE_DMA_REGION22_LOW_S) -#define TEE_DMA_REGION22_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION22_LOW_S 12 - -/** TEE_DMA_REGION22_HIGH_REG register - * Region22 address high register. - */ -#define TEE_DMA_REGION22_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xbc) -/** TEE_DMA_REGION22_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region22 address high. - */ -#define TEE_DMA_REGION22_HIGH 0x000FFFFFU -#define TEE_DMA_REGION22_HIGH_M (TEE_DMA_REGION22_HIGH_V << TEE_DMA_REGION22_HIGH_S) -#define TEE_DMA_REGION22_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION22_HIGH_S 12 - -/** TEE_DMA_REGION23_LOW_REG register - * Region23 address low register. - */ -#define TEE_DMA_REGION23_LOW_REG (DR_REG_TEE_DMA_BASE + 0xc0) -/** TEE_DMA_REGION23_LOW : R/W; bitpos: [31:12]; default: 0; - * Region23 address low. - */ -#define TEE_DMA_REGION23_LOW 0x000FFFFFU -#define TEE_DMA_REGION23_LOW_M (TEE_DMA_REGION23_LOW_V << TEE_DMA_REGION23_LOW_S) -#define TEE_DMA_REGION23_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION23_LOW_S 12 - -/** TEE_DMA_REGION23_HIGH_REG register - * Region23 address high register. - */ -#define TEE_DMA_REGION23_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xc4) -/** TEE_DMA_REGION23_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region23 address high. - */ -#define TEE_DMA_REGION23_HIGH 0x000FFFFFU -#define TEE_DMA_REGION23_HIGH_M (TEE_DMA_REGION23_HIGH_V << TEE_DMA_REGION23_HIGH_S) -#define TEE_DMA_REGION23_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION23_HIGH_S 12 - -/** TEE_DMA_REGION24_LOW_REG register - * Region24 address low register. - */ -#define TEE_DMA_REGION24_LOW_REG (DR_REG_TEE_DMA_BASE + 0xc8) -/** TEE_DMA_REGION24_LOW : R/W; bitpos: [31:12]; default: 0; - * Region24 address low. - */ -#define TEE_DMA_REGION24_LOW 0x000FFFFFU -#define TEE_DMA_REGION24_LOW_M (TEE_DMA_REGION24_LOW_V << TEE_DMA_REGION24_LOW_S) -#define TEE_DMA_REGION24_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION24_LOW_S 12 - -/** TEE_DMA_REGION24_HIGH_REG register - * Region24 address high register. - */ -#define TEE_DMA_REGION24_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xcc) -/** TEE_DMA_REGION24_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region24 address high. - */ -#define TEE_DMA_REGION24_HIGH 0x000FFFFFU -#define TEE_DMA_REGION24_HIGH_M (TEE_DMA_REGION24_HIGH_V << TEE_DMA_REGION24_HIGH_S) -#define TEE_DMA_REGION24_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION24_HIGH_S 12 - -/** TEE_DMA_REGION25_LOW_REG register - * Region25 address low register. - */ -#define TEE_DMA_REGION25_LOW_REG (DR_REG_TEE_DMA_BASE + 0xd0) -/** TEE_DMA_REGION25_LOW : R/W; bitpos: [31:12]; default: 0; - * Region25 address low. - */ -#define TEE_DMA_REGION25_LOW 0x000FFFFFU -#define TEE_DMA_REGION25_LOW_M (TEE_DMA_REGION25_LOW_V << TEE_DMA_REGION25_LOW_S) -#define TEE_DMA_REGION25_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION25_LOW_S 12 - -/** TEE_DMA_REGION25_HIGH_REG register - * Region25 address high register. - */ -#define TEE_DMA_REGION25_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xd4) -/** TEE_DMA_REGION25_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region25 address high. - */ -#define TEE_DMA_REGION25_HIGH 0x000FFFFFU -#define TEE_DMA_REGION25_HIGH_M (TEE_DMA_REGION25_HIGH_V << TEE_DMA_REGION25_HIGH_S) -#define TEE_DMA_REGION25_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION25_HIGH_S 12 - -/** TEE_DMA_REGION26_LOW_REG register - * Region26 address low register. - */ -#define TEE_DMA_REGION26_LOW_REG (DR_REG_TEE_DMA_BASE + 0xd8) -/** TEE_DMA_REGION26_LOW : R/W; bitpos: [31:12]; default: 0; - * Region26 address low. - */ -#define TEE_DMA_REGION26_LOW 0x000FFFFFU -#define TEE_DMA_REGION26_LOW_M (TEE_DMA_REGION26_LOW_V << TEE_DMA_REGION26_LOW_S) -#define TEE_DMA_REGION26_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION26_LOW_S 12 - -/** TEE_DMA_REGION26_HIGH_REG register - * Region26 address high register. - */ -#define TEE_DMA_REGION26_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xdc) -/** TEE_DMA_REGION26_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region26 address high. - */ -#define TEE_DMA_REGION26_HIGH 0x000FFFFFU -#define TEE_DMA_REGION26_HIGH_M (TEE_DMA_REGION26_HIGH_V << TEE_DMA_REGION26_HIGH_S) -#define TEE_DMA_REGION26_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION26_HIGH_S 12 - -/** TEE_DMA_REGION27_LOW_REG register - * Region27 address low register. - */ -#define TEE_DMA_REGION27_LOW_REG (DR_REG_TEE_DMA_BASE + 0xe0) -/** TEE_DMA_REGION27_LOW : R/W; bitpos: [31:12]; default: 0; - * Region27 address low. - */ -#define TEE_DMA_REGION27_LOW 0x000FFFFFU -#define TEE_DMA_REGION27_LOW_M (TEE_DMA_REGION27_LOW_V << TEE_DMA_REGION27_LOW_S) -#define TEE_DMA_REGION27_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION27_LOW_S 12 - -/** TEE_DMA_REGION27_HIGH_REG register - * Region27 address high register. - */ -#define TEE_DMA_REGION27_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xe4) -/** TEE_DMA_REGION27_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region27 address high. - */ -#define TEE_DMA_REGION27_HIGH 0x000FFFFFU -#define TEE_DMA_REGION27_HIGH_M (TEE_DMA_REGION27_HIGH_V << TEE_DMA_REGION27_HIGH_S) -#define TEE_DMA_REGION27_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION27_HIGH_S 12 - -/** TEE_DMA_REGION28_LOW_REG register - * Region28 address low register. - */ -#define TEE_DMA_REGION28_LOW_REG (DR_REG_TEE_DMA_BASE + 0xe8) -/** TEE_DMA_REGION28_LOW : R/W; bitpos: [31:12]; default: 0; - * Region28 address low. - */ -#define TEE_DMA_REGION28_LOW 0x000FFFFFU -#define TEE_DMA_REGION28_LOW_M (TEE_DMA_REGION28_LOW_V << TEE_DMA_REGION28_LOW_S) -#define TEE_DMA_REGION28_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION28_LOW_S 12 - -/** TEE_DMA_REGION28_HIGH_REG register - * Region28 address high register. - */ -#define TEE_DMA_REGION28_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xec) -/** TEE_DMA_REGION28_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region28 address high. - */ -#define TEE_DMA_REGION28_HIGH 0x000FFFFFU -#define TEE_DMA_REGION28_HIGH_M (TEE_DMA_REGION28_HIGH_V << TEE_DMA_REGION28_HIGH_S) -#define TEE_DMA_REGION28_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION28_HIGH_S 12 - -/** TEE_DMA_REGION29_LOW_REG register - * Region29 address low register. - */ -#define TEE_DMA_REGION29_LOW_REG (DR_REG_TEE_DMA_BASE + 0xf0) -/** TEE_DMA_REGION29_LOW : R/W; bitpos: [31:12]; default: 0; - * Region29 address low. - */ -#define TEE_DMA_REGION29_LOW 0x000FFFFFU -#define TEE_DMA_REGION29_LOW_M (TEE_DMA_REGION29_LOW_V << TEE_DMA_REGION29_LOW_S) -#define TEE_DMA_REGION29_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION29_LOW_S 12 - -/** TEE_DMA_REGION29_HIGH_REG register - * Region29 address high register. - */ -#define TEE_DMA_REGION29_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xf4) -/** TEE_DMA_REGION29_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region29 address high. - */ -#define TEE_DMA_REGION29_HIGH 0x000FFFFFU -#define TEE_DMA_REGION29_HIGH_M (TEE_DMA_REGION29_HIGH_V << TEE_DMA_REGION29_HIGH_S) -#define TEE_DMA_REGION29_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION29_HIGH_S 12 - -/** TEE_DMA_REGION30_LOW_REG register - * Region30 address low register. - */ -#define TEE_DMA_REGION30_LOW_REG (DR_REG_TEE_DMA_BASE + 0xf8) -/** TEE_DMA_REGION30_LOW : R/W; bitpos: [31:12]; default: 0; - * Region30 address low. - */ -#define TEE_DMA_REGION30_LOW 0x000FFFFFU -#define TEE_DMA_REGION30_LOW_M (TEE_DMA_REGION30_LOW_V << TEE_DMA_REGION30_LOW_S) -#define TEE_DMA_REGION30_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION30_LOW_S 12 - -/** TEE_DMA_REGION30_HIGH_REG register - * Region30 address high register. - */ -#define TEE_DMA_REGION30_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xfc) -/** TEE_DMA_REGION30_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region30 address high. - */ -#define TEE_DMA_REGION30_HIGH 0x000FFFFFU -#define TEE_DMA_REGION30_HIGH_M (TEE_DMA_REGION30_HIGH_V << TEE_DMA_REGION30_HIGH_S) -#define TEE_DMA_REGION30_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION30_HIGH_S 12 - -/** TEE_DMA_REGION31_LOW_REG register - * Region31 address low register. - */ -#define TEE_DMA_REGION31_LOW_REG (DR_REG_TEE_DMA_BASE + 0x100) -/** TEE_DMA_REGION31_LOW : R/W; bitpos: [31:12]; default: 0; - * Region31 address low. - */ -#define TEE_DMA_REGION31_LOW 0x000FFFFFU -#define TEE_DMA_REGION31_LOW_M (TEE_DMA_REGION31_LOW_V << TEE_DMA_REGION31_LOW_S) -#define TEE_DMA_REGION31_LOW_V 0x000FFFFFU -#define TEE_DMA_REGION31_LOW_S 12 - -/** TEE_DMA_REGION31_HIGH_REG register - * Region31 address high register. - */ -#define TEE_DMA_REGION31_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x104) -/** TEE_DMA_REGION31_HIGH : R/W; bitpos: [31:12]; default: 1048575; - * Region31 address high. - */ -#define TEE_DMA_REGION31_HIGH 0x000FFFFFU -#define TEE_DMA_REGION31_HIGH_M (TEE_DMA_REGION31_HIGH_V << TEE_DMA_REGION31_HIGH_S) -#define TEE_DMA_REGION31_HIGH_V 0x000FFFFFU -#define TEE_DMA_REGION31_HIGH_S 12 - -/** TEE_DMA_GMDA_CH0_R_PMS_REG register - * GDMA ch0 read permission control registers. - */ -#define TEE_DMA_GMDA_CH0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x108) -/** TEE_DMA_GDMA_CH0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch0 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GDMA_CH0_R_PMS 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH0_R_PMS_M (TEE_DMA_GDMA_CH0_R_PMS_V << TEE_DMA_GDMA_CH0_R_PMS_S) -#define TEE_DMA_GDMA_CH0_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH0_R_PMS_S 0 - -/** TEE_DMA_GMDA_CH0_W_PMS_REG register - * GDMA ch0 write permission control registers. - */ -#define TEE_DMA_GMDA_CH0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x10c) -/** TEE_DMA_GDMA_CH0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch0 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GDMA_CH0_W_PMS 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH0_W_PMS_M (TEE_DMA_GDMA_CH0_W_PMS_V << TEE_DMA_GDMA_CH0_W_PMS_S) -#define TEE_DMA_GDMA_CH0_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH0_W_PMS_S 0 - -/** TEE_DMA_GMDA_CH1_R_PMS_REG register - * GDMA ch1 read permission control registers. - */ -#define TEE_DMA_GMDA_CH1_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x110) -/** TEE_DMA_GDMA_CH1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch1 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GDMA_CH1_R_PMS 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH1_R_PMS_M (TEE_DMA_GDMA_CH1_R_PMS_V << TEE_DMA_GDMA_CH1_R_PMS_S) -#define TEE_DMA_GDMA_CH1_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH1_R_PMS_S 0 - -/** TEE_DMA_GMDA_CH1_W_PMS_REG register - * GDMA ch1 write permission control registers. - */ -#define TEE_DMA_GMDA_CH1_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x114) -/** TEE_DMA_GDMA_CH1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch1 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GDMA_CH1_W_PMS 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH1_W_PMS_M (TEE_DMA_GDMA_CH1_W_PMS_V << TEE_DMA_GDMA_CH1_W_PMS_S) -#define TEE_DMA_GDMA_CH1_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH1_W_PMS_S 0 - -/** TEE_DMA_GMDA_CH2_R_PMS_REG register - * GDMA ch2 read permission control registers. - */ -#define TEE_DMA_GMDA_CH2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x118) -/** TEE_DMA_GDMA_CH2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch2 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GDMA_CH2_R_PMS 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH2_R_PMS_M (TEE_DMA_GDMA_CH2_R_PMS_V << TEE_DMA_GDMA_CH2_R_PMS_S) -#define TEE_DMA_GDMA_CH2_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH2_R_PMS_S 0 - -/** TEE_DMA_GMDA_CH2_W_PMS_REG register - * GDMA ch2 write permission control registers. - */ -#define TEE_DMA_GMDA_CH2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x11c) -/** TEE_DMA_GDMA_CH2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch2 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GDMA_CH2_W_PMS 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH2_W_PMS_M (TEE_DMA_GDMA_CH2_W_PMS_V << TEE_DMA_GDMA_CH2_W_PMS_S) -#define TEE_DMA_GDMA_CH2_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH2_W_PMS_S 0 - -/** TEE_DMA_GMDA_CH3_R_PMS_REG register - * GDMA ch3 read permission control registers. - */ -#define TEE_DMA_GMDA_CH3_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x120) -/** TEE_DMA_GDMA_CH3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch3 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GDMA_CH3_R_PMS 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH3_R_PMS_M (TEE_DMA_GDMA_CH3_R_PMS_V << TEE_DMA_GDMA_CH3_R_PMS_S) -#define TEE_DMA_GDMA_CH3_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH3_R_PMS_S 0 - -/** TEE_DMA_GMDA_CH3_W_PMS_REG register - * GDMA ch3 write permission control registers. - */ -#define TEE_DMA_GMDA_CH3_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x124) -/** TEE_DMA_GDMA_CH3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch3 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GDMA_CH3_W_PMS 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH3_W_PMS_M (TEE_DMA_GDMA_CH3_W_PMS_V << TEE_DMA_GDMA_CH3_W_PMS_S) -#define TEE_DMA_GDMA_CH3_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GDMA_CH3_W_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_ADC_R_PMS_REG register - * AHB PDMA adc read permission control registers. - */ -#define TEE_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x128) -/** TEE_DMA_AHB_PDMA_ADC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA adc read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_ADC_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_ADC_R_PMS_M (TEE_DMA_AHB_PDMA_ADC_R_PMS_V << TEE_DMA_AHB_PDMA_ADC_R_PMS_S) -#define TEE_DMA_AHB_PDMA_ADC_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_ADC_R_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_ADC_W_PMS_REG register - * AHB PDMA adc write permission control registers. - */ -#define TEE_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x12c) -/** TEE_DMA_AHB_PDMA_ADC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA adc write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_ADC_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_ADC_W_PMS_M (TEE_DMA_AHB_PDMA_ADC_W_PMS_V << TEE_DMA_AHB_PDMA_ADC_W_PMS_S) -#define TEE_DMA_AHB_PDMA_ADC_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_ADC_W_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_I2S0_R_PMS_REG register - * AHB PDMA i2s0 read permission control registers. - */ -#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x130) -/** TEE_DMA_AHB_PDMA_I2S0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s0 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_I2S0_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_M (TEE_DMA_AHB_PDMA_I2S0_R_PMS_V << TEE_DMA_AHB_PDMA_I2S0_R_PMS_S) -#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_I2S0_W_PMS_REG register - * AHB PDMA i2s0 write permission control registers. - */ -#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x134) -/** TEE_DMA_AHB_PDMA_I2S0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s0 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_I2S0_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_M (TEE_DMA_AHB_PDMA_I2S0_W_PMS_V << TEE_DMA_AHB_PDMA_I2S0_W_PMS_S) -#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_I2S1_R_PMS_REG register - * AHB PDMA i2s1 read permission control registers. - */ -#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x138) -/** TEE_DMA_AHB_PDMA_I2S1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s1 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_I2S1_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_M (TEE_DMA_AHB_PDMA_I2S1_R_PMS_V << TEE_DMA_AHB_PDMA_I2S1_R_PMS_S) -#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_I2S1_W_PMS_REG register - * AHB PDMA i2s1 write permission control registers. - */ -#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x13c) -/** TEE_DMA_AHB_PDMA_I2S1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s1 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_I2S1_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_M (TEE_DMA_AHB_PDMA_I2S1_W_PMS_V << TEE_DMA_AHB_PDMA_I2S1_W_PMS_S) -#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_I2S2_R_PMS_REG register - * AHB PDMA i2s2 read permission control registers. - */ -#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x140) -/** TEE_DMA_AHB_PDMA_I2S2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s2 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_I2S2_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_M (TEE_DMA_AHB_PDMA_I2S2_R_PMS_V << TEE_DMA_AHB_PDMA_I2S2_R_PMS_S) -#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_I2S2_W_PMS_REG register - * AHB PDMA i2s2 write permission control registers. - */ -#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x144) -/** TEE_DMA_AHB_PDMA_I2S2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s2 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_I2S2_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_M (TEE_DMA_AHB_PDMA_I2S2_W_PMS_V << TEE_DMA_AHB_PDMA_I2S2_W_PMS_S) -#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_REG register - * AHB PDMA i3s mst read permission control registers. - */ -#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x148) -/** TEE_DMA_AHB_PDMA_I3C_MST_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i3c mst read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_M (TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_V << TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_S) -#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_REG register - * AHB PDMA i3c mst write permission control registers. - */ -#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x14c) -/** TEE_DMA_AHB_PDMA_I3C_MST_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i3c mst write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_M (TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_V << TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_S) -#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_UHCI0_R_PMS_REG register - * AHB PDMA uhci0 read permission control registers. - */ -#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x150) -/** TEE_DMA_AHB_PDMA_UHCI0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA uhci0 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_M (TEE_DMA_AHB_PDMA_UHCI0_R_PMS_V << TEE_DMA_AHB_PDMA_UHCI0_R_PMS_S) -#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_UHCI0_W_PMS_REG register - * AHB PDMA uhci0 write permission control registers. - */ -#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x154) -/** TEE_DMA_AHB_PDMA_UHCI0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA uhci0 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_M (TEE_DMA_AHB_PDMA_UHCI0_W_PMS_V << TEE_DMA_AHB_PDMA_UHCI0_W_PMS_S) -#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_RMT_R_PMS_REG register - * AHB PDMA rmt read permission control registers. - */ -#define TEE_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x158) -/** TEE_DMA_AHB_PDMA_RMT_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA rmt read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_RMT_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_RMT_R_PMS_M (TEE_DMA_AHB_PDMA_RMT_R_PMS_V << TEE_DMA_AHB_PDMA_RMT_R_PMS_S) -#define TEE_DMA_AHB_PDMA_RMT_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_RMT_R_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_RMT_W_PMS_REG register - * AHB PDMA rmt write permission control registers. - */ -#define TEE_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x170) -/** TEE_DMA_AHB_PDMA_RMT_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA rmt write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_RMT_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_RMT_W_PMS_M (TEE_DMA_AHB_PDMA_RMT_W_PMS_V << TEE_DMA_AHB_PDMA_RMT_W_PMS_S) -#define TEE_DMA_AHB_PDMA_RMT_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_RMT_W_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_REG register - * AXI PDMA lcdcam read permission control registers. - */ -#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x174) -/** TEE_DMA_AXI_PDMA_LCDCAM_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA lcdcam read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_M (TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_V << TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_S) -#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_REG register - * AXI PDMA lcdcam write permission control registers. - */ -#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x178) -/** TEE_DMA_AXI_PDMA_LCDCAM_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA lcdcam write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_M (TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_V << TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_S) -#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_REG register - * AXI PDMA gpspi2 read permission control registers. - */ -#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x17c) -/** TEE_DMA_AXI_PDMA_GPSPI2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA gpspi2 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_M (TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_V << TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_S) -#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_REG register - * AXI PDMA gpspi2 write permission control registers. - */ -#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x180) -/** TEE_DMA_AXI_PDMA_GPSPI2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA gpspi2 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_M (TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_V << TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_S) -#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_REG register - * AXI PDMA gpspi3 read permission control registers. - */ -#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x184) -/** TEE_DMA_AXI_PDMA_GPSPI3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA gpspi3 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_M (TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_V << TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_S) -#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_REG register - * AXI PDMA gpspi3 write permission control registers. - */ -#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x188) -/** TEE_DMA_AXI_PDMA_GPSPI3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA gpspi3 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_M (TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_V << TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_S) -#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_PARLIO_R_PMS_REG register - * AXI PDMA parl io read permission control registers. - */ -#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x18c) -/** TEE_DMA_AXI_PDMA_PARLIO_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA parl io read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_M (TEE_DMA_AXI_PDMA_PARLIO_R_PMS_V << TEE_DMA_AXI_PDMA_PARLIO_R_PMS_S) -#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_PARLIO_W_PMS_REG register - * AXI PDMA parl io write permission control registers. - */ -#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x190) -/** TEE_DMA_AXI_PDMA_PARLIO_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA parl io write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_M (TEE_DMA_AXI_PDMA_PARLIO_W_PMS_V << TEE_DMA_AXI_PDMA_PARLIO_W_PMS_S) -#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_AES_R_PMS_REG register - * AXI PDMA aes read permission control registers. - */ -#define TEE_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x194) -/** TEE_DMA_AXI_PDMA_AES_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA aes read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_AES_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_AES_R_PMS_M (TEE_DMA_AXI_PDMA_AES_R_PMS_V << TEE_DMA_AXI_PDMA_AES_R_PMS_S) -#define TEE_DMA_AXI_PDMA_AES_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_AES_R_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_AES_W_PMS_REG register - * AXI PDMA aes write permission control registers. - */ -#define TEE_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x198) -/** TEE_DMA_AXI_PDMA_AES_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA aes write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_AES_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_AES_W_PMS_M (TEE_DMA_AXI_PDMA_AES_W_PMS_V << TEE_DMA_AXI_PDMA_AES_W_PMS_S) -#define TEE_DMA_AXI_PDMA_AES_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_AES_W_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_SHA_R_PMS_REG register - * AXI PDMA sha read permission control registers. - */ -#define TEE_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x19c) -/** TEE_DMA_AXI_PDMA_SHA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA sha read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_SHA_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_SHA_R_PMS_M (TEE_DMA_AXI_PDMA_SHA_R_PMS_V << TEE_DMA_AXI_PDMA_SHA_R_PMS_S) -#define TEE_DMA_AXI_PDMA_SHA_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_SHA_R_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_SHA_W_PMS_REG register - * AXI PDMA sha write permission control registers. - */ -#define TEE_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x1a0) -/** TEE_DMA_AXI_PDMA_SHA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA sha write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_SHA_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_SHA_W_PMS_M (TEE_DMA_AXI_PDMA_SHA_W_PMS_V << TEE_DMA_AXI_PDMA_SHA_W_PMS_S) -#define TEE_DMA_AXI_PDMA_SHA_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_SHA_W_PMS_S 0 - -/** TEE_DMA_DMA2D_JPEG_PMS_R_REG register - * DMA2D JPEG read permission control registers. - */ -#define TEE_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1a4) -/** TEE_DMA_DMA2D_JPEG_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D JPEG read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_DMA2D_JPEG_R_PMS 0xFFFFFFFFU -#define TEE_DMA_DMA2D_JPEG_R_PMS_M (TEE_DMA_DMA2D_JPEG_R_PMS_V << TEE_DMA_DMA2D_JPEG_R_PMS_S) -#define TEE_DMA_DMA2D_JPEG_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_DMA2D_JPEG_R_PMS_S 0 - -/** TEE_DMA_DMA2D_JPEG_PMS_W_REG register - * DMA2D JPEG write permission control registers. - */ -#define TEE_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1a8) -/** TEE_DMA_DMA2D_JPEG_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D JPEG write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_DMA2D_JPEG_W_PMS 0xFFFFFFFFU -#define TEE_DMA_DMA2D_JPEG_W_PMS_M (TEE_DMA_DMA2D_JPEG_W_PMS_V << TEE_DMA_DMA2D_JPEG_W_PMS_S) -#define TEE_DMA_DMA2D_JPEG_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_DMA2D_JPEG_W_PMS_S 0 - -/** TEE_DMA_USB_PMS_R_REG register - * USB read permission control registers. - */ -#define TEE_DMA_USB_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1ac) -/** TEE_DMA_USB_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * USB read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_USB_R_PMS 0xFFFFFFFFU -#define TEE_DMA_USB_R_PMS_M (TEE_DMA_USB_R_PMS_V << TEE_DMA_USB_R_PMS_S) -#define TEE_DMA_USB_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_USB_R_PMS_S 0 - -/** TEE_DMA_USB_PMS_W_REG register - * USB write permission control registers. - */ -#define TEE_DMA_USB_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1b0) -/** TEE_DMA_USB_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * USB write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_USB_W_PMS 0xFFFFFFFFU -#define TEE_DMA_USB_W_PMS_M (TEE_DMA_USB_W_PMS_V << TEE_DMA_USB_W_PMS_S) -#define TEE_DMA_USB_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_USB_W_PMS_S 0 - -/** TEE_DMA_GMAC_PMS_R_REG register - * GMAC read permission control registers. - */ -#define TEE_DMA_GMAC_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1b4) -/** TEE_DMA_GMAC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GMAC read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GMAC_R_PMS 0xFFFFFFFFU -#define TEE_DMA_GMAC_R_PMS_M (TEE_DMA_GMAC_R_PMS_V << TEE_DMA_GMAC_R_PMS_S) -#define TEE_DMA_GMAC_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GMAC_R_PMS_S 0 - -/** TEE_DMA_GMAC_PMS_W_REG register - * GMAC write permission control registers. - */ -#define TEE_DMA_GMAC_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1b8) -/** TEE_DMA_GMAC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * GMAC write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_GMAC_W_PMS 0xFFFFFFFFU -#define TEE_DMA_GMAC_W_PMS_M (TEE_DMA_GMAC_W_PMS_V << TEE_DMA_GMAC_W_PMS_S) -#define TEE_DMA_GMAC_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_GMAC_W_PMS_S 0 - -/** TEE_DMA_SDMMC_PMS_R_REG register - * SDMMC read permission control registers. - */ -#define TEE_DMA_SDMMC_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1bc) -/** TEE_DMA_SDMMC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * SDMMC read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_SDMMC_R_PMS 0xFFFFFFFFU -#define TEE_DMA_SDMMC_R_PMS_M (TEE_DMA_SDMMC_R_PMS_V << TEE_DMA_SDMMC_R_PMS_S) -#define TEE_DMA_SDMMC_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_SDMMC_R_PMS_S 0 - -/** TEE_DMA_SDMMC_PMS_W_REG register - * SDMMC write permission control registers. - */ -#define TEE_DMA_SDMMC_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1c0) -/** TEE_DMA_SDMMC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * SDMMC write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_SDMMC_W_PMS 0xFFFFFFFFU -#define TEE_DMA_SDMMC_W_PMS_M (TEE_DMA_SDMMC_W_PMS_V << TEE_DMA_SDMMC_W_PMS_S) -#define TEE_DMA_SDMMC_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_SDMMC_W_PMS_S 0 - -/** TEE_DMA_USBOTG11_PMS_R_REG register - * USBOTG11 read permission control registers. - */ -#define TEE_DMA_USBOTG11_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1c4) -/** TEE_DMA_USBOTG11_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * USBOTG11 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_USBOTG11_R_PMS 0xFFFFFFFFU -#define TEE_DMA_USBOTG11_R_PMS_M (TEE_DMA_USBOTG11_R_PMS_V << TEE_DMA_USBOTG11_R_PMS_S) -#define TEE_DMA_USBOTG11_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_USBOTG11_R_PMS_S 0 - -/** TEE_DMA_USBOTG11_PMS_W_REG register - * USBOTG11 write permission control registers. - */ -#define TEE_DMA_USBOTG11_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1c8) -/** TEE_DMA_USBOTG11_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * USBOTG11 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_USBOTG11_W_PMS 0xFFFFFFFFU -#define TEE_DMA_USBOTG11_W_PMS_M (TEE_DMA_USBOTG11_W_PMS_V << TEE_DMA_USBOTG11_W_PMS_S) -#define TEE_DMA_USBOTG11_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_USBOTG11_W_PMS_S 0 - -/** TEE_DMA_TRACE0_PMS_R_REG register - * TRACE0 read permission control registers. - */ -#define TEE_DMA_TRACE0_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1cc) -/** TEE_DMA_TRACE0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * TRACE0 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_TRACE0_R_PMS 0xFFFFFFFFU -#define TEE_DMA_TRACE0_R_PMS_M (TEE_DMA_TRACE0_R_PMS_V << TEE_DMA_TRACE0_R_PMS_S) -#define TEE_DMA_TRACE0_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_TRACE0_R_PMS_S 0 - -/** TEE_DMA_TRACE0_PMS_W_REG register - * TRACE0 write permission control registers. - */ -#define TEE_DMA_TRACE0_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1d0) -/** TEE_DMA_TRACE0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * TRACE0 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_TRACE0_W_PMS 0xFFFFFFFFU -#define TEE_DMA_TRACE0_W_PMS_M (TEE_DMA_TRACE0_W_PMS_V << TEE_DMA_TRACE0_W_PMS_S) -#define TEE_DMA_TRACE0_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_TRACE0_W_PMS_S 0 - -/** TEE_DMA_TRACE1_PMS_R_REG register - * TRACE1 read permission control registers. - */ -#define TEE_DMA_TRACE1_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1d4) -/** TEE_DMA_TRACE1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * TRACE1 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_TRACE1_R_PMS 0xFFFFFFFFU -#define TEE_DMA_TRACE1_R_PMS_M (TEE_DMA_TRACE1_R_PMS_V << TEE_DMA_TRACE1_R_PMS_S) -#define TEE_DMA_TRACE1_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_TRACE1_R_PMS_S 0 - -/** TEE_DMA_TRACE1_PMS_W_REG register - * TRACE1 write permission control registers. - */ -#define TEE_DMA_TRACE1_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1d8) -/** TEE_DMA_TRACE1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * TRACE1 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_TRACE1_W_PMS 0xFFFFFFFFU -#define TEE_DMA_TRACE1_W_PMS_M (TEE_DMA_TRACE1_W_PMS_V << TEE_DMA_TRACE1_W_PMS_S) -#define TEE_DMA_TRACE1_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_TRACE1_W_PMS_S 0 - -/** TEE_DMA_L2MEM_MON_PMS_R_REG register - * L2MEM MON read permission control registers. - */ -#define TEE_DMA_L2MEM_MON_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1dc) -/** TEE_DMA_L2MEM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * L2MEM MON read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_L2MEM_MON_R_PMS 0xFFFFFFFFU -#define TEE_DMA_L2MEM_MON_R_PMS_M (TEE_DMA_L2MEM_MON_R_PMS_V << TEE_DMA_L2MEM_MON_R_PMS_S) -#define TEE_DMA_L2MEM_MON_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_L2MEM_MON_R_PMS_S 0 - -/** TEE_DMA_L2MEM_MON_PMS_W_REG register - * L2MEM MON write permission control registers. - */ -#define TEE_DMA_L2MEM_MON_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1e0) -/** TEE_DMA_L2MEM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * L2MEM MON write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_L2MEM_MON_W_PMS 0xFFFFFFFFU -#define TEE_DMA_L2MEM_MON_W_PMS_M (TEE_DMA_L2MEM_MON_W_PMS_V << TEE_DMA_L2MEM_MON_W_PMS_S) -#define TEE_DMA_L2MEM_MON_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_L2MEM_MON_W_PMS_S 0 - -/** TEE_DMA_TCM_MON_PMS_R_REG register - * TCM MON read permission control registers. - */ -#define TEE_DMA_TCM_MON_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1e4) -/** TEE_DMA_TCM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * TCM MON read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_TCM_MON_R_PMS 0xFFFFFFFFU -#define TEE_DMA_TCM_MON_R_PMS_M (TEE_DMA_TCM_MON_R_PMS_V << TEE_DMA_TCM_MON_R_PMS_S) -#define TEE_DMA_TCM_MON_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_TCM_MON_R_PMS_S 0 - -/** TEE_DMA_TCM_MON_PMS_W_REG register - * TCM MON write permission control registers. - */ -#define TEE_DMA_TCM_MON_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1e8) -/** TEE_DMA_TCM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * TCM MON write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_TCM_MON_W_PMS 0xFFFFFFFFU -#define TEE_DMA_TCM_MON_W_PMS_M (TEE_DMA_TCM_MON_W_PMS_V << TEE_DMA_TCM_MON_W_PMS_S) -#define TEE_DMA_TCM_MON_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_TCM_MON_W_PMS_S 0 - -/** TEE_DMA_REGDMA_PMS_R_REG register - * REGDMA read permission control registers. - */ -#define TEE_DMA_REGDMA_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1ec) -/** TEE_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * REGDMA read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_REGDMA_R_PMS 0xFFFFFFFFU -#define TEE_DMA_REGDMA_R_PMS_M (TEE_DMA_REGDMA_R_PMS_V << TEE_DMA_REGDMA_R_PMS_S) -#define TEE_DMA_REGDMA_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_REGDMA_R_PMS_S 0 - -/** TEE_DMA_REGDMA_PMS_W_REG register - * REGDMA write permission control registers. - */ -#define TEE_DMA_REGDMA_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1f0) -/** TEE_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * REGDMA write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_REGDMA_W_PMS 0xFFFFFFFFU -#define TEE_DMA_REGDMA_W_PMS_M (TEE_DMA_REGDMA_W_PMS_V << TEE_DMA_REGDMA_W_PMS_S) -#define TEE_DMA_REGDMA_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_REGDMA_W_PMS_S 0 - -/** TEE_DMA_H264_PMS_R_REG register - * H264 read permission control registers. - */ -#define TEE_DMA_H264_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1fc) -/** TEE_DMA_H264_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * H264 read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_H264_R_PMS 0xFFFFFFFFU -#define TEE_DMA_H264_R_PMS_M (TEE_DMA_H264_R_PMS_V << TEE_DMA_H264_R_PMS_S) -#define TEE_DMA_H264_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_H264_R_PMS_S 0 - -/** TEE_DMA_H264_PMS_W_REG register - * H264 write permission control registers. - */ -#define TEE_DMA_H264_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x200) -/** TEE_DMA_H264_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * H264 write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_H264_W_PMS 0xFFFFFFFFU -#define TEE_DMA_H264_W_PMS_M (TEE_DMA_H264_W_PMS_V << TEE_DMA_H264_W_PMS_S) -#define TEE_DMA_H264_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_H264_W_PMS_S 0 - -/** TEE_DMA_DMA2D_PPA_PMS_R_REG register - * DMA2D PPA read permission control registers. - */ -#define TEE_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x204) -/** TEE_DMA_DMA2D_PPA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D PPA read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_DMA2D_PPA_R_PMS 0xFFFFFFFFU -#define TEE_DMA_DMA2D_PPA_R_PMS_M (TEE_DMA_DMA2D_PPA_R_PMS_V << TEE_DMA_DMA2D_PPA_R_PMS_S) -#define TEE_DMA_DMA2D_PPA_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_DMA2D_PPA_R_PMS_S 0 - -/** TEE_DMA_DMA2D_PPA_PMS_W_REG register - * DMA2D PPA write permission control registers. - */ -#define TEE_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x208) -/** TEE_DMA_DMA2D_PPA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D PPA write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_DMA2D_PPA_W_PMS 0xFFFFFFFFU -#define TEE_DMA_DMA2D_PPA_W_PMS_M (TEE_DMA_DMA2D_PPA_W_PMS_V << TEE_DMA_DMA2D_PPA_W_PMS_S) -#define TEE_DMA_DMA2D_PPA_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_DMA2D_PPA_W_PMS_S 0 - -/** TEE_DMA_DMA2D_DUMMY_PMS_R_REG register - * DMA2D dummy read permission control registers. - */ -#define TEE_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x20c) -/** TEE_DMA_DMA2D_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D dummy read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_DMA2D_DUMMY_R_PMS 0xFFFFFFFFU -#define TEE_DMA_DMA2D_DUMMY_R_PMS_M (TEE_DMA_DMA2D_DUMMY_R_PMS_V << TEE_DMA_DMA2D_DUMMY_R_PMS_S) -#define TEE_DMA_DMA2D_DUMMY_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_DMA2D_DUMMY_R_PMS_S 0 - -/** TEE_DMA_DMA2D_DUMMY_PMS_W_REG register - * DMA2D dummy write permission control registers. - */ -#define TEE_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x210) -/** TEE_DMA_DMA2D_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D dummy write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_DMA2D_DUMMY_W_PMS 0xFFFFFFFFU -#define TEE_DMA_DMA2D_DUMMY_W_PMS_M (TEE_DMA_DMA2D_DUMMY_W_PMS_V << TEE_DMA_DMA2D_DUMMY_W_PMS_S) -#define TEE_DMA_DMA2D_DUMMY_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_DMA2D_DUMMY_W_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_DUMMY_R_PMS_REG register - * AHB PDMA dummy read permission control registers. - */ -#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x214) -/** TEE_DMA_AHB_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA dummy read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_M (TEE_DMA_AHB_PDMA_DUMMY_R_PMS_V << TEE_DMA_AHB_PDMA_DUMMY_R_PMS_S) -#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_S 0 - -/** TEE_DMA_AHB_PDMA_DUMMY_W_PMS_REG register - * AHB PDMA dummy write permission control registers. - */ -#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x218) -/** TEE_DMA_AHB_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA dummy write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_M (TEE_DMA_AHB_PDMA_DUMMY_W_PMS_V << TEE_DMA_AHB_PDMA_DUMMY_W_PMS_S) -#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_DUMMY_R_PMS_REG register - * AXI PDMA dummy read permission control registers. - */ -#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x21c) -/** TEE_DMA_AXI_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA dummy read permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_M (TEE_DMA_AXI_PDMA_DUMMY_R_PMS_V << TEE_DMA_AXI_PDMA_DUMMY_R_PMS_S) -#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_S 0 - -/** TEE_DMA_AXI_PDMA_DUMMY_W_PMS_REG register - * AXI PDMA dummy write permission control registers. - */ -#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x220) -/** TEE_DMA_AXI_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA dummy write permission control, each bit corresponds to a region. - */ -#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_M (TEE_DMA_AXI_PDMA_DUMMY_W_PMS_V << TEE_DMA_AXI_PDMA_DUMMY_W_PMS_S) -#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_V 0xFFFFFFFFU -#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_reg.h index 622d01e65aa..82a6bac1fc5 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_reg.h @@ -1584,6 +1584,30 @@ extern "C" { #define PMS_DMA_SPM_MON_W_PMS_V 0xFFFFFFFFU #define PMS_DMA_SPM_MON_W_PMS_S 0 +/** PMS_DMA_REGDMA_PMS_R_REG register + * REGDMA read permission control registers. + */ +#define PMS_DMA_REGDMA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ec) +/** PMS_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; + * REGDMA read permission control, each bit corresponds to a region. + */ +#define PMS_DMA_REGDMA_R_PMS 0xFFFFFFFFU +#define PMS_DMA_REGDMA_R_PMS_M (PMS_DMA_REGDMA_R_PMS_V << PMS_DMA_REGDMA_R_PMS_S) +#define PMS_DMA_REGDMA_R_PMS_V 0xFFFFFFFFU +#define PMS_DMA_REGDMA_R_PMS_S 0 + +/** PMS_DMA_REGDMA_PMS_W_REG register + * REGDMA write permission control registers. + */ +#define PMS_DMA_REGDMA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1f0) +/** PMS_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; + * REGDMA write permission control, each bit corresponds to a region. + */ +#define PMS_DMA_REGDMA_W_PMS 0xFFFFFFFFU +#define PMS_DMA_REGDMA_W_PMS_M (PMS_DMA_REGDMA_W_PMS_V << PMS_DMA_REGDMA_W_PMS_S) +#define PMS_DMA_REGDMA_W_PMS_V 0xFFFFFFFFU +#define PMS_DMA_REGDMA_W_PMS_S 0 + /** PMS_DMA_H264_PMS_R_REG register * H264 DMA read permission control register */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_struct.h index c5c1bcc4e19..30a5140c8dd 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_struct.h @@ -10,1908 +10,1104 @@ extern "C" { #endif -/** Group: Tee version register. */ +/** Group: Version Control Registers */ /** Type of date register - * NA + * Version control register */ typedef union { struct { - /** tee_date : R/W; bitpos: [31:0]; default: 539165460; - * NA + /** date : R/W; bitpos: [31:0]; default: 539165460; + * Version control register. */ - uint32_t tee_date:32; + uint32_t date:32; }; uint32_t val; -} tee_dma_date_reg_t; +} pms_dma_date_reg_t; -/** Group: Tee regbank clock gating control register. */ +/** Group: Clock Gating Registers */ /** Type of clk_en register - * NA + * Clock gating register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * NA + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating. + * 1: Keep the clock always on. */ uint32_t clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} tee_dma_clk_en_reg_t; +} pms_dma_clk_en_reg_t; -/** Group: Tee region configuration registers. */ -/** Type of region0_low register - * Region0 address low register. +/** Group: Region Configuration Registers */ +/** Type of regionn_low register + * Regionn start address configuration register */ typedef union { struct { uint32_t reserved_0:12; - /** region0_low : R/W; bitpos: [31:12]; default: 0; - * Region0 address low. + /** regionn_low : R/W; bitpos: [31:12]; default: 0; + * Configures the high 20 bits of the start address for regionn. */ - uint32_t region0_low:20; + uint32_t regionn_low:20; }; uint32_t val; -} tee_dma_region0_low_reg_t; +} pms_dma_regionn_low_reg_t; -/** Type of region0_high register - * Region0 address high register. +/** Type of regionn_high register + * Regionn end address configuration register */ typedef union { struct { uint32_t reserved_0:12; - /** region0_high : R/W; bitpos: [31:12]; default: 1048575; - * Region0 address high. + /** regionn_high : R/W; bitpos: [31:12]; default: 1048575; + * Configures the high 20 bits of the end address for regionn. */ - uint32_t region0_high:20; + uint32_t regionn_high:20; }; uint32_t val; -} tee_dma_region0_high_reg_t; +} pms_dma_regionn_high_reg_t; -/** Type of region1_low register - * Region1 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region1_low : R/W; bitpos: [31:12]; default: 0; - * Region1 address low. - */ - uint32_t region1_low:20; - }; - uint32_t val; -} tee_dma_region1_low_reg_t; - -/** Type of region1_high register - * Region1 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region1_high : R/W; bitpos: [31:12]; default: 1048575; - * Region1 address high. - */ - uint32_t region1_high:20; - }; - uint32_t val; -} tee_dma_region1_high_reg_t; - -/** Type of region2_low register - * Region2 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region2_low : R/W; bitpos: [31:12]; default: 0; - * Region2 address low. - */ - uint32_t region2_low:20; - }; - uint32_t val; -} tee_dma_region2_low_reg_t; - -/** Type of region2_high register - * Region2 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region2_high : R/W; bitpos: [31:12]; default: 1048575; - * Region2 address high. - */ - uint32_t region2_high:20; - }; - uint32_t val; -} tee_dma_region2_high_reg_t; - -/** Type of region3_low register - * Region3 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region3_low : R/W; bitpos: [31:12]; default: 0; - * Region3 address low. - */ - uint32_t region3_low:20; - }; - uint32_t val; -} tee_dma_region3_low_reg_t; - -/** Type of region3_high register - * Region3 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region3_high : R/W; bitpos: [31:12]; default: 1048575; - * Region3 address high. - */ - uint32_t region3_high:20; - }; - uint32_t val; -} tee_dma_region3_high_reg_t; - -/** Type of region4_low register - * Region4 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region4_low : R/W; bitpos: [31:12]; default: 0; - * Region4 address low. - */ - uint32_t region4_low:20; - }; - uint32_t val; -} tee_dma_region4_low_reg_t; - -/** Type of region4_high register - * Region4 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region4_high : R/W; bitpos: [31:12]; default: 1048575; - * Region4 address high. - */ - uint32_t region4_high:20; - }; - uint32_t val; -} tee_dma_region4_high_reg_t; - -/** Type of region5_low register - * Region5 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region5_low : R/W; bitpos: [31:12]; default: 0; - * Region5 address low. - */ - uint32_t region5_low:20; - }; - uint32_t val; -} tee_dma_region5_low_reg_t; - -/** Type of region5_high register - * Region5 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region5_high : R/W; bitpos: [31:12]; default: 1048575; - * Region5 address high. - */ - uint32_t region5_high:20; - }; - uint32_t val; -} tee_dma_region5_high_reg_t; - -/** Type of region6_low register - * Region6 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region6_low : R/W; bitpos: [31:12]; default: 0; - * Region6 address low. - */ - uint32_t region6_low:20; - }; - uint32_t val; -} tee_dma_region6_low_reg_t; - -/** Type of region6_high register - * Region6 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region6_high : R/W; bitpos: [31:12]; default: 1048575; - * Region6 address high. - */ - uint32_t region6_high:20; - }; - uint32_t val; -} tee_dma_region6_high_reg_t; - -/** Type of region7_low register - * Region7 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region7_low : R/W; bitpos: [31:12]; default: 0; - * Region7 address low. - */ - uint32_t region7_low:20; - }; - uint32_t val; -} tee_dma_region7_low_reg_t; - -/** Type of region7_high register - * Region7 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region7_high : R/W; bitpos: [31:12]; default: 1048575; - * Region7 address high. - */ - uint32_t region7_high:20; - }; - uint32_t val; -} tee_dma_region7_high_reg_t; - -/** Type of region8_low register - * Region8 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region8_low : R/W; bitpos: [31:12]; default: 0; - * Region8 address low. - */ - uint32_t region8_low:20; - }; - uint32_t val; -} tee_dma_region8_low_reg_t; - -/** Type of region8_high register - * Region8 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region8_high : R/W; bitpos: [31:12]; default: 1048575; - * Region8 address high. - */ - uint32_t region8_high:20; - }; - uint32_t val; -} tee_dma_region8_high_reg_t; - -/** Type of region9_low register - * Region9 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region9_low : R/W; bitpos: [31:12]; default: 0; - * Region9 address low. - */ - uint32_t region9_low:20; - }; - uint32_t val; -} tee_dma_region9_low_reg_t; - -/** Type of region9_high register - * Region9 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region9_high : R/W; bitpos: [31:12]; default: 1048575; - * Region9 address high. - */ - uint32_t region9_high:20; - }; - uint32_t val; -} tee_dma_region9_high_reg_t; - -/** Type of region10_low register - * Region10 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region10_low : R/W; bitpos: [31:12]; default: 0; - * Region10 address low. - */ - uint32_t region10_low:20; - }; - uint32_t val; -} tee_dma_region10_low_reg_t; - -/** Type of region10_high register - * Region10 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region10_high : R/W; bitpos: [31:12]; default: 1048575; - * Region10 address high. - */ - uint32_t region10_high:20; - }; - uint32_t val; -} tee_dma_region10_high_reg_t; - -/** Type of region11_low register - * Region11 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region11_low : R/W; bitpos: [31:12]; default: 0; - * Region11 address low. - */ - uint32_t region11_low:20; - }; - uint32_t val; -} tee_dma_region11_low_reg_t; - -/** Type of region11_high register - * Region11 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region11_high : R/W; bitpos: [31:12]; default: 1048575; - * Region11 address high. - */ - uint32_t region11_high:20; - }; - uint32_t val; -} tee_dma_region11_high_reg_t; - -/** Type of region12_low register - * Region12 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region12_low : R/W; bitpos: [31:12]; default: 0; - * Region12 address low. - */ - uint32_t region12_low:20; - }; - uint32_t val; -} tee_dma_region12_low_reg_t; - -/** Type of region12_high register - * Region12 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region12_high : R/W; bitpos: [31:12]; default: 1048575; - * Region12 address high. - */ - uint32_t region12_high:20; - }; - uint32_t val; -} tee_dma_region12_high_reg_t; - -/** Type of region13_low register - * Region13 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region13_low : R/W; bitpos: [31:12]; default: 0; - * Region13 address low. - */ - uint32_t region13_low:20; - }; - uint32_t val; -} tee_dma_region13_low_reg_t; - -/** Type of region13_high register - * Region13 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region13_high : R/W; bitpos: [31:12]; default: 1048575; - * Region13 address high. - */ - uint32_t region13_high:20; - }; - uint32_t val; -} tee_dma_region13_high_reg_t; - -/** Type of region14_low register - * Region14 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region14_low : R/W; bitpos: [31:12]; default: 0; - * Region14 address low. - */ - uint32_t region14_low:20; - }; - uint32_t val; -} tee_dma_region14_low_reg_t; - -/** Type of region14_high register - * Region14 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region14_high : R/W; bitpos: [31:12]; default: 1048575; - * Region14 address high. - */ - uint32_t region14_high:20; - }; - uint32_t val; -} tee_dma_region14_high_reg_t; - -/** Type of region15_low register - * Region15 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region15_low : R/W; bitpos: [31:12]; default: 0; - * Region15 address low. - */ - uint32_t region15_low:20; - }; - uint32_t val; -} tee_dma_region15_low_reg_t; - -/** Type of region15_high register - * Region15 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region15_high : R/W; bitpos: [31:12]; default: 1048575; - * Region15 address high. - */ - uint32_t region15_high:20; - }; - uint32_t val; -} tee_dma_region15_high_reg_t; - -/** Type of region16_low register - * Region16 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region16_low : R/W; bitpos: [31:12]; default: 0; - * Region16 address low. - */ - uint32_t region16_low:20; - }; - uint32_t val; -} tee_dma_region16_low_reg_t; - -/** Type of region16_high register - * Region16 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region16_high : R/W; bitpos: [31:12]; default: 1048575; - * Region16 address high. - */ - uint32_t region16_high:20; - }; - uint32_t val; -} tee_dma_region16_high_reg_t; - -/** Type of region17_low register - * Region17 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region17_low : R/W; bitpos: [31:12]; default: 0; - * Region17 address low. - */ - uint32_t region17_low:20; - }; - uint32_t val; -} tee_dma_region17_low_reg_t; - -/** Type of region17_high register - * Region17 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region17_high : R/W; bitpos: [31:12]; default: 1048575; - * Region17 address high. - */ - uint32_t region17_high:20; - }; - uint32_t val; -} tee_dma_region17_high_reg_t; - -/** Type of region18_low register - * Region18 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region18_low : R/W; bitpos: [31:12]; default: 0; - * Region18 address low. - */ - uint32_t region18_low:20; - }; - uint32_t val; -} tee_dma_region18_low_reg_t; - -/** Type of region18_high register - * Region18 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region18_high : R/W; bitpos: [31:12]; default: 1048575; - * Region18 address high. - */ - uint32_t region18_high:20; - }; - uint32_t val; -} tee_dma_region18_high_reg_t; - -/** Type of region19_low register - * Region19 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region19_low : R/W; bitpos: [31:12]; default: 0; - * Region19 address low. - */ - uint32_t region19_low:20; - }; - uint32_t val; -} tee_dma_region19_low_reg_t; - -/** Type of region19_high register - * Region19 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region19_high : R/W; bitpos: [31:12]; default: 1048575; - * Region19 address high. - */ - uint32_t region19_high:20; - }; - uint32_t val; -} tee_dma_region19_high_reg_t; - -/** Type of region20_low register - * Region20 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region20_low : R/W; bitpos: [31:12]; default: 0; - * Region20 address low. - */ - uint32_t region20_low:20; - }; - uint32_t val; -} tee_dma_region20_low_reg_t; - -/** Type of region20_high register - * Region20 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region20_high : R/W; bitpos: [31:12]; default: 1048575; - * Region20 address high. - */ - uint32_t region20_high:20; - }; - uint32_t val; -} tee_dma_region20_high_reg_t; - -/** Type of region21_low register - * Region21 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region21_low : R/W; bitpos: [31:12]; default: 0; - * Region21 address low. - */ - uint32_t region21_low:20; - }; - uint32_t val; -} tee_dma_region21_low_reg_t; - -/** Type of region21_high register - * Region21 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region21_high : R/W; bitpos: [31:12]; default: 1048575; - * Region21 address high. - */ - uint32_t region21_high:20; - }; - uint32_t val; -} tee_dma_region21_high_reg_t; - -/** Type of region22_low register - * Region22 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region22_low : R/W; bitpos: [31:12]; default: 0; - * Region22 address low. - */ - uint32_t region22_low:20; - }; - uint32_t val; -} tee_dma_region22_low_reg_t; - -/** Type of region22_high register - * Region22 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region22_high : R/W; bitpos: [31:12]; default: 1048575; - * Region22 address high. - */ - uint32_t region22_high:20; - }; - uint32_t val; -} tee_dma_region22_high_reg_t; - -/** Type of region23_low register - * Region23 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region23_low : R/W; bitpos: [31:12]; default: 0; - * Region23 address low. - */ - uint32_t region23_low:20; - }; - uint32_t val; -} tee_dma_region23_low_reg_t; - -/** Type of region23_high register - * Region23 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region23_high : R/W; bitpos: [31:12]; default: 1048575; - * Region23 address high. - */ - uint32_t region23_high:20; - }; - uint32_t val; -} tee_dma_region23_high_reg_t; - -/** Type of region24_low register - * Region24 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region24_low : R/W; bitpos: [31:12]; default: 0; - * Region24 address low. - */ - uint32_t region24_low:20; - }; - uint32_t val; -} tee_dma_region24_low_reg_t; - -/** Type of region24_high register - * Region24 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region24_high : R/W; bitpos: [31:12]; default: 1048575; - * Region24 address high. - */ - uint32_t region24_high:20; - }; - uint32_t val; -} tee_dma_region24_high_reg_t; - -/** Type of region25_low register - * Region25 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region25_low : R/W; bitpos: [31:12]; default: 0; - * Region25 address low. - */ - uint32_t region25_low:20; - }; - uint32_t val; -} tee_dma_region25_low_reg_t; - -/** Type of region25_high register - * Region25 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region25_high : R/W; bitpos: [31:12]; default: 1048575; - * Region25 address high. - */ - uint32_t region25_high:20; - }; - uint32_t val; -} tee_dma_region25_high_reg_t; - -/** Type of region26_low register - * Region26 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region26_low : R/W; bitpos: [31:12]; default: 0; - * Region26 address low. - */ - uint32_t region26_low:20; - }; - uint32_t val; -} tee_dma_region26_low_reg_t; - -/** Type of region26_high register - * Region26 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region26_high : R/W; bitpos: [31:12]; default: 1048575; - * Region26 address high. - */ - uint32_t region26_high:20; - }; - uint32_t val; -} tee_dma_region26_high_reg_t; - -/** Type of region27_low register - * Region27 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region27_low : R/W; bitpos: [31:12]; default: 0; - * Region27 address low. - */ - uint32_t region27_low:20; - }; - uint32_t val; -} tee_dma_region27_low_reg_t; - -/** Type of region27_high register - * Region27 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region27_high : R/W; bitpos: [31:12]; default: 1048575; - * Region27 address high. - */ - uint32_t region27_high:20; - }; - uint32_t val; -} tee_dma_region27_high_reg_t; - -/** Type of region28_low register - * Region28 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region28_low : R/W; bitpos: [31:12]; default: 0; - * Region28 address low. - */ - uint32_t region28_low:20; - }; - uint32_t val; -} tee_dma_region28_low_reg_t; - -/** Type of region28_high register - * Region28 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region28_high : R/W; bitpos: [31:12]; default: 1048575; - * Region28 address high. - */ - uint32_t region28_high:20; - }; - uint32_t val; -} tee_dma_region28_high_reg_t; - -/** Type of region29_low register - * Region29 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region29_low : R/W; bitpos: [31:12]; default: 0; - * Region29 address low. - */ - uint32_t region29_low:20; - }; - uint32_t val; -} tee_dma_region29_low_reg_t; - -/** Type of region29_high register - * Region29 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region29_high : R/W; bitpos: [31:12]; default: 1048575; - * Region29 address high. - */ - uint32_t region29_high:20; - }; - uint32_t val; -} tee_dma_region29_high_reg_t; - -/** Type of region30_low register - * Region30 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region30_low : R/W; bitpos: [31:12]; default: 0; - * Region30 address low. - */ - uint32_t region30_low:20; - }; - uint32_t val; -} tee_dma_region30_low_reg_t; - -/** Type of region30_high register - * Region30 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region30_high : R/W; bitpos: [31:12]; default: 1048575; - * Region30 address high. - */ - uint32_t region30_high:20; - }; - uint32_t val; -} tee_dma_region30_high_reg_t; - -/** Type of region31_low register - * Region31 address low register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region31_low : R/W; bitpos: [31:12]; default: 0; - * Region31 address low. - */ - uint32_t region31_low:20; - }; - uint32_t val; -} tee_dma_region31_low_reg_t; - -/** Type of region31_high register - * Region31 address high register. - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** region31_high : R/W; bitpos: [31:12]; default: 1048575; - * Region31 address high. - */ - uint32_t region31_high:20; - }; - uint32_t val; -} tee_dma_region31_high_reg_t; - - -/** Group: Tee permission control registers. */ -/** Type of gmda_ch0_r_pms register - * GDMA ch0 read permission control registers. - */ -typedef union { - struct { - /** gdma_ch0_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch0 read permission control, each bit corresponds to a region. - */ - uint32_t gdma_ch0_r_pms:32; - }; - uint32_t val; -} tee_dma_gmda_ch0_r_pms_reg_t; - -/** Type of gmda_ch0_w_pms register - * GDMA ch0 write permission control registers. - */ -typedef union { - struct { - /** gdma_ch0_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch0 write permission control, each bit corresponds to a region. - */ - uint32_t gdma_ch0_w_pms:32; - }; - uint32_t val; -} tee_dma_gmda_ch0_w_pms_reg_t; - -/** Type of gmda_ch1_r_pms register - * GDMA ch1 read permission control registers. - */ -typedef union { - struct { - /** gdma_ch1_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch1 read permission control, each bit corresponds to a region. - */ - uint32_t gdma_ch1_r_pms:32; - }; - uint32_t val; -} tee_dma_gmda_ch1_r_pms_reg_t; - -/** Type of gmda_ch1_w_pms register - * GDMA ch1 write permission control registers. - */ -typedef union { - struct { - /** gdma_ch1_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch1 write permission control, each bit corresponds to a region. - */ - uint32_t gdma_ch1_w_pms:32; - }; - uint32_t val; -} tee_dma_gmda_ch1_w_pms_reg_t; - -/** Type of gmda_ch2_r_pms register - * GDMA ch2 read permission control registers. - */ -typedef union { - struct { - /** gdma_ch2_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch2 read permission control, each bit corresponds to a region. - */ - uint32_t gdma_ch2_r_pms:32; - }; - uint32_t val; -} tee_dma_gmda_ch2_r_pms_reg_t; - -/** Type of gmda_ch2_w_pms register - * GDMA ch2 write permission control registers. - */ -typedef union { - struct { - /** gdma_ch2_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch2 write permission control, each bit corresponds to a region. - */ - uint32_t gdma_ch2_w_pms:32; - }; - uint32_t val; -} tee_dma_gmda_ch2_w_pms_reg_t; -/** Type of gmda_ch3_r_pms register - * GDMA ch3 read permission control registers. +/** Group: DMA Masters Read and Write Permission Control Registers */ +/** Type of gdma_chn_r_pms register + * GDMA chn read permission control register */ typedef union { struct { - /** gdma_ch3_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch3 read permission control, each bit corresponds to a region. + /** gdma_chn_r_pms : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the permission for GDMA chn to read 32 address regions. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ - uint32_t gdma_ch3_r_pms:32; + uint32_t gdma_chn_r_pms:32; }; uint32_t val; -} tee_dma_gmda_ch3_r_pms_reg_t; +} pms_dma_gdma_chn_r_pms_reg_t; -/** Type of gmda_ch3_w_pms register - * GDMA ch3 write permission control registers. +/** Type of gdma_chn_w_pms register + * GDMA chn write permission control register */ typedef union { struct { - /** gdma_ch3_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GDMA ch3 write permission control, each bit corresponds to a region. + /** gdma_chn_w_pms : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the permission for GDMA chn to write 32 address regions. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ - uint32_t gdma_ch3_w_pms:32; + uint32_t gdma_chn_w_pms:32; }; uint32_t val; -} tee_dma_gmda_ch3_w_pms_reg_t; +} pms_dma_gdma_chn_w_pms_reg_t; /** Type of ahb_pdma_adc_r_pms register - * AHB PDMA adc read permission control registers. + * GDMA-AHB ADC read permission control register */ typedef union { struct { /** ahb_pdma_adc_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA adc read permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to read 32 address ranges requested by ADC. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t ahb_pdma_adc_r_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_adc_r_pms_reg_t; +} pms_dma_ahb_pdma_adc_r_pms_reg_t; /** Type of ahb_pdma_adc_w_pms register - * AHB PDMA adc write permission control registers. + * GDMA-AHB ADC write permission control register */ typedef union { struct { /** ahb_pdma_adc_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA adc write permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to write 32 address ranges requested by ADC. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t ahb_pdma_adc_w_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_adc_w_pms_reg_t; +} pms_dma_ahb_pdma_adc_w_pms_reg_t; /** Type of ahb_pdma_i2s0_r_pms register - * AHB PDMA i2s0 read permission control registers. + * GDMA-AHB I2S0 read permission control register */ typedef union { struct { /** ahb_pdma_i2s0_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s0 read permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to read 32 address ranges requested by I2S0. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t ahb_pdma_i2s0_r_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_i2s0_r_pms_reg_t; +} pms_dma_ahb_pdma_i2s0_r_pms_reg_t; /** Type of ahb_pdma_i2s0_w_pms register - * AHB PDMA i2s0 write permission control registers. + * GDMA-AHB I2S0 write permission control register */ typedef union { struct { /** ahb_pdma_i2s0_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s0 write permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to write 32 address ranges requested by I2S0. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t ahb_pdma_i2s0_w_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_i2s0_w_pms_reg_t; +} pms_dma_ahb_pdma_i2s0_w_pms_reg_t; /** Type of ahb_pdma_i2s1_r_pms register - * AHB PDMA i2s1 read permission control registers. + * GDMA-AHB I2S1 read permission control register */ typedef union { struct { /** ahb_pdma_i2s1_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s1 read permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to read 32 address ranges requested by I2S1. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t ahb_pdma_i2s1_r_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_i2s1_r_pms_reg_t; +} pms_dma_ahb_pdma_i2s1_r_pms_reg_t; /** Type of ahb_pdma_i2s1_w_pms register - * AHB PDMA i2s1 write permission control registers. + * GDMA-AHB I2S1 write permission control register */ typedef union { struct { /** ahb_pdma_i2s1_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s1 write permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to write 32 address ranges requested by I2S1. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t ahb_pdma_i2s1_w_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_i2s1_w_pms_reg_t; +} pms_dma_ahb_pdma_i2s1_w_pms_reg_t; /** Type of ahb_pdma_i2s2_r_pms register - * AHB PDMA i2s2 read permission control registers. + * GDMA-AHB I2S2 read permission control register */ typedef union { struct { /** ahb_pdma_i2s2_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s2 read permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to read 32 address ranges requested by I2S2. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t ahb_pdma_i2s2_r_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_i2s2_r_pms_reg_t; +} pms_dma_ahb_pdma_i2s2_r_pms_reg_t; /** Type of ahb_pdma_i2s2_w_pms register - * AHB PDMA i2s2 write permission control registers. + * GDMA-AHB I2S2 write permission control register */ typedef union { struct { /** ahb_pdma_i2s2_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i2s2 write permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to write 32 address ranges requested by I2S2. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t ahb_pdma_i2s2_w_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_i2s2_w_pms_reg_t; +} pms_dma_ahb_pdma_i2s2_w_pms_reg_t; /** Type of ahb_pdma_i3c_mst_r_pms register - * AHB PDMA i3s mst read permission control registers. + * GDMA-AHB I3C MST read permission control register */ typedef union { struct { /** ahb_pdma_i3c_mst_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i3c mst read permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to read 32 address ranges requested by I3C master. + * Bit 0 corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t ahb_pdma_i3c_mst_r_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_i3c_mst_r_pms_reg_t; +} pms_dma_ahb_pdma_i3c_mst_r_pms_reg_t; /** Type of ahb_pdma_i3c_mst_w_pms register - * AHB PDMA i3c mst write permission control registers. + * GDMA-AHB I3C MST write permission control register */ typedef union { struct { /** ahb_pdma_i3c_mst_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA i3c mst write permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to write 32 address ranges requested by I3C master. + * Bit 0 corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t ahb_pdma_i3c_mst_w_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_i3c_mst_w_pms_reg_t; +} pms_dma_ahb_pdma_i3c_mst_w_pms_reg_t; /** Type of ahb_pdma_uhci0_r_pms register - * AHB PDMA uhci0 read permission control registers. + * GDMA-AHB UHCI read permission control register */ typedef union { struct { /** ahb_pdma_uhci0_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA uhci0 read permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to read 32 address ranges requested by UHCI. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t ahb_pdma_uhci0_r_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_uhci0_r_pms_reg_t; +} pms_dma_ahb_pdma_uhci0_r_pms_reg_t; /** Type of ahb_pdma_uhci0_w_pms register - * AHB PDMA uhci0 write permission control registers. + * GDMA-AHB UHCI write permission control register */ typedef union { struct { /** ahb_pdma_uhci0_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA uhci0 write permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to write 32 address ranges requested by UHCI. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t ahb_pdma_uhci0_w_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_uhci0_w_pms_reg_t; +} pms_dma_ahb_pdma_uhci0_w_pms_reg_t; /** Type of ahb_pdma_rmt_r_pms register - * AHB PDMA rmt read permission control registers. + * GDMA-AHB RMT read permission control register */ typedef union { struct { /** ahb_pdma_rmt_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA rmt read permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to read 32 address ranges requested by RMT. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t ahb_pdma_rmt_r_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_rmt_r_pms_reg_t; +} pms_dma_ahb_pdma_rmt_r_pms_reg_t; /** Type of ahb_pdma_rmt_w_pms register - * AHB PDMA rmt write permission control registers. + * GDMA-AHB RMT write permission control register */ typedef union { struct { /** ahb_pdma_rmt_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA rmt write permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to write 32 address ranges requested by RMT. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t ahb_pdma_rmt_w_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_rmt_w_pms_reg_t; +} pms_dma_ahb_pdma_rmt_w_pms_reg_t; /** Type of axi_pdma_lcdcam_r_pms register - * AXI PDMA lcdcam read permission control registers. + * GDMA-AXI LCD_CAM read permission control register */ typedef union { struct { /** axi_pdma_lcdcam_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA lcdcam read permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to read 32 address ranges requested by LCD_CAM. Bit + * 0 corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t axi_pdma_lcdcam_r_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_lcdcam_r_pms_reg_t; +} pms_dma_axi_pdma_lcdcam_r_pms_reg_t; /** Type of axi_pdma_lcdcam_w_pms register - * AXI PDMA lcdcam write permission control registers. + * GDMA-AXI LCD_CAM write permission control register */ typedef union { struct { /** axi_pdma_lcdcam_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA lcdcam write permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to write 32 address ranges requested by LCD_CAM. Bit + * 0 corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t axi_pdma_lcdcam_w_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_lcdcam_w_pms_reg_t; +} pms_dma_axi_pdma_lcdcam_w_pms_reg_t; /** Type of axi_pdma_gpspi2_r_pms register - * AXI PDMA gpspi2 read permission control registers. + * GDMA-AXI GPSPI2 read permission control register */ typedef union { struct { /** axi_pdma_gpspi2_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA gpspi2 read permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI2. Bit + * 0 corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t axi_pdma_gpspi2_r_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_gpspi2_r_pms_reg_t; +} pms_dma_axi_pdma_gpspi2_r_pms_reg_t; /** Type of axi_pdma_gpspi2_w_pms register - * AXI PDMA gpspi2 write permission control registers. + * GDMA-AXI GPSPI2 write permission control register */ typedef union { struct { /** axi_pdma_gpspi2_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA gpspi2 write permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI2. Bit + * 0 corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t axi_pdma_gpspi2_w_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_gpspi2_w_pms_reg_t; +} pms_dma_axi_pdma_gpspi2_w_pms_reg_t; /** Type of axi_pdma_gpspi3_r_pms register - * AXI PDMA gpspi3 read permission control registers. + * GDMA-AXI GPSPI3 read permission control register */ typedef union { struct { /** axi_pdma_gpspi3_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA gpspi3 read permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI3. Bit + * 0 corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t axi_pdma_gpspi3_r_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_gpspi3_r_pms_reg_t; +} pms_dma_axi_pdma_gpspi3_r_pms_reg_t; /** Type of axi_pdma_gpspi3_w_pms register - * AXI PDMA gpspi3 write permission control registers. + * AXI PDMA GPSPI3 write permission control register */ typedef union { struct { /** axi_pdma_gpspi3_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA gpspi3 write permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI3. Bit + * 0 corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t axi_pdma_gpspi3_w_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_gpspi3_w_pms_reg_t; +} pms_dma_axi_pdma_gpspi3_w_pms_reg_t; /** Type of axi_pdma_parlio_r_pms register - * AXI PDMA parl io read permission control registers. + * GDMA-AXI PARLIO read permission control register */ typedef union { struct { /** axi_pdma_parlio_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA parl io read permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to read 32 address ranges requested by PARLIO + * (Parallel IO Controller). Bit 0 corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t axi_pdma_parlio_r_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_parlio_r_pms_reg_t; +} pms_dma_axi_pdma_parlio_r_pms_reg_t; /** Type of axi_pdma_parlio_w_pms register - * AXI PDMA parl io write permission control registers. + * GDMA-AXI PARLIO write permission control register */ typedef union { struct { /** axi_pdma_parlio_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA parl io write permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to write 32 address ranges requested by PARLIO. Bit + * 0 corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t axi_pdma_parlio_w_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_parlio_w_pms_reg_t; +} pms_dma_axi_pdma_parlio_w_pms_reg_t; /** Type of axi_pdma_aes_r_pms register - * AXI PDMA aes read permission control registers. + * GDMA-AXI AES read permission control register */ typedef union { struct { /** axi_pdma_aes_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA aes read permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to read 32 address ranges requested by AES. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t axi_pdma_aes_r_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_aes_r_pms_reg_t; +} pms_dma_axi_pdma_aes_r_pms_reg_t; /** Type of axi_pdma_aes_w_pms register - * AXI PDMA aes write permission control registers. + * GDMA-AXI AES write permission control register */ typedef union { struct { /** axi_pdma_aes_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA aes write permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to write 32 address ranges requested by AES. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t axi_pdma_aes_w_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_aes_w_pms_reg_t; +} pms_dma_axi_pdma_aes_w_pms_reg_t; /** Type of axi_pdma_sha_r_pms register - * AXI PDMA sha read permission control registers. + * GDMA-AXI SHA read permission control register */ typedef union { struct { /** axi_pdma_sha_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA sha read permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to read 32 address ranges requested by SHA. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t axi_pdma_sha_r_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_sha_r_pms_reg_t; +} pms_dma_axi_pdma_sha_r_pms_reg_t; /** Type of axi_pdma_sha_w_pms register - * AXI PDMA sha write permission control registers. + * GDMA-AXI SHA write permission control register */ typedef union { struct { /** axi_pdma_sha_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA sha write permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to write 32 address ranges requested by SHA. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t axi_pdma_sha_w_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_sha_w_pms_reg_t; +} pms_dma_axi_pdma_sha_w_pms_reg_t; /** Type of dma2d_jpeg_pms_r register - * DMA2D JPEG read permission control registers. + * 2D-DMA JPEG read permission control register */ typedef union { struct { /** dma2d_jpeg_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D JPEG read permission control, each bit corresponds to a region. + * Configures 2D-DMA permission to read 32 address ranges requested by JPEG. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t dma2d_jpeg_r_pms:32; }; uint32_t val; -} tee_dma_dma2d_jpeg_pms_r_reg_t; +} pms_dma_dma2d_jpeg_pms_r_reg_t; /** Type of dma2d_jpeg_pms_w register - * DMA2D JPEG write permission control registers. + * 2D-DMA JPEG write permission control register */ typedef union { struct { /** dma2d_jpeg_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D JPEG write permission control, each bit corresponds to a region. + * Configures 2D-DMA permission to write 32 address ranges requested by JPEG. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t dma2d_jpeg_w_pms:32; }; uint32_t val; -} tee_dma_dma2d_jpeg_pms_w_reg_t; +} pms_dma_dma2d_jpeg_pms_w_reg_t; /** Type of usb_pms_r register - * USB read permission control registers. + * High-speed USB 2.0 OTG read permission control register */ typedef union { struct { /** usb_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * USB read permission control, each bit corresponds to a region. + * Configures read permission for high-speed USB 2.0 OTG to access 32 address ranges. + * Bit 0 corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t usb_r_pms:32; }; uint32_t val; -} tee_dma_usb_pms_r_reg_t; +} pms_dma_usb_pms_r_reg_t; /** Type of usb_pms_w register - * USB write permission control registers. + * High-speed USB 2.0 OTG write permission control register */ typedef union { struct { /** usb_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * USB write permission control, each bit corresponds to a region. + * Configures write permission for high-speed USB 2.0 OTG to access 32 address ranges. + * Bit 0 corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t usb_w_pms:32; }; uint32_t val; -} tee_dma_usb_pms_w_reg_t; +} pms_dma_usb_pms_w_reg_t; /** Type of gmac_pms_r register - * GMAC read permission control registers. + * EMAC read permission control register */ typedef union { struct { /** gmac_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GMAC read permission control, each bit corresponds to a region. + * Configures read permission for EMAC to access 32 address ranges. Bit 0 corresponds + * to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t gmac_r_pms:32; }; uint32_t val; -} tee_dma_gmac_pms_r_reg_t; +} pms_dma_gmac_pms_r_reg_t; /** Type of gmac_pms_w register - * GMAC write permission control registers. + * EMAC write permission control register */ typedef union { struct { /** gmac_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * GMAC write permission control, each bit corresponds to a region. + * Configures write permission for EMAC to access 32 address ranges. Bit 0 corresponds + * to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t gmac_w_pms:32; }; uint32_t val; -} tee_dma_gmac_pms_w_reg_t; +} pms_dma_gmac_pms_w_reg_t; /** Type of sdmmc_pms_r register - * SDMMC read permission control registers. + * SDMMC read permission control register */ typedef union { struct { /** sdmmc_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * SDMMC read permission control, each bit corresponds to a region. + * Configures read permission for SDMMC to access 32 address ranges. Bit 0 corresponds + * to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t sdmmc_r_pms:32; }; uint32_t val; -} tee_dma_sdmmc_pms_r_reg_t; +} pms_dma_sdmmc_pms_r_reg_t; /** Type of sdmmc_pms_w register - * SDMMC write permission control registers. + * SDMMC write permission control register */ typedef union { struct { /** sdmmc_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * SDMMC write permission control, each bit corresponds to a region. + * Configures write permission for SDMMC to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t sdmmc_w_pms:32; }; uint32_t val; -} tee_dma_sdmmc_pms_w_reg_t; +} pms_dma_sdmmc_pms_w_reg_t; /** Type of usbotg11_pms_r register - * USBOTG11 read permission control registers. + * Full-speed USB 2.0 OTG full-speed read permission control register */ typedef union { struct { /** usbotg11_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * USBOTG11 read permission control, each bit corresponds to a region. + * Configures read permission for full-speed USB 2.0 OTG to access 32 address ranges. + * Bit 0 corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t usbotg11_r_pms:32; }; uint32_t val; -} tee_dma_usbotg11_pms_r_reg_t; +} pms_dma_usbotg11_pms_r_reg_t; /** Type of usbotg11_pms_w register - * USBOTG11 write permission control registers. + * Full-speed USB 2.0 OTG full-speed write permission control register */ typedef union { struct { /** usbotg11_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * USBOTG11 write permission control, each bit corresponds to a region. + * Configures write permission for full-speed USB 2.0 OTG to access 32 address ranges. + * Bit 0 corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t usbotg11_w_pms:32; }; uint32_t val; -} tee_dma_usbotg11_pms_w_reg_t; +} pms_dma_usbotg11_pms_w_reg_t; /** Type of trace0_pms_r register - * TRACE0 read permission control registers. + * TRACE0 read permission control register */ typedef union { struct { /** trace0_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * TRACE0 read permission control, each bit corresponds to a region. + * Configures read permission for TRACE0 to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t trace0_r_pms:32; }; uint32_t val; -} tee_dma_trace0_pms_r_reg_t; +} pms_dma_trace0_pms_r_reg_t; /** Type of trace0_pms_w register - * TRACE0 write permission control registers. + * TRACE0 write permission control register */ typedef union { struct { /** trace0_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * TRACE0 write permission control, each bit corresponds to a region. + * Configures write permission for TRACE0 to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t trace0_w_pms:32; }; uint32_t val; -} tee_dma_trace0_pms_w_reg_t; +} pms_dma_trace0_pms_w_reg_t; /** Type of trace1_pms_r register - * TRACE1 read permission control registers. + * TRACE1 read permission control register */ typedef union { struct { /** trace1_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * TRACE1 read permission control, each bit corresponds to a region. + * Configures read permission for TRACE1 to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t trace1_r_pms:32; }; uint32_t val; -} tee_dma_trace1_pms_r_reg_t; +} pms_dma_trace1_pms_r_reg_t; /** Type of trace1_pms_w register - * TRACE1 write permission control registers. + * TRACE1 write permission control register */ typedef union { struct { /** trace1_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * TRACE1 write permission control, each bit corresponds to a region. + * Configures write permission for TRACE1 to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t trace1_w_pms:32; }; uint32_t val; -} tee_dma_trace1_pms_w_reg_t; +} pms_dma_trace1_pms_w_reg_t; /** Type of l2mem_mon_pms_r register - * L2MEM MON read permission control registers. + * L2MEM Monitor read permission control register */ typedef union { struct { /** l2mem_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * L2MEM MON read permission control, each bit corresponds to a region. + * Configures read permission for L2MEM MON. Each bit corresponds to a region. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t l2mem_mon_r_pms:32; }; uint32_t val; -} tee_dma_l2mem_mon_pms_r_reg_t; +} pms_dma_l2mem_mon_pms_r_reg_t; /** Type of l2mem_mon_pms_w register - * L2MEM MON write permission control registers. + * L2MEM Monitor write permission control register */ typedef union { struct { /** l2mem_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * L2MEM MON write permission control, each bit corresponds to a region. + * Configures write permission for L2MEM monitor to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t l2mem_mon_w_pms:32; }; uint32_t val; -} tee_dma_l2mem_mon_pms_w_reg_t; +} pms_dma_l2mem_mon_pms_w_reg_t; -/** Type of tcm_mon_pms_r register - * TCM MON read permission control registers. +/** Type of spm_mon_pms_r register + * SPM Monitor read permission control register */ typedef union { struct { - /** tcm_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * TCM MON read permission control, each bit corresponds to a region. + /** spm_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295; + * Configures read permission for SPM MON. Each bit corresponds to a region. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ - uint32_t tcm_mon_r_pms:32; + uint32_t spm_mon_r_pms:32; }; uint32_t val; -} tee_dma_tcm_mon_pms_r_reg_t; +} pms_dma_spm_mon_pms_r_reg_t; -/** Type of tcm_mon_pms_w register - * TCM MON write permission control registers. +/** Type of spm_mon_pms_w register + * SPM Monitor write permission control register */ typedef union { struct { - /** tcm_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * TCM MON write permission control, each bit corresponds to a region. + /** spm_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295; + * Configures write permission for SPM monitor to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ - uint32_t tcm_mon_w_pms:32; + uint32_t spm_mon_w_pms:32; }; uint32_t val; -} tee_dma_tcm_mon_pms_w_reg_t; - -/** Type of regdma_pms_r register - * REGDMA read permission control registers. - */ -typedef union { - struct { - /** regdma_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * REGDMA read permission control, each bit corresponds to a region. - */ - uint32_t regdma_r_pms:32; - }; - uint32_t val; -} tee_dma_regdma_pms_r_reg_t; - -/** Type of regdma_pms_w register - * REGDMA write permission control registers. - */ -typedef union { - struct { - /** regdma_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * REGDMA write permission control, each bit corresponds to a region. - */ - uint32_t regdma_w_pms:32; - }; - uint32_t val; -} tee_dma_regdma_pms_w_reg_t; +} pms_dma_spm_mon_pms_w_reg_t; /** Type of h264_pms_r register - * H264 read permission control registers. + * H264 DMA read permission control register */ typedef union { struct { /** h264_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * H264 read permission control, each bit corresponds to a region. + * Configures read permission for H264 DMA to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t h264_r_pms:32; }; uint32_t val; -} tee_dma_h264_pms_r_reg_t; +} pms_dma_h264_pms_r_reg_t; /** Type of h264_pms_w register - * H264 write permission control registers. + * H264 DMA write permission control register */ typedef union { struct { /** h264_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * H264 write permission control, each bit corresponds to a region. + * Configures write permission for H264 DMA to access 32 address ranges. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t h264_w_pms:32; }; uint32_t val; -} tee_dma_h264_pms_w_reg_t; +} pms_dma_h264_pms_w_reg_t; /** Type of dma2d_ppa_pms_r register - * DMA2D PPA read permission control registers. + * 2D-DMA PPA read permission control register */ typedef union { struct { /** dma2d_ppa_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D PPA read permission control, each bit corresponds to a region. + * Configures 2D-DMA permission to read 32 address ranges requested by PPA + * (Pixel-Processing Accelerator). Bit 0 corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t dma2d_ppa_r_pms:32; }; uint32_t val; -} tee_dma_dma2d_ppa_pms_r_reg_t; +} pms_dma_dma2d_ppa_pms_r_reg_t; /** Type of dma2d_ppa_pms_w register - * DMA2D PPA write permission control registers. + * 2D-DMA PPA write permission control register */ typedef union { struct { /** dma2d_ppa_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D PPA write permission control, each bit corresponds to a region. + * Configures 2D-DMA permission to write 32 address ranges requested by PPA. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t dma2d_ppa_w_pms:32; }; uint32_t val; -} tee_dma_dma2d_ppa_pms_w_reg_t; +} pms_dma_dma2d_ppa_pms_w_reg_t; /** Type of dma2d_dummy_pms_r register - * DMA2D dummy read permission control registers. + * 2D-DMA dummy read permission control register */ typedef union { struct { /** dma2d_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D dummy read permission control, each bit corresponds to a region. + * Configures 2D-DMA permission to read 32 address ranges requested by Dummy. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t dma2d_dummy_r_pms:32; }; uint32_t val; -} tee_dma_dma2d_dummy_pms_r_reg_t; +} pms_dma_dma2d_dummy_pms_r_reg_t; /** Type of dma2d_dummy_pms_w register - * DMA2D dummy write permission control registers. + * 2D-DMA dummy write permission control register */ typedef union { struct { /** dma2d_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * DMA2D dummy write permission control, each bit corresponds to a region. + * Configures 2D-DMA permission to write 32 address ranges requested by Dummy. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t dma2d_dummy_w_pms:32; }; uint32_t val; -} tee_dma_dma2d_dummy_pms_w_reg_t; +} pms_dma_dma2d_dummy_pms_w_reg_t; /** Type of ahb_pdma_dummy_r_pms register - * AHB PDMA dummy read permission control registers. + * GDMA-AHB dummy read permission control register */ typedef union { struct { /** ahb_pdma_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA dummy read permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to read 32 address ranges requested by Dummy. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t ahb_pdma_dummy_r_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_dummy_r_pms_reg_t; +} pms_dma_ahb_pdma_dummy_r_pms_reg_t; /** Type of ahb_pdma_dummy_w_pms register - * AHB PDMA dummy write permission control registers. + * GDMA-AHB dummy write permission control register */ typedef union { struct { /** ahb_pdma_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AHB PDMA dummy write permission control, each bit corresponds to a region. + * Configures GDMA-AHB permission to write 32 address ranges requested by Dummy. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t ahb_pdma_dummy_w_pms:32; }; uint32_t val; -} tee_dma_ahb_pdma_dummy_w_pms_reg_t; +} pms_dma_ahb_pdma_dummy_w_pms_reg_t; /** Type of axi_pdma_dummy_r_pms register - * AXI PDMA dummy read permission control registers. + * GDMA-AXI dummy read permission control register */ typedef union { struct { /** axi_pdma_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA dummy read permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to read 32 address ranges requested by Dummy. Bit 0 + * corresponds to region0, and so on. + * 0: Disable read permission. + * 1: Enable read permission. */ uint32_t axi_pdma_dummy_r_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_dummy_r_pms_reg_t; +} pms_dma_axi_pdma_dummy_r_pms_reg_t; /** Type of axi_pdma_dummy_w_pms register - * AXI PDMA dummy write permission control registers. + * GDMA-AXI dummy write permission control register */ typedef union { struct { /** axi_pdma_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295; - * AXI PDMA dummy write permission control, each bit corresponds to a region. + * Configures GDMA-AXI permission to write 32 address ranges requested by Dummy. Bit 0 + * corresponds to region0, and so on. + * 0: Disable write permission. + * 1: Enable write permission. */ uint32_t axi_pdma_dummy_w_pms:32; }; uint32_t val; -} tee_dma_axi_pdma_dummy_w_pms_reg_t; +} pms_dma_axi_pdma_dummy_w_pms_reg_t; typedef struct { - volatile tee_dma_date_reg_t date; - volatile tee_dma_clk_en_reg_t clk_en; - volatile tee_dma_region0_low_reg_t region0_low; - volatile tee_dma_region0_high_reg_t region0_high; - volatile tee_dma_region1_low_reg_t region1_low; - volatile tee_dma_region1_high_reg_t region1_high; - volatile tee_dma_region2_low_reg_t region2_low; - volatile tee_dma_region2_high_reg_t region2_high; - volatile tee_dma_region3_low_reg_t region3_low; - volatile tee_dma_region3_high_reg_t region3_high; - volatile tee_dma_region4_low_reg_t region4_low; - volatile tee_dma_region4_high_reg_t region4_high; - volatile tee_dma_region5_low_reg_t region5_low; - volatile tee_dma_region5_high_reg_t region5_high; - volatile tee_dma_region6_low_reg_t region6_low; - volatile tee_dma_region6_high_reg_t region6_high; - volatile tee_dma_region7_low_reg_t region7_low; - volatile tee_dma_region7_high_reg_t region7_high; - volatile tee_dma_region8_low_reg_t region8_low; - volatile tee_dma_region8_high_reg_t region8_high; - volatile tee_dma_region9_low_reg_t region9_low; - volatile tee_dma_region9_high_reg_t region9_high; - volatile tee_dma_region10_low_reg_t region10_low; - volatile tee_dma_region10_high_reg_t region10_high; - volatile tee_dma_region11_low_reg_t region11_low; - volatile tee_dma_region11_high_reg_t region11_high; - volatile tee_dma_region12_low_reg_t region12_low; - volatile tee_dma_region12_high_reg_t region12_high; - volatile tee_dma_region13_low_reg_t region13_low; - volatile tee_dma_region13_high_reg_t region13_high; - volatile tee_dma_region14_low_reg_t region14_low; - volatile tee_dma_region14_high_reg_t region14_high; - volatile tee_dma_region15_low_reg_t region15_low; - volatile tee_dma_region15_high_reg_t region15_high; - volatile tee_dma_region16_low_reg_t region16_low; - volatile tee_dma_region16_high_reg_t region16_high; - volatile tee_dma_region17_low_reg_t region17_low; - volatile tee_dma_region17_high_reg_t region17_high; - volatile tee_dma_region18_low_reg_t region18_low; - volatile tee_dma_region18_high_reg_t region18_high; - volatile tee_dma_region19_low_reg_t region19_low; - volatile tee_dma_region19_high_reg_t region19_high; - volatile tee_dma_region20_low_reg_t region20_low; - volatile tee_dma_region20_high_reg_t region20_high; - volatile tee_dma_region21_low_reg_t region21_low; - volatile tee_dma_region21_high_reg_t region21_high; - volatile tee_dma_region22_low_reg_t region22_low; - volatile tee_dma_region22_high_reg_t region22_high; - volatile tee_dma_region23_low_reg_t region23_low; - volatile tee_dma_region23_high_reg_t region23_high; - volatile tee_dma_region24_low_reg_t region24_low; - volatile tee_dma_region24_high_reg_t region24_high; - volatile tee_dma_region25_low_reg_t region25_low; - volatile tee_dma_region25_high_reg_t region25_high; - volatile tee_dma_region26_low_reg_t region26_low; - volatile tee_dma_region26_high_reg_t region26_high; - volatile tee_dma_region27_low_reg_t region27_low; - volatile tee_dma_region27_high_reg_t region27_high; - volatile tee_dma_region28_low_reg_t region28_low; - volatile tee_dma_region28_high_reg_t region28_high; - volatile tee_dma_region29_low_reg_t region29_low; - volatile tee_dma_region29_high_reg_t region29_high; - volatile tee_dma_region30_low_reg_t region30_low; - volatile tee_dma_region30_high_reg_t region30_high; - volatile tee_dma_region31_low_reg_t region31_low; - volatile tee_dma_region31_high_reg_t region31_high; - volatile tee_dma_gmda_ch0_r_pms_reg_t gmda_ch0_r_pms; - volatile tee_dma_gmda_ch0_w_pms_reg_t gmda_ch0_w_pms; - volatile tee_dma_gmda_ch1_r_pms_reg_t gmda_ch1_r_pms; - volatile tee_dma_gmda_ch1_w_pms_reg_t gmda_ch1_w_pms; - volatile tee_dma_gmda_ch2_r_pms_reg_t gmda_ch2_r_pms; - volatile tee_dma_gmda_ch2_w_pms_reg_t gmda_ch2_w_pms; - volatile tee_dma_gmda_ch3_r_pms_reg_t gmda_ch3_r_pms; - volatile tee_dma_gmda_ch3_w_pms_reg_t gmda_ch3_w_pms; - volatile tee_dma_ahb_pdma_adc_r_pms_reg_t ahb_pdma_adc_r_pms; - volatile tee_dma_ahb_pdma_adc_w_pms_reg_t ahb_pdma_adc_w_pms; - volatile tee_dma_ahb_pdma_i2s0_r_pms_reg_t ahb_pdma_i2s0_r_pms; - volatile tee_dma_ahb_pdma_i2s0_w_pms_reg_t ahb_pdma_i2s0_w_pms; - volatile tee_dma_ahb_pdma_i2s1_r_pms_reg_t ahb_pdma_i2s1_r_pms; - volatile tee_dma_ahb_pdma_i2s1_w_pms_reg_t ahb_pdma_i2s1_w_pms; - volatile tee_dma_ahb_pdma_i2s2_r_pms_reg_t ahb_pdma_i2s2_r_pms; - volatile tee_dma_ahb_pdma_i2s2_w_pms_reg_t ahb_pdma_i2s2_w_pms; - volatile tee_dma_ahb_pdma_i3c_mst_r_pms_reg_t ahb_pdma_i3c_mst_r_pms; - volatile tee_dma_ahb_pdma_i3c_mst_w_pms_reg_t ahb_pdma_i3c_mst_w_pms; - volatile tee_dma_ahb_pdma_uhci0_r_pms_reg_t ahb_pdma_uhci0_r_pms; - volatile tee_dma_ahb_pdma_uhci0_w_pms_reg_t ahb_pdma_uhci0_w_pms; - volatile tee_dma_ahb_pdma_rmt_r_pms_reg_t ahb_pdma_rmt_r_pms; + volatile pms_dma_date_reg_t date; + volatile pms_dma_clk_en_reg_t clk_en; + volatile pms_dma_regionn_low_reg_t region0_low; + volatile pms_dma_regionn_high_reg_t region0_high; + volatile pms_dma_regionn_low_reg_t region1_low; + volatile pms_dma_regionn_high_reg_t region1_high; + volatile pms_dma_regionn_low_reg_t region2_low; + volatile pms_dma_regionn_high_reg_t region2_high; + volatile pms_dma_regionn_low_reg_t region3_low; + volatile pms_dma_regionn_high_reg_t region3_high; + volatile pms_dma_regionn_low_reg_t region4_low; + volatile pms_dma_regionn_high_reg_t region4_high; + volatile pms_dma_regionn_low_reg_t region5_low; + volatile pms_dma_regionn_high_reg_t region5_high; + volatile pms_dma_regionn_low_reg_t region6_low; + volatile pms_dma_regionn_high_reg_t region6_high; + volatile pms_dma_regionn_low_reg_t region7_low; + volatile pms_dma_regionn_high_reg_t region7_high; + volatile pms_dma_regionn_low_reg_t region8_low; + volatile pms_dma_regionn_high_reg_t region8_high; + volatile pms_dma_regionn_low_reg_t region9_low; + volatile pms_dma_regionn_high_reg_t region9_high; + volatile pms_dma_regionn_low_reg_t region10_low; + volatile pms_dma_regionn_high_reg_t region10_high; + volatile pms_dma_regionn_low_reg_t region11_low; + volatile pms_dma_regionn_high_reg_t region11_high; + volatile pms_dma_regionn_low_reg_t region12_low; + volatile pms_dma_regionn_high_reg_t region12_high; + volatile pms_dma_regionn_low_reg_t region13_low; + volatile pms_dma_regionn_high_reg_t region13_high; + volatile pms_dma_regionn_low_reg_t region14_low; + volatile pms_dma_regionn_high_reg_t region14_high; + volatile pms_dma_regionn_low_reg_t region15_low; + volatile pms_dma_regionn_high_reg_t region15_high; + volatile pms_dma_regionn_low_reg_t region16_low; + volatile pms_dma_regionn_high_reg_t region16_high; + volatile pms_dma_regionn_low_reg_t region17_low; + volatile pms_dma_regionn_high_reg_t region17_high; + volatile pms_dma_regionn_low_reg_t region18_low; + volatile pms_dma_regionn_high_reg_t region18_high; + volatile pms_dma_regionn_low_reg_t region19_low; + volatile pms_dma_regionn_high_reg_t region19_high; + volatile pms_dma_regionn_low_reg_t region20_low; + volatile pms_dma_regionn_high_reg_t region20_high; + volatile pms_dma_regionn_low_reg_t region21_low; + volatile pms_dma_regionn_high_reg_t region21_high; + volatile pms_dma_regionn_low_reg_t region22_low; + volatile pms_dma_regionn_high_reg_t region22_high; + volatile pms_dma_regionn_low_reg_t region23_low; + volatile pms_dma_regionn_high_reg_t region23_high; + volatile pms_dma_regionn_low_reg_t region24_low; + volatile pms_dma_regionn_high_reg_t region24_high; + volatile pms_dma_regionn_low_reg_t region25_low; + volatile pms_dma_regionn_high_reg_t region25_high; + volatile pms_dma_regionn_low_reg_t region26_low; + volatile pms_dma_regionn_high_reg_t region26_high; + volatile pms_dma_regionn_low_reg_t region27_low; + volatile pms_dma_regionn_high_reg_t region27_high; + volatile pms_dma_regionn_low_reg_t region28_low; + volatile pms_dma_regionn_high_reg_t region28_high; + volatile pms_dma_regionn_low_reg_t region29_low; + volatile pms_dma_regionn_high_reg_t region29_high; + volatile pms_dma_regionn_low_reg_t region30_low; + volatile pms_dma_regionn_high_reg_t region30_high; + volatile pms_dma_regionn_low_reg_t region31_low; + volatile pms_dma_regionn_high_reg_t region31_high; + volatile pms_dma_gdma_chn_r_pms_reg_t gdma_ch0_r_pms; + volatile pms_dma_gdma_chn_w_pms_reg_t gdma_ch0_w_pms; + volatile pms_dma_gdma_chn_r_pms_reg_t gdma_ch1_r_pms; + volatile pms_dma_gdma_chn_w_pms_reg_t gdma_ch1_w_pms; + volatile pms_dma_gdma_chn_r_pms_reg_t gdma_ch2_r_pms; + volatile pms_dma_gdma_chn_w_pms_reg_t gdma_ch2_w_pms; + volatile pms_dma_gdma_chn_r_pms_reg_t gdma_ch3_r_pms; + volatile pms_dma_gdma_chn_w_pms_reg_t gdma_ch3_w_pms; + volatile pms_dma_ahb_pdma_adc_r_pms_reg_t ahb_pdma_adc_r_pms; + volatile pms_dma_ahb_pdma_adc_w_pms_reg_t ahb_pdma_adc_w_pms; + volatile pms_dma_ahb_pdma_i2s0_r_pms_reg_t ahb_pdma_i2s0_r_pms; + volatile pms_dma_ahb_pdma_i2s0_w_pms_reg_t ahb_pdma_i2s0_w_pms; + volatile pms_dma_ahb_pdma_i2s1_r_pms_reg_t ahb_pdma_i2s1_r_pms; + volatile pms_dma_ahb_pdma_i2s1_w_pms_reg_t ahb_pdma_i2s1_w_pms; + volatile pms_dma_ahb_pdma_i2s2_r_pms_reg_t ahb_pdma_i2s2_r_pms; + volatile pms_dma_ahb_pdma_i2s2_w_pms_reg_t ahb_pdma_i2s2_w_pms; + volatile pms_dma_ahb_pdma_i3c_mst_r_pms_reg_t ahb_pdma_i3c_mst_r_pms; + volatile pms_dma_ahb_pdma_i3c_mst_w_pms_reg_t ahb_pdma_i3c_mst_w_pms; + volatile pms_dma_ahb_pdma_uhci0_r_pms_reg_t ahb_pdma_uhci0_r_pms; + volatile pms_dma_ahb_pdma_uhci0_w_pms_reg_t ahb_pdma_uhci0_w_pms; + volatile pms_dma_ahb_pdma_rmt_r_pms_reg_t ahb_pdma_rmt_r_pms; uint32_t reserved_15c[5]; - volatile tee_dma_ahb_pdma_rmt_w_pms_reg_t ahb_pdma_rmt_w_pms; - volatile tee_dma_axi_pdma_lcdcam_r_pms_reg_t axi_pdma_lcdcam_r_pms; - volatile tee_dma_axi_pdma_lcdcam_w_pms_reg_t axi_pdma_lcdcam_w_pms; - volatile tee_dma_axi_pdma_gpspi2_r_pms_reg_t axi_pdma_gpspi2_r_pms; - volatile tee_dma_axi_pdma_gpspi2_w_pms_reg_t axi_pdma_gpspi2_w_pms; - volatile tee_dma_axi_pdma_gpspi3_r_pms_reg_t axi_pdma_gpspi3_r_pms; - volatile tee_dma_axi_pdma_gpspi3_w_pms_reg_t axi_pdma_gpspi3_w_pms; - volatile tee_dma_axi_pdma_parlio_r_pms_reg_t axi_pdma_parlio_r_pms; - volatile tee_dma_axi_pdma_parlio_w_pms_reg_t axi_pdma_parlio_w_pms; - volatile tee_dma_axi_pdma_aes_r_pms_reg_t axi_pdma_aes_r_pms; - volatile tee_dma_axi_pdma_aes_w_pms_reg_t axi_pdma_aes_w_pms; - volatile tee_dma_axi_pdma_sha_r_pms_reg_t axi_pdma_sha_r_pms; - volatile tee_dma_axi_pdma_sha_w_pms_reg_t axi_pdma_sha_w_pms; - volatile tee_dma_dma2d_jpeg_pms_r_reg_t dma2d_jpeg_pms_r; - volatile tee_dma_dma2d_jpeg_pms_w_reg_t dma2d_jpeg_pms_w; - volatile tee_dma_usb_pms_r_reg_t usb_pms_r; - volatile tee_dma_usb_pms_w_reg_t usb_pms_w; - volatile tee_dma_gmac_pms_r_reg_t gmac_pms_r; - volatile tee_dma_gmac_pms_w_reg_t gmac_pms_w; - volatile tee_dma_sdmmc_pms_r_reg_t sdmmc_pms_r; - volatile tee_dma_sdmmc_pms_w_reg_t sdmmc_pms_w; - volatile tee_dma_usbotg11_pms_r_reg_t usbotg11_pms_r; - volatile tee_dma_usbotg11_pms_w_reg_t usbotg11_pms_w; - volatile tee_dma_trace0_pms_r_reg_t trace0_pms_r; - volatile tee_dma_trace0_pms_w_reg_t trace0_pms_w; - volatile tee_dma_trace1_pms_r_reg_t trace1_pms_r; - volatile tee_dma_trace1_pms_w_reg_t trace1_pms_w; - volatile tee_dma_l2mem_mon_pms_r_reg_t l2mem_mon_pms_r; - volatile tee_dma_l2mem_mon_pms_w_reg_t l2mem_mon_pms_w; - volatile tee_dma_tcm_mon_pms_r_reg_t tcm_mon_pms_r; - volatile tee_dma_tcm_mon_pms_w_reg_t tcm_mon_pms_w; - volatile tee_dma_regdma_pms_r_reg_t regdma_pms_r; - volatile tee_dma_regdma_pms_w_reg_t regdma_pms_w; - uint32_t reserved_1f4[2]; - volatile tee_dma_h264_pms_r_reg_t h264_pms_r; - volatile tee_dma_h264_pms_w_reg_t h264_pms_w; - volatile tee_dma_dma2d_ppa_pms_r_reg_t dma2d_ppa_pms_r; - volatile tee_dma_dma2d_ppa_pms_w_reg_t dma2d_ppa_pms_w; - volatile tee_dma_dma2d_dummy_pms_r_reg_t dma2d_dummy_pms_r; - volatile tee_dma_dma2d_dummy_pms_w_reg_t dma2d_dummy_pms_w; - volatile tee_dma_ahb_pdma_dummy_r_pms_reg_t ahb_pdma_dummy_r_pms; - volatile tee_dma_ahb_pdma_dummy_w_pms_reg_t ahb_pdma_dummy_w_pms; - volatile tee_dma_axi_pdma_dummy_r_pms_reg_t axi_pdma_dummy_r_pms; - volatile tee_dma_axi_pdma_dummy_w_pms_reg_t axi_pdma_dummy_w_pms; -} tee_dma_dev_t; + volatile pms_dma_ahb_pdma_rmt_w_pms_reg_t ahb_pdma_rmt_w_pms; + volatile pms_dma_axi_pdma_lcdcam_r_pms_reg_t axi_pdma_lcdcam_r_pms; + volatile pms_dma_axi_pdma_lcdcam_w_pms_reg_t axi_pdma_lcdcam_w_pms; + volatile pms_dma_axi_pdma_gpspi2_r_pms_reg_t axi_pdma_gpspi2_r_pms; + volatile pms_dma_axi_pdma_gpspi2_w_pms_reg_t axi_pdma_gpspi2_w_pms; + volatile pms_dma_axi_pdma_gpspi3_r_pms_reg_t axi_pdma_gpspi3_r_pms; + volatile pms_dma_axi_pdma_gpspi3_w_pms_reg_t axi_pdma_gpspi3_w_pms; + volatile pms_dma_axi_pdma_parlio_r_pms_reg_t axi_pdma_parlio_r_pms; + volatile pms_dma_axi_pdma_parlio_w_pms_reg_t axi_pdma_parlio_w_pms; + volatile pms_dma_axi_pdma_aes_r_pms_reg_t axi_pdma_aes_r_pms; + volatile pms_dma_axi_pdma_aes_w_pms_reg_t axi_pdma_aes_w_pms; + volatile pms_dma_axi_pdma_sha_r_pms_reg_t axi_pdma_sha_r_pms; + volatile pms_dma_axi_pdma_sha_w_pms_reg_t axi_pdma_sha_w_pms; + volatile pms_dma_dma2d_jpeg_pms_r_reg_t dma2d_jpeg_pms_r; + volatile pms_dma_dma2d_jpeg_pms_w_reg_t dma2d_jpeg_pms_w; + volatile pms_dma_usb_pms_r_reg_t usb_pms_r; + volatile pms_dma_usb_pms_w_reg_t usb_pms_w; + volatile pms_dma_gmac_pms_r_reg_t gmac_pms_r; + volatile pms_dma_gmac_pms_w_reg_t gmac_pms_w; + volatile pms_dma_sdmmc_pms_r_reg_t sdmmc_pms_r; + volatile pms_dma_sdmmc_pms_w_reg_t sdmmc_pms_w; + volatile pms_dma_usbotg11_pms_r_reg_t usbotg11_pms_r; + volatile pms_dma_usbotg11_pms_w_reg_t usbotg11_pms_w; + volatile pms_dma_trace0_pms_r_reg_t trace0_pms_r; + volatile pms_dma_trace0_pms_w_reg_t trace0_pms_w; + volatile pms_dma_trace1_pms_r_reg_t trace1_pms_r; + volatile pms_dma_trace1_pms_w_reg_t trace1_pms_w; + volatile pms_dma_l2mem_mon_pms_r_reg_t l2mem_mon_pms_r; + volatile pms_dma_l2mem_mon_pms_w_reg_t l2mem_mon_pms_w; + volatile pms_dma_spm_mon_pms_r_reg_t spm_mon_pms_r; + volatile pms_dma_spm_mon_pms_w_reg_t spm_mon_pms_w; + uint32_t reserved_1ec[4]; + volatile pms_dma_h264_pms_r_reg_t h264_pms_r; + volatile pms_dma_h264_pms_w_reg_t h264_pms_w; + volatile pms_dma_dma2d_ppa_pms_r_reg_t dma2d_ppa_pms_r; + volatile pms_dma_dma2d_ppa_pms_w_reg_t dma2d_ppa_pms_w; + volatile pms_dma_dma2d_dummy_pms_r_reg_t dma2d_dummy_pms_r; + volatile pms_dma_dma2d_dummy_pms_w_reg_t dma2d_dummy_pms_w; + volatile pms_dma_ahb_pdma_dummy_r_pms_reg_t ahb_pdma_dummy_r_pms; + volatile pms_dma_ahb_pdma_dummy_w_pms_reg_t ahb_pdma_dummy_w_pms; + volatile pms_dma_axi_pdma_dummy_r_pms_reg_t axi_pdma_dummy_r_pms; + volatile pms_dma_axi_pdma_dummy_w_pms_reg_t axi_pdma_dummy_w_pms; +} pms_dma_dev_t; -extern tee_dma_dev_t DMA_PMS; +extern pms_dma_dev_t DMA_PMS; #ifndef __cplusplus -_Static_assert(sizeof(tee_dma_dev_t) == 0x224, "Invalid size of tee_dma_dev_t structure"); +_Static_assert(sizeof(pms_dma_dev_t) == 0x224, "Invalid size of pms_dma_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h deleted file mode 100644 index 97e940133b3..00000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h +++ /dev/null @@ -1,778 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 OR MIT - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** TEE_HP2LP_TEE_PMS_DATE_REG register - * NA - */ -#define TEE_HP2LP_TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0) -/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943; - * NA - */ -#define TEE_TEE_DATE 0xFFFFFFFFU -#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S) -#define TEE_TEE_DATE_V 0xFFFFFFFFU -#define TEE_TEE_DATE_S 0 - -/** TEE_PMS_CLK_EN_REG register - * NA - */ -#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4) -/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CLK_EN (BIT(0)) -#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S) -#define TEE_REG_CLK_EN_V 0x00000001U -#define TEE_REG_CLK_EN_S 0 - -/** TEE_HP_CORE0_MM_PMS_REG0_REG register - * NA - */ -#define TEE_HP_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8) -/** TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW (BIT(0)) -#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S 0 -/** TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW (BIT(1)) -#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S 1 -/** TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW (BIT(2)) -#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S 2 -/** TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW (BIT(3)) -#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S 3 -/** TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW (BIT(4)) -#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S 4 -/** TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW (BIT(5)) -#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S 5 -/** TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW (BIT(6)) -#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S 6 -/** TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW (BIT(7)) -#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S 7 -/** TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW (BIT(8)) -#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S 8 -/** TEE_REG_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW (BIT(9)) -#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S 9 -/** TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW (BIT(10)) -#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S 10 -/** TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW (BIT(11)) -#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S 11 -/** TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW (BIT(12)) -#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S 12 -/** TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW (BIT(13)) -#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S 13 -/** TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW (BIT(14)) -#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S 14 -/** TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW (BIT(15)) -#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S 15 -/** TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW (BIT(16)) -#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S 16 -/** TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW (BIT(17)) -#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S 17 -/** TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW (BIT(18)) -#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S 18 -/** TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW (BIT(19)) -#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S 19 -/** TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW (BIT(20)) -#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S 20 -/** TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW (BIT(21)) -#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S 21 -/** TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW (BIT(22)) -#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S 22 -/** TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW (BIT(23)) -#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S 23 -/** TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW (BIT(24)) -#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S) -#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S 24 - -/** TEE_HP_CORE0_UM_PMS_REG0_REG register - * NA - */ -#define TEE_HP_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0xc) -/** TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW (BIT(0)) -#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S 0 -/** TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW (BIT(1)) -#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S 1 -/** TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW (BIT(2)) -#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S 2 -/** TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW (BIT(3)) -#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S 3 -/** TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW (BIT(4)) -#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S 4 -/** TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW (BIT(5)) -#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S 5 -/** TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW (BIT(6)) -#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S 6 -/** TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW (BIT(7)) -#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S 7 -/** TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW (BIT(8)) -#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S 8 -/** TEE_REG_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW (BIT(9)) -#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S 9 -/** TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW (BIT(10)) -#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S 10 -/** TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW (BIT(11)) -#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S 11 -/** TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW (BIT(12)) -#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S 12 -/** TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW (BIT(13)) -#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S 13 -/** TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW (BIT(14)) -#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S 14 -/** TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW (BIT(15)) -#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S 15 -/** TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW (BIT(16)) -#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S 16 -/** TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW (BIT(17)) -#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S 17 -/** TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW (BIT(18)) -#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S 18 -/** TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW (BIT(19)) -#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S 19 -/** TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW (BIT(20)) -#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S 20 -/** TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW (BIT(21)) -#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S 21 -/** TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW (BIT(22)) -#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S 22 -/** TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW (BIT(23)) -#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S 23 -/** TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW (BIT(24)) -#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S) -#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S 24 - -/** TEE_HP_CORE1_MM_PMS_REG0_REG register - * NA - */ -#define TEE_HP_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x10) -/** TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW (BIT(0)) -#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S 0 -/** TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW (BIT(1)) -#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S 1 -/** TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW (BIT(2)) -#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S 2 -/** TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW (BIT(3)) -#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S 3 -/** TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW (BIT(4)) -#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S 4 -/** TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW (BIT(5)) -#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S 5 -/** TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW (BIT(6)) -#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S 6 -/** TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW (BIT(7)) -#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S 7 -/** TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW (BIT(8)) -#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S 8 -/** TEE_REG_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW (BIT(9)) -#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S 9 -/** TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW (BIT(10)) -#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S 10 -/** TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW (BIT(11)) -#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S 11 -/** TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW (BIT(12)) -#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S 12 -/** TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW (BIT(13)) -#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S 13 -/** TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW (BIT(14)) -#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S 14 -/** TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW (BIT(15)) -#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S 15 -/** TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW (BIT(16)) -#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S 16 -/** TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW (BIT(17)) -#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S 17 -/** TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW (BIT(18)) -#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S 18 -/** TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW (BIT(19)) -#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S 19 -/** TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW (BIT(20)) -#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S 20 -/** TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW (BIT(21)) -#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S 21 -/** TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW (BIT(22)) -#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S 22 -/** TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW (BIT(23)) -#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S 23 -/** TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW (BIT(24)) -#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S) -#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S 24 - -/** TEE_HP_CORE1_UM_PMS_REG0_REG register - * NA - */ -#define TEE_HP_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x14) -/** TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW (BIT(0)) -#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S 0 -/** TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW (BIT(1)) -#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S 1 -/** TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW (BIT(2)) -#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S 2 -/** TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW (BIT(3)) -#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S 3 -/** TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW (BIT(4)) -#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S 4 -/** TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW (BIT(5)) -#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S 5 -/** TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW (BIT(6)) -#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S 6 -/** TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW (BIT(7)) -#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S 7 -/** TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW (BIT(8)) -#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S 8 -/** TEE_REG_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW (BIT(9)) -#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S 9 -/** TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW (BIT(10)) -#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S 10 -/** TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW (BIT(11)) -#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S 11 -/** TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW (BIT(12)) -#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S 12 -/** TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW (BIT(13)) -#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S 13 -/** TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW (BIT(14)) -#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S 14 -/** TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW (BIT(15)) -#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S 15 -/** TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW (BIT(16)) -#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S 16 -/** TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW (BIT(17)) -#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S 17 -/** TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW (BIT(18)) -#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S 18 -/** TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW (BIT(19)) -#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S 19 -/** TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW (BIT(20)) -#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S 20 -/** TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW (BIT(21)) -#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S 21 -/** TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW (BIT(22)) -#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S 22 -/** TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW (BIT(23)) -#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S 23 -/** TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW (BIT(24)) -#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S) -#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V 0x00000001U -#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S 24 - -/** TEE_REGDMA_PERI_PMS_REG register - * NA - */ -#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x18) -/** TEE_REG_REGDMA_PERI_LP_RAM_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW (BIT(0)) -#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_M (TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V << TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S) -#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V 0x00000001U -#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S 0 -/** TEE_REG_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW (BIT(1)) -#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_M (TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S) -#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V 0x00000001U -#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S 1 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_reg.h index 2a4a079a1bc..80c866a33db 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { * Version control register */ #define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x0) -/** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790; +/** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2363943; * Version control register */ #define PMS_HP2LP_PERI_PMS_DATE 0xFFFFFFFFU @@ -262,6 +262,14 @@ extern "C" { #define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_M (PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S) #define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V 0x00000001U #define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S 23 +/** PMS_HP_CORE0_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPU0 in machine mode has permission to access RNG. + * 0: Not allowed + * 1: Allowed */ +#define PMS_HP_CORE0_MM_LP_TRNG_ALLOW (BIT(24)) +#define PMS_HP_CORE0_MM_LP_TRNG_ALLOW_M (PMS_HP_CORE0_MM_LP_TRNG_ALLOW_V << PMS_HP_CORE0_MM_LP_TRNG_ALLOW_S) +#define PMS_HP_CORE0_MM_LP_TRNG_ALLOW_V 0x00000001U +#define PMS_HP_CORE0_MM_LP_TRNG_ALLOW_S 24 /** PMS_HP_CORE0_UM_PMS_REG0_REG register * Permission control register0 for HP CPU0 in user mode @@ -487,6 +495,15 @@ extern "C" { #define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_M (PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S) #define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V 0x00000001U #define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S 23 +/** PMS_HP_CORE0_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPU0 in user mode has permission to access RNG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_HP_CORE0_UM_LP_TRNG_ALLOW (BIT(24)) +#define PMS_HP_CORE0_UM_LP_TRNG_ALLOW_M (PMS_HP_CORE0_UM_LP_TRNG_ALLOW_V << PMS_HP_CORE0_UM_LP_TRNG_ALLOW_S) +#define PMS_HP_CORE0_UM_LP_TRNG_ALLOW_V 0x00000001U +#define PMS_HP_CORE0_UM_LP_TRNG_ALLOW_S 24 /** PMS_HP_CORE1_MM_PMS_REG0_REG register * Permission control register0 for HP CPU1 in machine mode @@ -714,6 +731,15 @@ extern "C" { #define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_M (PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S) #define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V 0x00000001U #define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S 23 +/** PMS_HP_CORE1_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPU1 in machine mode has permission to access RNG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_HP_CORE1_MM_LP_TRNG_ALLOW (BIT(24)) +#define PMS_HP_CORE1_MM_LP_TRNG_ALLOW_M (PMS_HP_CORE1_MM_LP_TRNG_ALLOW_V << PMS_HP_CORE1_MM_LP_TRNG_ALLOW_S) +#define PMS_HP_CORE1_MM_LP_TRNG_ALLOW_V 0x00000001U +#define PMS_HP_CORE1_MM_LP_TRNG_ALLOW_S 24 /** PMS_HP_CORE1_UM_PMS_REG0_REG register * Permission control register0 for HP CPU1 in user mode @@ -939,6 +965,15 @@ extern "C" { #define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_M (PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S) #define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V 0x00000001U #define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S 23 +/** PMS_HP_CORE1_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPU1 in user mode has permission to access RNG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_HP_CORE1_UM_LP_TRNG_ALLOW (BIT(24)) +#define PMS_HP_CORE1_UM_LP_TRNG_ALLOW_M (PMS_HP_CORE1_UM_LP_TRNG_ALLOW_V << PMS_HP_CORE1_UM_LP_TRNG_ALLOW_S) +#define PMS_HP_CORE1_UM_LP_TRNG_ALLOW_V 0x00000001U +#define PMS_HP_CORE1_UM_LP_TRNG_ALLOW_S 24 /** PMS_REGDMA_LP_PERI_PMS_REG register * LP Peripheral Permission register for REGDMA diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_struct.h index 2702999c72d..fff6363800c 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_struct.h @@ -10,519 +10,409 @@ extern "C" { #endif -/** Group: TEE HP2LP TEE PMS DATE REG */ -/** Type of hp2lp_tee_pms_date register - * NA +/** Group: Version Control Registers */ +/** Type of hp2lp_peri_pms_date register + * Version control register */ typedef union { struct { - /** tee_date : R/W; bitpos: [31:0]; default: 2363943; - * NA + /** hp2lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2363943; + * Version control register */ - uint32_t tee_date:32; + uint32_t hp2lp_peri_pms_date:32; }; uint32_t val; -} tee_hp2lp_tee_pms_date_reg_t; +} pms_hp2lp_peri_pms_date_reg_t; -/** Group: TEE PMS CLK EN REG */ -/** Type of pms_clk_en register - * NA +/** Group: Clock Gating Registers */ +/** Type of hp2lp_peri_pms_clk_en register + * Clock gating register */ typedef union { struct { - /** reg_clk_en : R/W; bitpos: [0]; default: 1; - * NA + /** hp2lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ - uint32_t reg_clk_en:1; + uint32_t hp2lp_peri_pms_clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} tee_pms_clk_en_reg_t; +} pms_hp2lp_peri_pms_clk_en_reg_t; -/** Group: TEE HP CORE0 MM PMS REG0 REG */ -/** Type of hp_core0_mm_pms_reg0 register - * NA +/** Group: HP CPU Permission Control Registers */ +/** Type of hp_coren_mm_pms_reg0 register + * Permission control register0 for HP CPUn in machine mode */ typedef union { struct { - /** reg_hp_core0_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; - * NA + /** hp_coren_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP System + * Registers. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_sysreg_allow:1; - /** reg_hp_core0_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t hp_coren_mm_lp_sysreg_allow:1; + /** hp_coren_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP_AONCLKRST. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_aonclkrst_allow:1; - /** reg_hp_core0_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t hp_coren_mm_lp_aonclkrst_allow:1; + /** hp_coren_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP timer. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_timer_allow:1; - /** reg_hp_core0_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t hp_coren_mm_lp_timer_allow:1; + /** hp_coren_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP ANAPERI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_anaperi_allow:1; - /** reg_hp_core0_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t hp_coren_mm_lp_anaperi_allow:1; + /** hp_coren_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP PMU. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_pmu_allow:1; - /** reg_hp_core0_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t hp_coren_mm_lp_pmu_allow:1; + /** hp_coren_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP WDT. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_wdt_allow:1; - /** reg_hp_core0_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t hp_coren_mm_lp_wdt_allow:1; + /** hp_coren_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP Mailbox + * Controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_mailbox_allow:1; - /** reg_hp_core0_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t hp_coren_mm_lp_mailbox_allow:1; + /** hp_coren_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP RTC. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core0_mm_lp_rtc_allow:1; - /** reg_hp_core0_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t hp_coren_mm_lp_rtc_allow:1; + /** hp_coren_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP PERICLKRST. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_periclkrst_allow:1; - /** reg_hp_core0_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t hp_coren_mm_lp_periclkrst_allow:1; + /** hp_coren_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP UART. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_uart_allow:1; - /** reg_hp_core0_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t hp_coren_mm_lp_uart_allow:1; + /** hp_coren_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP I2C. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_i2c_allow:1; - /** reg_hp_core0_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t hp_coren_mm_lp_i2c_allow:1; + /** hp_coren_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP SPI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_spi_allow:1; - /** reg_hp_core0_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t hp_coren_mm_lp_spi_allow:1; + /** hp_coren_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP I2C master. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_i2cmst_allow:1; - /** reg_hp_core0_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t hp_coren_mm_lp_i2cmst_allow:1; + /** hp_coren_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP I2S. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_i2s_allow:1; - /** reg_hp_core0_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t hp_coren_mm_lp_i2s_allow:1; + /** hp_coren_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP ADC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_adc_allow:1; - /** reg_hp_core0_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t hp_coren_mm_lp_adc_allow:1; + /** hp_coren_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP touch + * sensor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_touch_allow:1; - /** reg_hp_core0_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t hp_coren_mm_lp_touch_allow:1; + /** hp_coren_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP IO MUX. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_iomux_allow:1; - /** reg_hp_core0_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t hp_coren_mm_lp_iomux_allow:1; + /** hp_coren_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP INTR. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_intr_allow:1; - /** reg_hp_core0_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t hp_coren_mm_lp_intr_allow:1; + /** hp_coren_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP eFuse. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_efuse_allow:1; - /** reg_hp_core0_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t hp_coren_mm_lp_efuse_allow:1; + /** hp_coren_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access + * LP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_pms_allow:1; - /** reg_hp_core0_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; - * NA + uint32_t hp_coren_mm_lp_pms_allow:1; + /** hp_coren_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access + * HP2LP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_hp2lp_pms_allow:1; - /** reg_hp_core0_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1; - * NA + uint32_t hp_coren_mm_hp2lp_pms_allow:1; + /** hp_coren_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP temperature + * sensor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_tsens_allow:1; - /** reg_hp_core0_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t hp_coren_mm_lp_tsens_allow:1; + /** hp_coren_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1; + * Configures whether HP CPUn in machine mode has permission to LP HUK. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_huk_allow:1; - /** reg_hp_core0_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t hp_coren_mm_lp_huk_allow:1; + /** hp_coren_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP SRAM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_tcm_ram_allow:1; - /** reg_hp_core0_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t hp_coren_mm_lp_sram_allow:1; + /** hp_coren_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP RNG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_mm_lp_trng_allow:1; + uint32_t hp_coren_mm_lp_trng_allow:1; uint32_t reserved_25:7; }; uint32_t val; -} tee_hp_core0_mm_pms_reg0_reg_t; +} pms_hp_coren_mm_pms_reg0_reg_t; - -/** Group: TEE HP CORE0 UM PMS REG0 REG */ -/** Type of hp_core0_um_pms_reg0 register - * NA +/** Type of hp_coren_um_pms_reg0 register + * Permission control register0 for HP CPUn in user mode */ typedef union { struct { - /** reg_hp_core0_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; - * NA + /** hp_coren_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP System + * Registers. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_sysreg_allow:1; - /** reg_hp_core0_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t hp_coren_um_lp_sysreg_allow:1; + /** hp_coren_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP_AONCLKRST. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_aonclkrst_allow:1; - /** reg_hp_core0_um_lp_timer_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t hp_coren_um_lp_aonclkrst_allow:1; + /** hp_coren_um_lp_timer_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP timer. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_timer_allow:1; - /** reg_hp_core0_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t hp_coren_um_lp_timer_allow:1; + /** hp_coren_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP ANAPERI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_anaperi_allow:1; - /** reg_hp_core0_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t hp_coren_um_lp_anaperi_allow:1; + /** hp_coren_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP PMU. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_pmu_allow:1; - /** reg_hp_core0_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t hp_coren_um_lp_pmu_allow:1; + /** hp_coren_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP WDT. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_wdt_allow:1; - /** reg_hp_core0_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t hp_coren_um_lp_wdt_allow:1; + /** hp_coren_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP Mailbox + * Controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_mailbox_allow:1; - /** reg_hp_core0_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t hp_coren_um_lp_mailbox_allow:1; + /** hp_coren_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP RTC. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core0_um_lp_rtc_allow:1; - /** reg_hp_core0_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t hp_coren_um_lp_rtc_allow:1; + /** hp_coren_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP PERICLKRST. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_periclkrst_allow:1; - /** reg_hp_core0_um_lp_uart_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t hp_coren_um_lp_periclkrst_allow:1; + /** hp_coren_um_lp_uart_allow : R/W; bitpos: [9]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP UART. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_uart_allow:1; - /** reg_hp_core0_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t hp_coren_um_lp_uart_allow:1; + /** hp_coren_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP I2C. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_i2c_allow:1; - /** reg_hp_core0_um_lp_spi_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t hp_coren_um_lp_i2c_allow:1; + /** hp_coren_um_lp_spi_allow : R/W; bitpos: [11]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP SPI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_spi_allow:1; - /** reg_hp_core0_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t hp_coren_um_lp_spi_allow:1; + /** hp_coren_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP I2C master. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_i2cmst_allow:1; - /** reg_hp_core0_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t hp_coren_um_lp_i2cmst_allow:1; + /** hp_coren_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP I2S. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_i2s_allow:1; - /** reg_hp_core0_um_lp_adc_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t hp_coren_um_lp_i2s_allow:1; + /** hp_coren_um_lp_adc_allow : R/W; bitpos: [14]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP ADC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_adc_allow:1; - /** reg_hp_core0_um_lp_touch_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t hp_coren_um_lp_adc_allow:1; + /** hp_coren_um_lp_touch_allow : R/W; bitpos: [15]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP touch sensor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_touch_allow:1; - /** reg_hp_core0_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t hp_coren_um_lp_touch_allow:1; + /** hp_coren_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP IO MUX. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_iomux_allow:1; - /** reg_hp_core0_um_lp_intr_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t hp_coren_um_lp_iomux_allow:1; + /** hp_coren_um_lp_intr_allow : R/W; bitpos: [17]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP INTR. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_intr_allow:1; - /** reg_hp_core0_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t hp_coren_um_lp_intr_allow:1; + /** hp_coren_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP eFuse. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_efuse_allow:1; - /** reg_hp_core0_um_lp_pms_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t hp_coren_um_lp_efuse_allow:1; + /** hp_coren_um_lp_pms_allow : R/W; bitpos: [19]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_pms_allow:1; - /** reg_hp_core0_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; - * NA + uint32_t hp_coren_um_lp_pms_allow:1; + /** hp_coren_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; + * Configures whether HP CPUn in user mode has permission to access + * HP2LP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_hp2lp_pms_allow:1; - /** reg_hp_core0_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1; - * NA + uint32_t hp_coren_um_hp2lp_pms_allow:1; + /** hp_coren_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP temperature + * sensor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_tsens_allow:1; - /** reg_hp_core0_um_lp_huk_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t hp_coren_um_lp_tsens_allow:1; + /** hp_coren_um_lp_huk_allow : R/W; bitpos: [22]; default: 1; + * Configures whether HP CPUn in user mode has permission to LP HUK. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_huk_allow:1; - /** reg_hp_core0_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t hp_coren_um_lp_huk_allow:1; + /** hp_coren_um_lp_sram_allow : R/W; bitpos: [23]; default: 1; + * Configures whether HP CPUn in user mode has permission to access LP SRAM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_tcm_ram_allow:1; - /** reg_hp_core0_um_lp_trng_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t hp_coren_um_lp_sram_allow:1; + /** hp_coren_um_lp_trng_allow : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access LP RNG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_hp_core0_um_lp_trng_allow:1; + uint32_t hp_coren_um_lp_trng_allow:1; uint32_t reserved_25:7; }; uint32_t val; -} tee_hp_core0_um_pms_reg0_reg_t; +} pms_hp_coren_um_pms_reg0_reg_t; -/** Group: TEE HP CORE1 MM PMS REG0 REG */ -/** Type of hp_core1_mm_pms_reg0 register - * NA +/** Group: TEE Peripheral Permission Control Register */ +/** Type of regdma_lp_peri_pms register + * LP Peripheral Permission register for REGDMA */ typedef union { struct { - /** reg_hp_core1_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; - * NA + /** regdma_peri_lp_sram_allow : R/W; bitpos: [0]; default: 1; + * Configures whether REGDMA has permission to access LP SRAM. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core1_mm_lp_sysreg_allow:1; - /** reg_hp_core1_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t regdma_peri_lp_sram_allow:1; + /** regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1; + * Configures whether REGDMA has permission to access all LP peripherals. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core1_mm_lp_aonclkrst_allow:1; - /** reg_hp_core1_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_timer_allow:1; - /** reg_hp_core1_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_anaperi_allow:1; - /** reg_hp_core1_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_pmu_allow:1; - /** reg_hp_core1_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_wdt_allow:1; - /** reg_hp_core1_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_mailbox_allow:1; - /** reg_hp_core1_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_rtc_allow:1; - /** reg_hp_core1_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_periclkrst_allow:1; - /** reg_hp_core1_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_uart_allow:1; - /** reg_hp_core1_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_i2c_allow:1; - /** reg_hp_core1_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_spi_allow:1; - /** reg_hp_core1_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_i2cmst_allow:1; - /** reg_hp_core1_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_i2s_allow:1; - /** reg_hp_core1_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_adc_allow:1; - /** reg_hp_core1_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_touch_allow:1; - /** reg_hp_core1_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_iomux_allow:1; - /** reg_hp_core1_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_intr_allow:1; - /** reg_hp_core1_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_efuse_allow:1; - /** reg_hp_core1_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_pms_allow:1; - /** reg_hp_core1_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_hp2lp_pms_allow:1; - /** reg_hp_core1_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_tsens_allow:1; - /** reg_hp_core1_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_huk_allow:1; - /** reg_hp_core1_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_tcm_ram_allow:1; - /** reg_hp_core1_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1; - * NA - */ - uint32_t reg_hp_core1_mm_lp_trng_allow:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} tee_hp_core1_mm_pms_reg0_reg_t; - - -/** Group: TEE HP CORE1 UM PMS REG0 REG */ -/** Type of hp_core1_um_pms_reg0 register - * NA - */ -typedef union { - struct { - /** reg_hp_core1_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_sysreg_allow:1; - /** reg_hp_core1_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_aonclkrst_allow:1; - /** reg_hp_core1_um_lp_timer_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_timer_allow:1; - /** reg_hp_core1_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_anaperi_allow:1; - /** reg_hp_core1_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_pmu_allow:1; - /** reg_hp_core1_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_wdt_allow:1; - /** reg_hp_core1_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_mailbox_allow:1; - /** reg_hp_core1_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_rtc_allow:1; - /** reg_hp_core1_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_periclkrst_allow:1; - /** reg_hp_core1_um_lp_uart_allow : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_uart_allow:1; - /** reg_hp_core1_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_i2c_allow:1; - /** reg_hp_core1_um_lp_spi_allow : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_spi_allow:1; - /** reg_hp_core1_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_i2cmst_allow:1; - /** reg_hp_core1_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_i2s_allow:1; - /** reg_hp_core1_um_lp_adc_allow : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_adc_allow:1; - /** reg_hp_core1_um_lp_touch_allow : R/W; bitpos: [15]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_touch_allow:1; - /** reg_hp_core1_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_iomux_allow:1; - /** reg_hp_core1_um_lp_intr_allow : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_intr_allow:1; - /** reg_hp_core1_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_efuse_allow:1; - /** reg_hp_core1_um_lp_pms_allow : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_pms_allow:1; - /** reg_hp_core1_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_hp2lp_pms_allow:1; - /** reg_hp_core1_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_tsens_allow:1; - /** reg_hp_core1_um_lp_huk_allow : R/W; bitpos: [22]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_huk_allow:1; - /** reg_hp_core1_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_tcm_ram_allow:1; - /** reg_hp_core1_um_lp_trng_allow : R/W; bitpos: [24]; default: 1; - * NA - */ - uint32_t reg_hp_core1_um_lp_trng_allow:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} tee_hp_core1_um_pms_reg0_reg_t; - - -/** Group: TEE REGDMA PERI PMS REG */ -/** Type of regdma_peri_pms register - * NA - */ -typedef union { - struct { - /** reg_regdma_peri_lp_ram_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_regdma_peri_lp_ram_allow:1; - /** reg_regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_regdma_peri_lp_peri_allow:1; + uint32_t regdma_peri_lp_peri_allow:1; uint32_t reserved_2:30; }; uint32_t val; -} tee_regdma_peri_pms_reg_t; +} pms_regdma_lp_peri_pms_reg_t; typedef struct { - volatile tee_hp2lp_tee_pms_date_reg_t hp2lp_tee_pms_date; - volatile tee_pms_clk_en_reg_t pms_clk_en; - volatile tee_hp_core0_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0; - volatile tee_hp_core0_um_pms_reg0_reg_t hp_core0_um_pms_reg0; - volatile tee_hp_core1_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0; - volatile tee_hp_core1_um_pms_reg0_reg_t hp_core1_um_pms_reg0; - volatile tee_regdma_peri_pms_reg_t regdma_peri_pms; -} tee_dev_t; + volatile pms_hp2lp_peri_pms_date_reg_t hp2lp_peri_pms_date; + volatile pms_hp2lp_peri_pms_clk_en_reg_t hp2lp_peri_pms_clk_en; + volatile pms_hp_coren_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0; + volatile pms_hp_coren_um_pms_reg0_reg_t hp_core0_um_pms_reg0; + volatile pms_hp_coren_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0; + volatile pms_hp_coren_um_pms_reg0_reg_t hp_core1_um_pms_reg0; + volatile pms_regdma_lp_peri_pms_reg_t regdma_lp_peri_pms; +} hp2lp_peri_pms_dev_t; -extern tee_dev_t HP2LP_PERI_PMS; +extern hp2lp_peri_pms_dev_t HP2LP_PERI_PMS; #ifndef __cplusplus -_Static_assert(sizeof(tee_dev_t) == 0x1c, "Invalid size of tee_dev_t structure"); +_Static_assert(sizeof(hp2lp_peri_pms_dev_t) == 0x1c, "Invalid size of hp2lp_peri_pms_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h deleted file mode 100644 index 49d6aa16437..00000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h +++ /dev/null @@ -1,2231 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 OR MIT - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** TEE_PMS_DATE_REG register - * NA - */ -#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0) -/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943; - * NA - */ -#define TEE_TEE_DATE 0xFFFFFFFFU -#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S) -#define TEE_TEE_DATE_V 0xFFFFFFFFU -#define TEE_TEE_DATE_S 0 - -/** TEE_PMS_CLK_EN_REG register - * NA - */ -#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4) -/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CLK_EN (BIT(0)) -#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S) -#define TEE_REG_CLK_EN_V 0x00000001U -#define TEE_REG_CLK_EN_S 0 - -/** TEE_CORE0_MM_PMS_REG0_REG register - * NA - */ -#define TEE_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8) -/** TEE_REG_CORE0_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_PSRAM_ALLOW (BIT(0)) -#define TEE_REG_CORE0_MM_PSRAM_ALLOW_M (TEE_REG_CORE0_MM_PSRAM_ALLOW_V << TEE_REG_CORE0_MM_PSRAM_ALLOW_S) -#define TEE_REG_CORE0_MM_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_PSRAM_ALLOW_S 0 -/** TEE_REG_CORE0_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_FLASH_ALLOW (BIT(1)) -#define TEE_REG_CORE0_MM_FLASH_ALLOW_M (TEE_REG_CORE0_MM_FLASH_ALLOW_V << TEE_REG_CORE0_MM_FLASH_ALLOW_S) -#define TEE_REG_CORE0_MM_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_FLASH_ALLOW_S 1 -/** TEE_REG_CORE0_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_L2MEM_ALLOW (BIT(2)) -#define TEE_REG_CORE0_MM_L2MEM_ALLOW_M (TEE_REG_CORE0_MM_L2MEM_ALLOW_V << TEE_REG_CORE0_MM_L2MEM_ALLOW_S) -#define TEE_REG_CORE0_MM_L2MEM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_L2MEM_ALLOW_S 2 -/** TEE_REG_CORE0_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_L2ROM_ALLOW (BIT(3)) -#define TEE_REG_CORE0_MM_L2ROM_ALLOW_M (TEE_REG_CORE0_MM_L2ROM_ALLOW_V << TEE_REG_CORE0_MM_L2ROM_ALLOW_S) -#define TEE_REG_CORE0_MM_L2ROM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_L2ROM_ALLOW_S 3 -/** TEE_REG_CORE0_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_TRACE0_ALLOW (BIT(6)) -#define TEE_REG_CORE0_MM_TRACE0_ALLOW_M (TEE_REG_CORE0_MM_TRACE0_ALLOW_V << TEE_REG_CORE0_MM_TRACE0_ALLOW_S) -#define TEE_REG_CORE0_MM_TRACE0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_TRACE0_ALLOW_S 6 -/** TEE_REG_CORE0_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_TRACE1_ALLOW (BIT(7)) -#define TEE_REG_CORE0_MM_TRACE1_ALLOW_M (TEE_REG_CORE0_MM_TRACE1_ALLOW_V << TEE_REG_CORE0_MM_TRACE1_ALLOW_S) -#define TEE_REG_CORE0_MM_TRACE1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_TRACE1_ALLOW_S 7 -/** TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW (BIT(8)) -#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_M (TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_S) -#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_S 8 -/** TEE_REG_CORE0_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW (BIT(9)) -#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_M (TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_V << TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_S) -#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_S 9 -/** TEE_REG_CORE0_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_TCM_MON_ALLOW (BIT(10)) -#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_M (TEE_REG_CORE0_MM_TCM_MON_ALLOW_V << TEE_REG_CORE0_MM_TCM_MON_ALLOW_S) -#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_S 10 -/** TEE_REG_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_CACHE_ALLOW (BIT(11)) -#define TEE_REG_CORE0_MM_CACHE_ALLOW_M (TEE_REG_CORE0_MM_CACHE_ALLOW_V << TEE_REG_CORE0_MM_CACHE_ALLOW_S) -#define TEE_REG_CORE0_MM_CACHE_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_CACHE_ALLOW_S 11 - -/** TEE_CORE0_MM_PMS_REG1_REG register - * NA - */ -#define TEE_CORE0_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0xc) -/** TEE_REG_CORE0_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW (BIT(0)) -#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_M (TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_S 0 -/** TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW (BIT(1)) -#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_M (TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_S 1 -/** TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW (BIT(2)) -#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_M (TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S 2 -/** TEE_REG_CORE0_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW (BIT(3)) -#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_M (TEE_REG_CORE0_MM_HP_GDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_GDMA_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_S 3 -/** TEE_REG_CORE0_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW (BIT(4)) -#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_M (TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_S 4 -/** TEE_REG_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW (BIT(5)) -#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_M (TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_V << TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_S 5 -/** TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW (BIT(6)) -#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_M (TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_S 6 -/** TEE_REG_CORE0_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW (BIT(7)) -#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_M (TEE_REG_CORE0_MM_HP_JPEG_ALLOW_V << TEE_REG_CORE0_MM_HP_JPEG_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_S 7 -/** TEE_REG_CORE0_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_PPA_ALLOW (BIT(8)) -#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_M (TEE_REG_CORE0_MM_HP_PPA_ALLOW_V << TEE_REG_CORE0_MM_HP_PPA_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_S 8 -/** TEE_REG_CORE0_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW (BIT(9)) -#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_M (TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_V << TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_S 9 -/** TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW (BIT(10)) -#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_M (TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_S 10 -/** TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW (BIT(11)) -#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_M (TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_S 11 -/** TEE_REG_CORE0_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW (BIT(12)) -#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_M (TEE_REG_CORE0_MM_HP_FLASH_ALLOW_V << TEE_REG_CORE0_MM_HP_FLASH_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_S 12 -/** TEE_REG_CORE0_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW (BIT(13)) -#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_M (TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_V << TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_S 13 -/** TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW (BIT(14)) -#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_M (TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_S 14 -/** TEE_REG_CORE0_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW (BIT(15)) -#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_M (TEE_REG_CORE0_MM_HP_GMAC_ALLOW_V << TEE_REG_CORE0_MM_HP_GMAC_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_S 15 -/** TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW (BIT(16)) -#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_M (TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_S 16 -/** TEE_REG_CORE0_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_PVT_ALLOW (BIT(17)) -#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_M (TEE_REG_CORE0_MM_HP_PVT_ALLOW_V << TEE_REG_CORE0_MM_HP_PVT_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_S 17 -/** TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW (BIT(18)) -#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_M (TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_S 18 -/** TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW (BIT(19)) -#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_M (TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_S 19 -/** TEE_REG_CORE0_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_ISP_ALLOW (BIT(20)) -#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_M (TEE_REG_CORE0_MM_HP_ISP_ALLOW_V << TEE_REG_CORE0_MM_HP_ISP_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_S 20 -/** TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW (BIT(21)) -#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_M (TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_S 21 -/** TEE_REG_CORE0_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_RMT_ALLOW (BIT(22)) -#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_M (TEE_REG_CORE0_MM_HP_RMT_ALLOW_V << TEE_REG_CORE0_MM_HP_RMT_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_S 22 -/** TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_S 23 -/** TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW (BIT(24)) -#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_M (TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_S 24 -/** TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW (BIT(25)) -#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_M (TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_S 25 -/** TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW (BIT(26)) -#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_M (TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S) -#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S 26 -/** TEE_REG_CORE0_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW (BIT(27)) -#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_M (TEE_REG_CORE0_MM_DMA_PMS_ALLOW_V << TEE_REG_CORE0_MM_DMA_PMS_ALLOW_S) -#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_S 27 -/** TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW (BIT(28)) -#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_M (TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_S 28 -/** TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW (BIT(29)) -#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_M (TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_S) -#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_S 29 - -/** TEE_CORE0_MM_PMS_REG2_REG register - * NA - */ -#define TEE_CORE0_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x10) -/** TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW (BIT(0)) -#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_M (TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_S 0 -/** TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW (BIT(1)) -#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_M (TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_S 1 -/** TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW (BIT(2)) -#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_M (TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S 2 -/** TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW (BIT(3)) -#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_M (TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S 3 -/** TEE_REG_CORE0_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW (BIT(4)) -#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_M (TEE_REG_CORE0_MM_HP_I2C0_ALLOW_V << TEE_REG_CORE0_MM_HP_I2C0_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_S 4 -/** TEE_REG_CORE0_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW (BIT(5)) -#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_M (TEE_REG_CORE0_MM_HP_I2C1_ALLOW_V << TEE_REG_CORE0_MM_HP_I2C1_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_S 5 -/** TEE_REG_CORE0_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW (BIT(6)) -#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_M (TEE_REG_CORE0_MM_HP_I2S0_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S0_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_S 6 -/** TEE_REG_CORE0_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW (BIT(7)) -#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_M (TEE_REG_CORE0_MM_HP_I2S1_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S1_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_S 7 -/** TEE_REG_CORE0_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW (BIT(8)) -#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_M (TEE_REG_CORE0_MM_HP_I2S2_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S2_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_S 8 -/** TEE_REG_CORE0_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW (BIT(9)) -#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_M (TEE_REG_CORE0_MM_HP_PCNT_ALLOW_V << TEE_REG_CORE0_MM_HP_PCNT_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_S 9 -/** TEE_REG_CORE0_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_UART0_ALLOW (BIT(10)) -#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_M (TEE_REG_CORE0_MM_HP_UART0_ALLOW_V << TEE_REG_CORE0_MM_HP_UART0_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_S 10 -/** TEE_REG_CORE0_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_UART1_ALLOW (BIT(11)) -#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_M (TEE_REG_CORE0_MM_HP_UART1_ALLOW_V << TEE_REG_CORE0_MM_HP_UART1_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_S 11 -/** TEE_REG_CORE0_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_UART2_ALLOW (BIT(12)) -#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_M (TEE_REG_CORE0_MM_HP_UART2_ALLOW_V << TEE_REG_CORE0_MM_HP_UART2_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_S 12 -/** TEE_REG_CORE0_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_UART3_ALLOW (BIT(13)) -#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_M (TEE_REG_CORE0_MM_HP_UART3_ALLOW_V << TEE_REG_CORE0_MM_HP_UART3_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_S 13 -/** TEE_REG_CORE0_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_UART4_ALLOW (BIT(14)) -#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_M (TEE_REG_CORE0_MM_HP_UART4_ALLOW_V << TEE_REG_CORE0_MM_HP_UART4_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_S 14 -/** TEE_REG_CORE0_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW (BIT(15)) -#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_M (TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_V << TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_S 15 -/** TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW (BIT(16)) -#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_M (TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_S 16 -/** TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW (BIT(17)) -#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_M (TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_S 17 -/** TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW (BIT(18)) -#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_M (TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_S 18 -/** TEE_REG_CORE0_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW (BIT(19)) -#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_M (TEE_REG_CORE0_MM_HP_LEDC_ALLOW_V << TEE_REG_CORE0_MM_HP_LEDC_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_S 19 -/** TEE_REG_CORE0_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_ETM_ALLOW (BIT(21)) -#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_M (TEE_REG_CORE0_MM_HP_ETM_ALLOW_V << TEE_REG_CORE0_MM_HP_ETM_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_S 21 -/** TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW (BIT(22)) -#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_M (TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_S 22 -/** TEE_REG_CORE0_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW (BIT(23)) -#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_M (TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_S 23 -/** TEE_REG_CORE0_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW (BIT(24)) -#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_M (TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_S 24 -/** TEE_REG_CORE0_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW (BIT(25)) -#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_M (TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_S 25 -/** TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW (BIT(26)) -#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_M (TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_S 26 -/** TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW (BIT(27)) -#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_M (TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_S 27 -/** TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW (BIT(28)) -#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_M (TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_S 28 -/** TEE_REG_CORE0_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_ADC_ALLOW (BIT(30)) -#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_M (TEE_REG_CORE0_MM_HP_ADC_ALLOW_V << TEE_REG_CORE0_MM_HP_ADC_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_S 30 -/** TEE_REG_CORE0_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW (BIT(31)) -#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_M (TEE_REG_CORE0_MM_HP_UHCI_ALLOW_V << TEE_REG_CORE0_MM_HP_UHCI_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_S 31 - -/** TEE_CORE0_MM_PMS_REG3_REG register - * NA - */ -#define TEE_CORE0_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x14) -/** TEE_REG_CORE0_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW (BIT(0)) -#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_M (TEE_REG_CORE0_MM_HP_GPIO_ALLOW_V << TEE_REG_CORE0_MM_HP_GPIO_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_S 0 -/** TEE_REG_CORE0_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW (BIT(1)) -#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_M (TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_V << TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_S 1 -/** TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW (BIT(2)) -#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_M (TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_S 2 -/** TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW (BIT(3)) -#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_M (TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_S 3 -/** TEE_REG_CORE0_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW (BIT(4)) -#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_M (TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_V << TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_S 4 - -/** TEE_CORE0_UM_PMS_REG0_REG register - * NA - */ -#define TEE_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x18) -/** TEE_REG_CORE0_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_PSRAM_ALLOW (BIT(0)) -#define TEE_REG_CORE0_UM_PSRAM_ALLOW_M (TEE_REG_CORE0_UM_PSRAM_ALLOW_V << TEE_REG_CORE0_UM_PSRAM_ALLOW_S) -#define TEE_REG_CORE0_UM_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_PSRAM_ALLOW_S 0 -/** TEE_REG_CORE0_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_FLASH_ALLOW (BIT(1)) -#define TEE_REG_CORE0_UM_FLASH_ALLOW_M (TEE_REG_CORE0_UM_FLASH_ALLOW_V << TEE_REG_CORE0_UM_FLASH_ALLOW_S) -#define TEE_REG_CORE0_UM_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_FLASH_ALLOW_S 1 -/** TEE_REG_CORE0_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_L2MEM_ALLOW (BIT(2)) -#define TEE_REG_CORE0_UM_L2MEM_ALLOW_M (TEE_REG_CORE0_UM_L2MEM_ALLOW_V << TEE_REG_CORE0_UM_L2MEM_ALLOW_S) -#define TEE_REG_CORE0_UM_L2MEM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_L2MEM_ALLOW_S 2 -/** TEE_REG_CORE0_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_L2ROM_ALLOW (BIT(3)) -#define TEE_REG_CORE0_UM_L2ROM_ALLOW_M (TEE_REG_CORE0_UM_L2ROM_ALLOW_V << TEE_REG_CORE0_UM_L2ROM_ALLOW_S) -#define TEE_REG_CORE0_UM_L2ROM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_L2ROM_ALLOW_S 3 -/** TEE_REG_CORE0_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_TRACE0_ALLOW (BIT(6)) -#define TEE_REG_CORE0_UM_TRACE0_ALLOW_M (TEE_REG_CORE0_UM_TRACE0_ALLOW_V << TEE_REG_CORE0_UM_TRACE0_ALLOW_S) -#define TEE_REG_CORE0_UM_TRACE0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_TRACE0_ALLOW_S 6 -/** TEE_REG_CORE0_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_TRACE1_ALLOW (BIT(7)) -#define TEE_REG_CORE0_UM_TRACE1_ALLOW_M (TEE_REG_CORE0_UM_TRACE1_ALLOW_V << TEE_REG_CORE0_UM_TRACE1_ALLOW_S) -#define TEE_REG_CORE0_UM_TRACE1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_TRACE1_ALLOW_S 7 -/** TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW (BIT(8)) -#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_M (TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_S) -#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_S 8 -/** TEE_REG_CORE0_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW (BIT(9)) -#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_M (TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_V << TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_S) -#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_S 9 -/** TEE_REG_CORE0_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_TCM_MON_ALLOW (BIT(10)) -#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_M (TEE_REG_CORE0_UM_TCM_MON_ALLOW_V << TEE_REG_CORE0_UM_TCM_MON_ALLOW_S) -#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_S 10 -/** TEE_REG_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_CACHE_ALLOW (BIT(11)) -#define TEE_REG_CORE0_UM_CACHE_ALLOW_M (TEE_REG_CORE0_UM_CACHE_ALLOW_V << TEE_REG_CORE0_UM_CACHE_ALLOW_S) -#define TEE_REG_CORE0_UM_CACHE_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_CACHE_ALLOW_S 11 - -/** TEE_CORE0_UM_PMS_REG1_REG register - * NA - */ -#define TEE_CORE0_UM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x1c) -/** TEE_REG_CORE0_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW (BIT(0)) -#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_M (TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_S 0 -/** TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW (BIT(1)) -#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_M (TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_S 1 -/** TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW (BIT(2)) -#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_M (TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S 2 -/** TEE_REG_CORE0_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW (BIT(3)) -#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_M (TEE_REG_CORE0_UM_HP_GDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_GDMA_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_S 3 -/** TEE_REG_CORE0_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW (BIT(4)) -#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_M (TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_S 4 -/** TEE_REG_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW (BIT(5)) -#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_M (TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_V << TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_S 5 -/** TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW (BIT(6)) -#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_M (TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_S 6 -/** TEE_REG_CORE0_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW (BIT(7)) -#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_M (TEE_REG_CORE0_UM_HP_JPEG_ALLOW_V << TEE_REG_CORE0_UM_HP_JPEG_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_S 7 -/** TEE_REG_CORE0_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_PPA_ALLOW (BIT(8)) -#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_M (TEE_REG_CORE0_UM_HP_PPA_ALLOW_V << TEE_REG_CORE0_UM_HP_PPA_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_S 8 -/** TEE_REG_CORE0_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW (BIT(9)) -#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_M (TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_V << TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_S 9 -/** TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW (BIT(10)) -#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_M (TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_S 10 -/** TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW (BIT(11)) -#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_M (TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_S 11 -/** TEE_REG_CORE0_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW (BIT(12)) -#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_M (TEE_REG_CORE0_UM_HP_FLASH_ALLOW_V << TEE_REG_CORE0_UM_HP_FLASH_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_S 12 -/** TEE_REG_CORE0_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW (BIT(13)) -#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_M (TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_V << TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_S 13 -/** TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW (BIT(14)) -#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_M (TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_S 14 -/** TEE_REG_CORE0_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW (BIT(15)) -#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_M (TEE_REG_CORE0_UM_HP_GMAC_ALLOW_V << TEE_REG_CORE0_UM_HP_GMAC_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_S 15 -/** TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW (BIT(16)) -#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_M (TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_S 16 -/** TEE_REG_CORE0_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_PVT_ALLOW (BIT(17)) -#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_M (TEE_REG_CORE0_UM_HP_PVT_ALLOW_V << TEE_REG_CORE0_UM_HP_PVT_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_S 17 -/** TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW (BIT(18)) -#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_M (TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_S 18 -/** TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW (BIT(19)) -#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_M (TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_S 19 -/** TEE_REG_CORE0_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_ISP_ALLOW (BIT(20)) -#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_M (TEE_REG_CORE0_UM_HP_ISP_ALLOW_V << TEE_REG_CORE0_UM_HP_ISP_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_S 20 -/** TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW (BIT(21)) -#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_M (TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_S 21 -/** TEE_REG_CORE0_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_RMT_ALLOW (BIT(22)) -#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_M (TEE_REG_CORE0_UM_HP_RMT_ALLOW_V << TEE_REG_CORE0_UM_HP_RMT_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_S 22 -/** TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_S 23 -/** TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW (BIT(24)) -#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_M (TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_S 24 -/** TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW (BIT(25)) -#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_M (TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_S 25 -/** TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW (BIT(26)) -#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_M (TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S) -#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S 26 -/** TEE_REG_CORE0_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW (BIT(27)) -#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_M (TEE_REG_CORE0_UM_DMA_PMS_ALLOW_V << TEE_REG_CORE0_UM_DMA_PMS_ALLOW_S) -#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_S 27 -/** TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW (BIT(28)) -#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_M (TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_S 28 -/** TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW (BIT(29)) -#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_M (TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_S) -#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_S 29 - -/** TEE_CORE0_UM_PMS_REG2_REG register - * NA - */ -#define TEE_CORE0_UM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x20) -/** TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW (BIT(0)) -#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_M (TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_S 0 -/** TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW (BIT(1)) -#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_M (TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_S 1 -/** TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW (BIT(2)) -#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_M (TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S 2 -/** TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW (BIT(3)) -#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_M (TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S 3 -/** TEE_REG_CORE0_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW (BIT(4)) -#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_M (TEE_REG_CORE0_UM_HP_I2C0_ALLOW_V << TEE_REG_CORE0_UM_HP_I2C0_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_S 4 -/** TEE_REG_CORE0_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW (BIT(5)) -#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_M (TEE_REG_CORE0_UM_HP_I2C1_ALLOW_V << TEE_REG_CORE0_UM_HP_I2C1_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_S 5 -/** TEE_REG_CORE0_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW (BIT(6)) -#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_M (TEE_REG_CORE0_UM_HP_I2S0_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S0_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_S 6 -/** TEE_REG_CORE0_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW (BIT(7)) -#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_M (TEE_REG_CORE0_UM_HP_I2S1_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S1_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_S 7 -/** TEE_REG_CORE0_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW (BIT(8)) -#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_M (TEE_REG_CORE0_UM_HP_I2S2_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S2_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_S 8 -/** TEE_REG_CORE0_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW (BIT(9)) -#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_M (TEE_REG_CORE0_UM_HP_PCNT_ALLOW_V << TEE_REG_CORE0_UM_HP_PCNT_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_S 9 -/** TEE_REG_CORE0_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_UART0_ALLOW (BIT(10)) -#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_M (TEE_REG_CORE0_UM_HP_UART0_ALLOW_V << TEE_REG_CORE0_UM_HP_UART0_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_S 10 -/** TEE_REG_CORE0_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_UART1_ALLOW (BIT(11)) -#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_M (TEE_REG_CORE0_UM_HP_UART1_ALLOW_V << TEE_REG_CORE0_UM_HP_UART1_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_S 11 -/** TEE_REG_CORE0_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_UART2_ALLOW (BIT(12)) -#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_M (TEE_REG_CORE0_UM_HP_UART2_ALLOW_V << TEE_REG_CORE0_UM_HP_UART2_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_S 12 -/** TEE_REG_CORE0_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_UART3_ALLOW (BIT(13)) -#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_M (TEE_REG_CORE0_UM_HP_UART3_ALLOW_V << TEE_REG_CORE0_UM_HP_UART3_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_S 13 -/** TEE_REG_CORE0_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_UART4_ALLOW (BIT(14)) -#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_M (TEE_REG_CORE0_UM_HP_UART4_ALLOW_V << TEE_REG_CORE0_UM_HP_UART4_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_S 14 -/** TEE_REG_CORE0_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW (BIT(15)) -#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_M (TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_V << TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_S 15 -/** TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW (BIT(16)) -#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_M (TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_S 16 -/** TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW (BIT(17)) -#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_M (TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_S 17 -/** TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW (BIT(18)) -#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_M (TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_S 18 -/** TEE_REG_CORE0_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW (BIT(19)) -#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_M (TEE_REG_CORE0_UM_HP_LEDC_ALLOW_V << TEE_REG_CORE0_UM_HP_LEDC_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_S 19 -/** TEE_REG_CORE0_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_ETM_ALLOW (BIT(21)) -#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_M (TEE_REG_CORE0_UM_HP_ETM_ALLOW_V << TEE_REG_CORE0_UM_HP_ETM_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_S 21 -/** TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW (BIT(22)) -#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_M (TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_S 22 -/** TEE_REG_CORE0_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW (BIT(23)) -#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_M (TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_S 23 -/** TEE_REG_CORE0_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW (BIT(24)) -#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_M (TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_S 24 -/** TEE_REG_CORE0_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW (BIT(25)) -#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_M (TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_S 25 -/** TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW (BIT(26)) -#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_M (TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_S 26 -/** TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW (BIT(27)) -#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_M (TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_S 27 -/** TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW (BIT(28)) -#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_M (TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_S 28 -/** TEE_REG_CORE0_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_ADC_ALLOW (BIT(30)) -#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_M (TEE_REG_CORE0_UM_HP_ADC_ALLOW_V << TEE_REG_CORE0_UM_HP_ADC_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_S 30 -/** TEE_REG_CORE0_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW (BIT(31)) -#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_M (TEE_REG_CORE0_UM_HP_UHCI_ALLOW_V << TEE_REG_CORE0_UM_HP_UHCI_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_S 31 - -/** TEE_CORE0_UM_PMS_REG3_REG register - * NA - */ -#define TEE_CORE0_UM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x24) -/** TEE_REG_CORE0_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW (BIT(0)) -#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_M (TEE_REG_CORE0_UM_HP_GPIO_ALLOW_V << TEE_REG_CORE0_UM_HP_GPIO_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_S 0 -/** TEE_REG_CORE0_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW (BIT(1)) -#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_M (TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_V << TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_S 1 -/** TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW (BIT(2)) -#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_M (TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_S 2 -/** TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW (BIT(3)) -#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_M (TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_S 3 -/** TEE_REG_CORE0_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW (BIT(4)) -#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_M (TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_V << TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_S 4 - -/** TEE_CORE1_MM_PMS_REG0_REG register - * NA - */ -#define TEE_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x28) -/** TEE_REG_CORE1_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_PSRAM_ALLOW (BIT(0)) -#define TEE_REG_CORE1_MM_PSRAM_ALLOW_M (TEE_REG_CORE1_MM_PSRAM_ALLOW_V << TEE_REG_CORE1_MM_PSRAM_ALLOW_S) -#define TEE_REG_CORE1_MM_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_PSRAM_ALLOW_S 0 -/** TEE_REG_CORE1_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_FLASH_ALLOW (BIT(1)) -#define TEE_REG_CORE1_MM_FLASH_ALLOW_M (TEE_REG_CORE1_MM_FLASH_ALLOW_V << TEE_REG_CORE1_MM_FLASH_ALLOW_S) -#define TEE_REG_CORE1_MM_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_FLASH_ALLOW_S 1 -/** TEE_REG_CORE1_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_L2MEM_ALLOW (BIT(2)) -#define TEE_REG_CORE1_MM_L2MEM_ALLOW_M (TEE_REG_CORE1_MM_L2MEM_ALLOW_V << TEE_REG_CORE1_MM_L2MEM_ALLOW_S) -#define TEE_REG_CORE1_MM_L2MEM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_L2MEM_ALLOW_S 2 -/** TEE_REG_CORE1_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_L2ROM_ALLOW (BIT(3)) -#define TEE_REG_CORE1_MM_L2ROM_ALLOW_M (TEE_REG_CORE1_MM_L2ROM_ALLOW_V << TEE_REG_CORE1_MM_L2ROM_ALLOW_S) -#define TEE_REG_CORE1_MM_L2ROM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_L2ROM_ALLOW_S 3 -/** TEE_REG_CORE1_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_TRACE0_ALLOW (BIT(6)) -#define TEE_REG_CORE1_MM_TRACE0_ALLOW_M (TEE_REG_CORE1_MM_TRACE0_ALLOW_V << TEE_REG_CORE1_MM_TRACE0_ALLOW_S) -#define TEE_REG_CORE1_MM_TRACE0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_TRACE0_ALLOW_S 6 -/** TEE_REG_CORE1_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_TRACE1_ALLOW (BIT(7)) -#define TEE_REG_CORE1_MM_TRACE1_ALLOW_M (TEE_REG_CORE1_MM_TRACE1_ALLOW_V << TEE_REG_CORE1_MM_TRACE1_ALLOW_S) -#define TEE_REG_CORE1_MM_TRACE1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_TRACE1_ALLOW_S 7 -/** TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW (BIT(8)) -#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_M (TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_S) -#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_S 8 -/** TEE_REG_CORE1_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW (BIT(9)) -#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_M (TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_V << TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_S) -#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_S 9 -/** TEE_REG_CORE1_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_TCM_MON_ALLOW (BIT(10)) -#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_M (TEE_REG_CORE1_MM_TCM_MON_ALLOW_V << TEE_REG_CORE1_MM_TCM_MON_ALLOW_S) -#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_S 10 -/** TEE_REG_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_CACHE_ALLOW (BIT(11)) -#define TEE_REG_CORE1_MM_CACHE_ALLOW_M (TEE_REG_CORE1_MM_CACHE_ALLOW_V << TEE_REG_CORE1_MM_CACHE_ALLOW_S) -#define TEE_REG_CORE1_MM_CACHE_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_CACHE_ALLOW_S 11 - -/** TEE_CORE1_MM_PMS_REG1_REG register - * NA - */ -#define TEE_CORE1_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x2c) -/** TEE_REG_CORE1_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW (BIT(0)) -#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_M (TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_S 0 -/** TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW (BIT(1)) -#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_M (TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_S 1 -/** TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW (BIT(2)) -#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_M (TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S 2 -/** TEE_REG_CORE1_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW (BIT(3)) -#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_M (TEE_REG_CORE1_MM_HP_GDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_GDMA_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_S 3 -/** TEE_REG_CORE1_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW (BIT(4)) -#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_M (TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_S 4 -/** TEE_REG_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW (BIT(5)) -#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_M (TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_V << TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_S 5 -/** TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW (BIT(6)) -#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_M (TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_S 6 -/** TEE_REG_CORE1_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW (BIT(7)) -#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_M (TEE_REG_CORE1_MM_HP_JPEG_ALLOW_V << TEE_REG_CORE1_MM_HP_JPEG_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_S 7 -/** TEE_REG_CORE1_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_PPA_ALLOW (BIT(8)) -#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_M (TEE_REG_CORE1_MM_HP_PPA_ALLOW_V << TEE_REG_CORE1_MM_HP_PPA_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_S 8 -/** TEE_REG_CORE1_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW (BIT(9)) -#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_M (TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_V << TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_S 9 -/** TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW (BIT(10)) -#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_M (TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_S 10 -/** TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW (BIT(11)) -#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_M (TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_S 11 -/** TEE_REG_CORE1_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW (BIT(12)) -#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_M (TEE_REG_CORE1_MM_HP_FLASH_ALLOW_V << TEE_REG_CORE1_MM_HP_FLASH_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_S 12 -/** TEE_REG_CORE1_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW (BIT(13)) -#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_M (TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_V << TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_S 13 -/** TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW (BIT(14)) -#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_M (TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_S 14 -/** TEE_REG_CORE1_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW (BIT(15)) -#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_M (TEE_REG_CORE1_MM_HP_GMAC_ALLOW_V << TEE_REG_CORE1_MM_HP_GMAC_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_S 15 -/** TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW (BIT(16)) -#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_M (TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_S 16 -/** TEE_REG_CORE1_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_PVT_ALLOW (BIT(17)) -#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_M (TEE_REG_CORE1_MM_HP_PVT_ALLOW_V << TEE_REG_CORE1_MM_HP_PVT_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_S 17 -/** TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW (BIT(18)) -#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_M (TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_S 18 -/** TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW (BIT(19)) -#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_M (TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_S 19 -/** TEE_REG_CORE1_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_ISP_ALLOW (BIT(20)) -#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_M (TEE_REG_CORE1_MM_HP_ISP_ALLOW_V << TEE_REG_CORE1_MM_HP_ISP_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_S 20 -/** TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW (BIT(21)) -#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_M (TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_S 21 -/** TEE_REG_CORE1_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_RMT_ALLOW (BIT(22)) -#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_M (TEE_REG_CORE1_MM_HP_RMT_ALLOW_V << TEE_REG_CORE1_MM_HP_RMT_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_S 22 -/** TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_S 23 -/** TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW (BIT(24)) -#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_M (TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_S 24 -/** TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW (BIT(25)) -#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_M (TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_S 25 -/** TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW (BIT(26)) -#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_M (TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S) -#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S 26 -/** TEE_REG_CORE1_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW (BIT(27)) -#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_M (TEE_REG_CORE1_MM_DMA_PMS_ALLOW_V << TEE_REG_CORE1_MM_DMA_PMS_ALLOW_S) -#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_S 27 -/** TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW (BIT(28)) -#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_M (TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_S 28 -/** TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW (BIT(29)) -#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_M (TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_S) -#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_S 29 - -/** TEE_CORE1_MM_PMS_REG2_REG register - * NA - */ -#define TEE_CORE1_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x30) -/** TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW (BIT(0)) -#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_M (TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_S 0 -/** TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW (BIT(1)) -#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_M (TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_S 1 -/** TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW (BIT(2)) -#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_M (TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S 2 -/** TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW (BIT(3)) -#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_M (TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S 3 -/** TEE_REG_CORE1_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW (BIT(4)) -#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_M (TEE_REG_CORE1_MM_HP_I2C0_ALLOW_V << TEE_REG_CORE1_MM_HP_I2C0_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_S 4 -/** TEE_REG_CORE1_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW (BIT(5)) -#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_M (TEE_REG_CORE1_MM_HP_I2C1_ALLOW_V << TEE_REG_CORE1_MM_HP_I2C1_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_S 5 -/** TEE_REG_CORE1_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW (BIT(6)) -#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_M (TEE_REG_CORE1_MM_HP_I2S0_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S0_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_S 6 -/** TEE_REG_CORE1_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW (BIT(7)) -#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_M (TEE_REG_CORE1_MM_HP_I2S1_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S1_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_S 7 -/** TEE_REG_CORE1_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW (BIT(8)) -#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_M (TEE_REG_CORE1_MM_HP_I2S2_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S2_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_S 8 -/** TEE_REG_CORE1_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW (BIT(9)) -#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_M (TEE_REG_CORE1_MM_HP_PCNT_ALLOW_V << TEE_REG_CORE1_MM_HP_PCNT_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_S 9 -/** TEE_REG_CORE1_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_UART0_ALLOW (BIT(10)) -#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_M (TEE_REG_CORE1_MM_HP_UART0_ALLOW_V << TEE_REG_CORE1_MM_HP_UART0_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_S 10 -/** TEE_REG_CORE1_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_UART1_ALLOW (BIT(11)) -#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_M (TEE_REG_CORE1_MM_HP_UART1_ALLOW_V << TEE_REG_CORE1_MM_HP_UART1_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_S 11 -/** TEE_REG_CORE1_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_UART2_ALLOW (BIT(12)) -#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_M (TEE_REG_CORE1_MM_HP_UART2_ALLOW_V << TEE_REG_CORE1_MM_HP_UART2_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_S 12 -/** TEE_REG_CORE1_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_UART3_ALLOW (BIT(13)) -#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_M (TEE_REG_CORE1_MM_HP_UART3_ALLOW_V << TEE_REG_CORE1_MM_HP_UART3_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_S 13 -/** TEE_REG_CORE1_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_UART4_ALLOW (BIT(14)) -#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_M (TEE_REG_CORE1_MM_HP_UART4_ALLOW_V << TEE_REG_CORE1_MM_HP_UART4_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_S 14 -/** TEE_REG_CORE1_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW (BIT(15)) -#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_M (TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_V << TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_S 15 -/** TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW (BIT(16)) -#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_M (TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_S 16 -/** TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW (BIT(17)) -#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_M (TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_S 17 -/** TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW (BIT(18)) -#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_M (TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_S 18 -/** TEE_REG_CORE1_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW (BIT(19)) -#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_M (TEE_REG_CORE1_MM_HP_LEDC_ALLOW_V << TEE_REG_CORE1_MM_HP_LEDC_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_S 19 -/** TEE_REG_CORE1_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_ETM_ALLOW (BIT(21)) -#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_M (TEE_REG_CORE1_MM_HP_ETM_ALLOW_V << TEE_REG_CORE1_MM_HP_ETM_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_S 21 -/** TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW (BIT(22)) -#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_M (TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_S 22 -/** TEE_REG_CORE1_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW (BIT(23)) -#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_M (TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_S 23 -/** TEE_REG_CORE1_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW (BIT(24)) -#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_M (TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_S 24 -/** TEE_REG_CORE1_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW (BIT(25)) -#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_M (TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_S 25 -/** TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW (BIT(26)) -#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_M (TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_S 26 -/** TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW (BIT(27)) -#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_M (TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_S 27 -/** TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW (BIT(28)) -#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_M (TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_S 28 -/** TEE_REG_CORE1_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_ADC_ALLOW (BIT(30)) -#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_M (TEE_REG_CORE1_MM_HP_ADC_ALLOW_V << TEE_REG_CORE1_MM_HP_ADC_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_S 30 -/** TEE_REG_CORE1_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW (BIT(31)) -#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_M (TEE_REG_CORE1_MM_HP_UHCI_ALLOW_V << TEE_REG_CORE1_MM_HP_UHCI_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_S 31 - -/** TEE_CORE1_MM_PMS_REG3_REG register - * NA - */ -#define TEE_CORE1_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x34) -/** TEE_REG_CORE1_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW (BIT(0)) -#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_M (TEE_REG_CORE1_MM_HP_GPIO_ALLOW_V << TEE_REG_CORE1_MM_HP_GPIO_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_S 0 -/** TEE_REG_CORE1_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW (BIT(1)) -#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_M (TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_V << TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_S 1 -/** TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW (BIT(2)) -#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_M (TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_S 2 -/** TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW (BIT(3)) -#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_M (TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_S 3 -/** TEE_REG_CORE1_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW (BIT(4)) -#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_M (TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_V << TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_S 4 - -/** TEE_CORE1_UM_PMS_REG0_REG register - * NA - */ -#define TEE_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x38) -/** TEE_REG_CORE1_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_PSRAM_ALLOW (BIT(0)) -#define TEE_REG_CORE1_UM_PSRAM_ALLOW_M (TEE_REG_CORE1_UM_PSRAM_ALLOW_V << TEE_REG_CORE1_UM_PSRAM_ALLOW_S) -#define TEE_REG_CORE1_UM_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_PSRAM_ALLOW_S 0 -/** TEE_REG_CORE1_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_FLASH_ALLOW (BIT(1)) -#define TEE_REG_CORE1_UM_FLASH_ALLOW_M (TEE_REG_CORE1_UM_FLASH_ALLOW_V << TEE_REG_CORE1_UM_FLASH_ALLOW_S) -#define TEE_REG_CORE1_UM_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_FLASH_ALLOW_S 1 -/** TEE_REG_CORE1_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_L2MEM_ALLOW (BIT(2)) -#define TEE_REG_CORE1_UM_L2MEM_ALLOW_M (TEE_REG_CORE1_UM_L2MEM_ALLOW_V << TEE_REG_CORE1_UM_L2MEM_ALLOW_S) -#define TEE_REG_CORE1_UM_L2MEM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_L2MEM_ALLOW_S 2 -/** TEE_REG_CORE1_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_L2ROM_ALLOW (BIT(3)) -#define TEE_REG_CORE1_UM_L2ROM_ALLOW_M (TEE_REG_CORE1_UM_L2ROM_ALLOW_V << TEE_REG_CORE1_UM_L2ROM_ALLOW_S) -#define TEE_REG_CORE1_UM_L2ROM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_L2ROM_ALLOW_S 3 -/** TEE_REG_CORE1_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_TRACE0_ALLOW (BIT(6)) -#define TEE_REG_CORE1_UM_TRACE0_ALLOW_M (TEE_REG_CORE1_UM_TRACE0_ALLOW_V << TEE_REG_CORE1_UM_TRACE0_ALLOW_S) -#define TEE_REG_CORE1_UM_TRACE0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_TRACE0_ALLOW_S 6 -/** TEE_REG_CORE1_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_TRACE1_ALLOW (BIT(7)) -#define TEE_REG_CORE1_UM_TRACE1_ALLOW_M (TEE_REG_CORE1_UM_TRACE1_ALLOW_V << TEE_REG_CORE1_UM_TRACE1_ALLOW_S) -#define TEE_REG_CORE1_UM_TRACE1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_TRACE1_ALLOW_S 7 -/** TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW (BIT(8)) -#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_M (TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_S) -#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_S 8 -/** TEE_REG_CORE1_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW (BIT(9)) -#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_M (TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_V << TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_S) -#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_S 9 -/** TEE_REG_CORE1_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_TCM_MON_ALLOW (BIT(10)) -#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_M (TEE_REG_CORE1_UM_TCM_MON_ALLOW_V << TEE_REG_CORE1_UM_TCM_MON_ALLOW_S) -#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_S 10 -/** TEE_REG_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_CACHE_ALLOW (BIT(11)) -#define TEE_REG_CORE1_UM_CACHE_ALLOW_M (TEE_REG_CORE1_UM_CACHE_ALLOW_V << TEE_REG_CORE1_UM_CACHE_ALLOW_S) -#define TEE_REG_CORE1_UM_CACHE_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_CACHE_ALLOW_S 11 - -/** TEE_CORE1_UM_PMS_REG1_REG register - * NA - */ -#define TEE_CORE1_UM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x3c) -/** TEE_REG_CORE1_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW (BIT(0)) -#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_M (TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_S 0 -/** TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW (BIT(1)) -#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_M (TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_S 1 -/** TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW (BIT(2)) -#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_M (TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S 2 -/** TEE_REG_CORE1_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW (BIT(3)) -#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_M (TEE_REG_CORE1_UM_HP_GDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_GDMA_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_S 3 -/** TEE_REG_CORE1_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW (BIT(4)) -#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_M (TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_S 4 -/** TEE_REG_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW (BIT(5)) -#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_M (TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_V << TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_S 5 -/** TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW (BIT(6)) -#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_M (TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_S 6 -/** TEE_REG_CORE1_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW (BIT(7)) -#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_M (TEE_REG_CORE1_UM_HP_JPEG_ALLOW_V << TEE_REG_CORE1_UM_HP_JPEG_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_S 7 -/** TEE_REG_CORE1_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_PPA_ALLOW (BIT(8)) -#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_M (TEE_REG_CORE1_UM_HP_PPA_ALLOW_V << TEE_REG_CORE1_UM_HP_PPA_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_S 8 -/** TEE_REG_CORE1_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW (BIT(9)) -#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_M (TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_V << TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_S 9 -/** TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW (BIT(10)) -#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_M (TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_S 10 -/** TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW (BIT(11)) -#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_M (TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_S 11 -/** TEE_REG_CORE1_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW (BIT(12)) -#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_M (TEE_REG_CORE1_UM_HP_FLASH_ALLOW_V << TEE_REG_CORE1_UM_HP_FLASH_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_S 12 -/** TEE_REG_CORE1_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW (BIT(13)) -#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_M (TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_V << TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_S 13 -/** TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW (BIT(14)) -#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_M (TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_S 14 -/** TEE_REG_CORE1_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW (BIT(15)) -#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_M (TEE_REG_CORE1_UM_HP_GMAC_ALLOW_V << TEE_REG_CORE1_UM_HP_GMAC_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_S 15 -/** TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW (BIT(16)) -#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_M (TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_S 16 -/** TEE_REG_CORE1_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_PVT_ALLOW (BIT(17)) -#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_M (TEE_REG_CORE1_UM_HP_PVT_ALLOW_V << TEE_REG_CORE1_UM_HP_PVT_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_S 17 -/** TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW (BIT(18)) -#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_M (TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_S 18 -/** TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW (BIT(19)) -#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_M (TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_S 19 -/** TEE_REG_CORE1_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_ISP_ALLOW (BIT(20)) -#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_M (TEE_REG_CORE1_UM_HP_ISP_ALLOW_V << TEE_REG_CORE1_UM_HP_ISP_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_S 20 -/** TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW (BIT(21)) -#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_M (TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_S 21 -/** TEE_REG_CORE1_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_RMT_ALLOW (BIT(22)) -#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_M (TEE_REG_CORE1_UM_HP_RMT_ALLOW_V << TEE_REG_CORE1_UM_HP_RMT_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_S 22 -/** TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_S 23 -/** TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW (BIT(24)) -#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_M (TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_S 24 -/** TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW (BIT(25)) -#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_M (TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_S 25 -/** TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW (BIT(26)) -#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_M (TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S) -#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S 26 -/** TEE_REG_CORE1_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW (BIT(27)) -#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_M (TEE_REG_CORE1_UM_DMA_PMS_ALLOW_V << TEE_REG_CORE1_UM_DMA_PMS_ALLOW_S) -#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_S 27 -/** TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW (BIT(28)) -#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_M (TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_S 28 -/** TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW (BIT(29)) -#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_M (TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_S) -#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_S 29 - -/** TEE_CORE1_UM_PMS_REG2_REG register - * NA - */ -#define TEE_CORE1_UM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x40) -/** TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW (BIT(0)) -#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_M (TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_S 0 -/** TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW (BIT(1)) -#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_M (TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_S 1 -/** TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW (BIT(2)) -#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_M (TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S 2 -/** TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW (BIT(3)) -#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_M (TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S 3 -/** TEE_REG_CORE1_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW (BIT(4)) -#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_M (TEE_REG_CORE1_UM_HP_I2C0_ALLOW_V << TEE_REG_CORE1_UM_HP_I2C0_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_S 4 -/** TEE_REG_CORE1_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW (BIT(5)) -#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_M (TEE_REG_CORE1_UM_HP_I2C1_ALLOW_V << TEE_REG_CORE1_UM_HP_I2C1_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_S 5 -/** TEE_REG_CORE1_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW (BIT(6)) -#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_M (TEE_REG_CORE1_UM_HP_I2S0_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S0_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_S 6 -/** TEE_REG_CORE1_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW (BIT(7)) -#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_M (TEE_REG_CORE1_UM_HP_I2S1_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S1_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_S 7 -/** TEE_REG_CORE1_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW (BIT(8)) -#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_M (TEE_REG_CORE1_UM_HP_I2S2_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S2_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_S 8 -/** TEE_REG_CORE1_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW (BIT(9)) -#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_M (TEE_REG_CORE1_UM_HP_PCNT_ALLOW_V << TEE_REG_CORE1_UM_HP_PCNT_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_S 9 -/** TEE_REG_CORE1_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_UART0_ALLOW (BIT(10)) -#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_M (TEE_REG_CORE1_UM_HP_UART0_ALLOW_V << TEE_REG_CORE1_UM_HP_UART0_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_S 10 -/** TEE_REG_CORE1_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_UART1_ALLOW (BIT(11)) -#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_M (TEE_REG_CORE1_UM_HP_UART1_ALLOW_V << TEE_REG_CORE1_UM_HP_UART1_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_S 11 -/** TEE_REG_CORE1_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_UART2_ALLOW (BIT(12)) -#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_M (TEE_REG_CORE1_UM_HP_UART2_ALLOW_V << TEE_REG_CORE1_UM_HP_UART2_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_S 12 -/** TEE_REG_CORE1_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_UART3_ALLOW (BIT(13)) -#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_M (TEE_REG_CORE1_UM_HP_UART3_ALLOW_V << TEE_REG_CORE1_UM_HP_UART3_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_S 13 -/** TEE_REG_CORE1_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_UART4_ALLOW (BIT(14)) -#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_M (TEE_REG_CORE1_UM_HP_UART4_ALLOW_V << TEE_REG_CORE1_UM_HP_UART4_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_S 14 -/** TEE_REG_CORE1_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW (BIT(15)) -#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_M (TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_V << TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_S 15 -/** TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW (BIT(16)) -#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_M (TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_S 16 -/** TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW (BIT(17)) -#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_M (TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_S 17 -/** TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW (BIT(18)) -#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_M (TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_S 18 -/** TEE_REG_CORE1_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW (BIT(19)) -#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_M (TEE_REG_CORE1_UM_HP_LEDC_ALLOW_V << TEE_REG_CORE1_UM_HP_LEDC_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_S 19 -/** TEE_REG_CORE1_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_ETM_ALLOW (BIT(21)) -#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_M (TEE_REG_CORE1_UM_HP_ETM_ALLOW_V << TEE_REG_CORE1_UM_HP_ETM_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_S 21 -/** TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW (BIT(22)) -#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_M (TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_S 22 -/** TEE_REG_CORE1_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW (BIT(23)) -#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_M (TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_S 23 -/** TEE_REG_CORE1_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW (BIT(24)) -#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_M (TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_S 24 -/** TEE_REG_CORE1_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW (BIT(25)) -#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_M (TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_S 25 -/** TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW (BIT(26)) -#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_M (TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_S 26 -/** TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW (BIT(27)) -#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_M (TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_S 27 -/** TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW (BIT(28)) -#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_M (TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_S 28 -/** TEE_REG_CORE1_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_ADC_ALLOW (BIT(30)) -#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_M (TEE_REG_CORE1_UM_HP_ADC_ALLOW_V << TEE_REG_CORE1_UM_HP_ADC_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_S 30 -/** TEE_REG_CORE1_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW (BIT(31)) -#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_M (TEE_REG_CORE1_UM_HP_UHCI_ALLOW_V << TEE_REG_CORE1_UM_HP_UHCI_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_S 31 - -/** TEE_CORE1_UM_PMS_REG3_REG register - * NA - */ -#define TEE_CORE1_UM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x44) -/** TEE_REG_CORE1_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW (BIT(0)) -#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_M (TEE_REG_CORE1_UM_HP_GPIO_ALLOW_V << TEE_REG_CORE1_UM_HP_GPIO_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_S 0 -/** TEE_REG_CORE1_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW (BIT(1)) -#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_M (TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_V << TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_S 1 -/** TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW (BIT(2)) -#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_M (TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_S 2 -/** TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW (BIT(3)) -#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_M (TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_S 3 -/** TEE_REG_CORE1_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW (BIT(4)) -#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_M (TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_V << TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_S 4 - -/** TEE_REGDMA_PERI_PMS_REG register - * NA - */ -#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x48) -/** TEE_REG_REGDMA_PERI_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_REGDMA_PERI_ALLOW (BIT(0)) -#define TEE_REG_REGDMA_PERI_ALLOW_M (TEE_REG_REGDMA_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_ALLOW_S) -#define TEE_REG_REGDMA_PERI_ALLOW_V 0x00000001U -#define TEE_REG_REGDMA_PERI_ALLOW_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h index da2f6df98b2..6cef945ddff 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { * Version control register */ #define PMS_HP_PERI_PMS_DATE_REG (DR_REG_HP_PERI_PMS_BASE + 0x0) -/** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537; +/** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2363943; * Version control register. */ #define PMS_HP_PERI_PMS_DATE 0xFFFFFFFFU @@ -179,6 +179,15 @@ extern "C" { #define PMS_CORE0_MM_HP_GDMA_ALLOW_M (PMS_CORE0_MM_HP_GDMA_ALLOW_V << PMS_CORE0_MM_HP_GDMA_ALLOW_S) #define PMS_CORE0_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE0_MM_HP_GDMA_ALLOW_S 3 +/** PMS_CORE0_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPU0 in machine mode has permission to access HP REGDMA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_CORE0_MM_HP_REGDMA_ALLOW (BIT(4)) +#define PMS_CORE0_MM_HP_REGDMA_ALLOW_M (PMS_CORE0_MM_HP_REGDMA_ALLOW_V << PMS_CORE0_MM_HP_REGDMA_ALLOW_S) +#define PMS_CORE0_MM_HP_REGDMA_ALLOW_V 0x00000001U +#define PMS_CORE0_MM_HP_REGDMA_ALLOW_S 4 /** PMS_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access HP SDMMC. * 0: Not allowed @@ -406,6 +415,15 @@ extern "C" { #define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_M (PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_V << PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_S) #define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U #define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_S 28 +/** PMS_CORE0_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; + * Configures whether HP CPU0 in machine mode has permission to access AXI PERFMON. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_CORE0_MM_AXI_PERF_MON_ALLOW (BIT(29)) +#define PMS_CORE0_MM_AXI_PERF_MON_ALLOW_M (PMS_CORE0_MM_AXI_PERF_MON_ALLOW_V << PMS_CORE0_MM_AXI_PERF_MON_ALLOW_S) +#define PMS_CORE0_MM_AXI_PERF_MON_ALLOW_V 0x00000001U +#define PMS_CORE0_MM_AXI_PERF_MON_ALLOW_S 29 /** PMS_CORE0_MM_HP_PERI_PMS_REG2_REG register * Permission control register2 for HP CPU0 in machine mode @@ -877,13 +895,20 @@ extern "C" { * Configures whether HP CPU0 in user mode has permission to access HP DW-GDMA. * 0: Not allowed * 1: Allowed - * 0: Not allowed - * 1: Allowed */ #define PMS_CORE0_UM_HP_GDMA_ALLOW (BIT(3)) #define PMS_CORE0_UM_HP_GDMA_ALLOW_M (PMS_CORE0_UM_HP_GDMA_ALLOW_V << PMS_CORE0_UM_HP_GDMA_ALLOW_S) #define PMS_CORE0_UM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE0_UM_HP_GDMA_ALLOW_S 3 +/** PMS_CORE0_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPU0 in user mode has permission to access HP REGDMA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_CORE0_UM_HP_REGDMA_ALLOW (BIT(4)) +#define PMS_CORE0_UM_HP_REGDMA_ALLOW_M (PMS_CORE0_UM_HP_REGDMA_ALLOW_V << PMS_CORE0_UM_HP_REGDMA_ALLOW_S) +#define PMS_CORE0_UM_HP_REGDMA_ALLOW_V 0x00000001U +#define PMS_CORE0_UM_HP_REGDMA_ALLOW_S 4 /** PMS_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; * Configures whether HP CPU0 in user mode has permission to access HP SDMMC. * 0: Not allowed @@ -1104,6 +1129,15 @@ extern "C" { #define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_M (PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_V << PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_S) #define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_V 0x00000001U #define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_S 28 +/** PMS_CORE0_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; + * Configures whether HP CPU0 in user mode has permission to access AXI PERFMON. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_CORE0_UM_AXI_PERF_MON_ALLOW (BIT(29)) +#define PMS_CORE0_UM_AXI_PERF_MON_ALLOW_M (PMS_CORE0_UM_AXI_PERF_MON_ALLOW_V << PMS_CORE0_UM_AXI_PERF_MON_ALLOW_S) +#define PMS_CORE0_UM_AXI_PERF_MON_ALLOW_V 0x00000001U +#define PMS_CORE0_UM_AXI_PERF_MON_ALLOW_S 29 /** PMS_CORE0_UM_HP_PERI_PMS_REG2_REG register * Permission control register2 for HP CPU0 in user mode @@ -1578,6 +1612,15 @@ extern "C" { #define PMS_CORE1_MM_HP_GDMA_ALLOW_M (PMS_CORE1_MM_HP_GDMA_ALLOW_V << PMS_CORE1_MM_HP_GDMA_ALLOW_S) #define PMS_CORE1_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE1_MM_HP_GDMA_ALLOW_S 3 +/** PMS_CORE1_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPU1 in machine mode has permission to access HP REGDMA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_CORE1_MM_HP_REGDMA_ALLOW (BIT(4)) +#define PMS_CORE1_MM_HP_REGDMA_ALLOW_M (PMS_CORE1_MM_HP_REGDMA_ALLOW_V << PMS_CORE1_MM_HP_REGDMA_ALLOW_S) +#define PMS_CORE1_MM_HP_REGDMA_ALLOW_V 0x00000001U +#define PMS_CORE1_MM_HP_REGDMA_ALLOW_S 4 /** PMS_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access HP SDMMC. * 0: Not allowed @@ -1805,6 +1848,15 @@ extern "C" { #define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_M (PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_V << PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_S) #define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U #define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_S 28 +/** PMS_CORE1_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; + * Configures whether HP CPU1 in machine mode has permission to access AXI PERFMON. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_CORE1_MM_AXI_PERF_MON_ALLOW (BIT(29)) +#define PMS_CORE1_MM_AXI_PERF_MON_ALLOW_M (PMS_CORE1_MM_AXI_PERF_MON_ALLOW_V << PMS_CORE1_MM_AXI_PERF_MON_ALLOW_S) +#define PMS_CORE1_MM_AXI_PERF_MON_ALLOW_V 0x00000001U +#define PMS_CORE1_MM_AXI_PERF_MON_ALLOW_S 29 /** PMS_CORE1_MM_HP_PERI_PMS_REG2_REG register * Permission control register2 for HP CPU1 in machine mode @@ -2276,13 +2328,20 @@ extern "C" { * Configures whether HP CPU1 in user mode has permission to access HP DW-GDMA. * 0: Not allowed * 1: Allowed - * 0: Not allowed - * 1: Allowed */ #define PMS_CORE1_UM_HP_GDMA_ALLOW (BIT(3)) #define PMS_CORE1_UM_HP_GDMA_ALLOW_M (PMS_CORE1_UM_HP_GDMA_ALLOW_V << PMS_CORE1_UM_HP_GDMA_ALLOW_S) #define PMS_CORE1_UM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_GDMA_ALLOW_S 3 +/** PMS_CORE1_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPU1 in user mode has permission to access HP REGDMA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_CORE1_UM_HP_REGDMA_ALLOW (BIT(4)) +#define PMS_CORE1_UM_HP_REGDMA_ALLOW_M (PMS_CORE1_UM_HP_REGDMA_ALLOW_V << PMS_CORE1_UM_HP_REGDMA_ALLOW_S) +#define PMS_CORE1_UM_HP_REGDMA_ALLOW_V 0x00000001U +#define PMS_CORE1_UM_HP_REGDMA_ALLOW_S 4 /** PMS_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; * Configures whether HP CPU1 in user mode has permission to access HP SDMMC. * 0: Not allowed @@ -2503,6 +2562,15 @@ extern "C" { #define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_M (PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_V << PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_S) #define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_S 28 +/** PMS_CORE1_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; + * Configures whether HP CPU1 in user mode has permission to access AXI PERFMON. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_CORE1_UM_AXI_PERF_MON_ALLOW (BIT(29)) +#define PMS_CORE1_UM_AXI_PERF_MON_ALLOW_M (PMS_CORE1_UM_AXI_PERF_MON_ALLOW_V << PMS_CORE1_UM_AXI_PERF_MON_ALLOW_S) +#define PMS_CORE1_UM_AXI_PERF_MON_ALLOW_V 0x00000001U +#define PMS_CORE1_UM_AXI_PERF_MON_ALLOW_S 29 /** PMS_CORE1_UM_HP_PERI_PMS_REG2_REG register * Permission control register2 for HP CPU1 in user mode @@ -2834,6 +2902,20 @@ extern "C" { #define PMS_CORE1_UM_HP_CLKRST_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_CLKRST_ALLOW_S 4 +/** PMS_REGDMA_HP_PERI_PMS_REG register + * HP Peripheral Permission register for REGDMA + */ +#define PMS_REGDMA_HP_PERI_PMS_REG (DR_REG_HP_PERI_PMS_BASE + 0x48) +/** PMS_REGDMA_PERI_HP_PERI_ALLOW : R/W; bitpos: [0]; default: 1; + * Configures whether REGDMA has permission to access all HP peripherals. + * 0: Not allowed + * 1: Allow + */ +#define PMS_REGDMA_PERI_HP_PERI_ALLOW (BIT(0)) +#define PMS_REGDMA_PERI_HP_PERI_ALLOW_M (PMS_REGDMA_PERI_HP_PERI_ALLOW_V << PMS_REGDMA_PERI_HP_PERI_ALLOW_S) +#define PMS_REGDMA_PERI_HP_PERI_ALLOW_V 0x00000001U +#define PMS_REGDMA_PERI_HP_PERI_ALLOW_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_struct.h index faad017de08..1a96375db76 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_struct.h @@ -10,1479 +10,1102 @@ extern "C" { #endif -/** Group: TEE PMS DATE REG */ -/** Type of pms_date register - * NA +/** Group: TEE HP Peripheral Version Control Registers */ +/** Type of hp_peri_pms_date register + * Version control register */ typedef union { struct { - /** tee_date : R/W; bitpos: [31:0]; default: 2363943; - * NA + /** hp_peri_pms_date : R/W; bitpos: [31:0]; default: 2363943; + * Version control register. */ - uint32_t tee_date:32; + uint32_t hp_peri_pms_date:32; }; uint32_t val; -} tee_pms_date_reg_t; +} pms_hp_peri_pms_date_reg_t; -/** Group: TEE PMS CLK EN REG */ -/** Type of pms_clk_en register - * NA +/** Group: Clock Gating Registers */ +/** Type of hp_peri_pms_clk_en register + * Clock gating register */ typedef union { struct { - /** reg_clk_en : R/W; bitpos: [0]; default: 1; - * NA + /** hp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ - uint32_t reg_clk_en:1; + uint32_t hp_peri_pms_clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} tee_pms_clk_en_reg_t; +} pms_hp_peri_pms_clk_en_reg_t; -/** Group: TEE CORE0 MM PMS REG0 REG */ -/** Type of core0_mm_pms_reg0 register - * NA +/** Group: HP CPU Permission Control Registers */ +/** Type of coren_mm_hp_peri_pms_reg0 register + * Permission control register0 for HP CPUn in machine mode */ typedef union { struct { - /** reg_core0_mm_psram_allow : R/W; bitpos: [0]; default: 1; - * NA + /** coren_mm_psram_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access external RAM + * without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_psram_allow:1; - /** reg_core0_mm_flash_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t coren_mm_psram_allow:1; + /** coren_mm_flash_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access external flash + * without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_flash_allow:1; - /** reg_core0_mm_l2mem_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t coren_mm_flash_allow:1; + /** coren_mm_l2mem_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP L2MEM + * without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_l2mem_allow:1; - /** reg_core0_mm_l2rom_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t coren_mm_l2mem_allow:1; + /** coren_mm_l2rom_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP ROM without + * going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_l2rom_allow:1; + uint32_t coren_mm_l2rom_allow:1; uint32_t reserved_4:2; - /** reg_core0_mm_trace0_allow : R/W; bitpos: [6]; default: 1; - * NA + /** coren_mm_trace0_allow : R/W; bitpos: [6]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access TRACE0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_trace0_allow:1; - /** reg_core0_mm_trace1_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t coren_mm_trace0_allow:1; + /** coren_mm_trace1_allow : R/W; bitpos: [7]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access TRACE1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_trace1_allow:1; - /** reg_core0_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t coren_mm_trace1_allow:1; + /** coren_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access CPU bus + * monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_cpu_bus_mon_allow:1; - /** reg_core0_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t coren_mm_cpu_bus_mon_allow:1; + /** coren_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access L2MEM monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_l2mem_mon_allow:1; - /** reg_core0_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t coren_mm_l2mem_mon_allow:1; + /** coren_mm_spm_mon_allow : R/W; bitpos: [10]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access SPM monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_tcm_mon_allow:1; - /** reg_core0_mm_cache_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t coren_mm_spm_mon_allow:1; + /** coren_mm_cache_allow : R/W; bitpos: [11]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_cache_allow:1; + uint32_t coren_mm_cache_allow:1; uint32_t reserved_12:20; }; uint32_t val; -} tee_core0_mm_pms_reg0_reg_t; +} pms_coren_mm_hp_peri_pms_reg0_reg_t; - -/** Group: TEE CORE0 MM PMS REG1 REG */ -/** Type of core0_mm_pms_reg1 register - * NA +/** Type of coren_mm_hp_peri_pms_reg1 register + * Permission control register1 for HP CPUn in machine mode */ typedef union { struct { - /** reg_core0_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; - * NA + /** coren_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP high-speed + * USB 2.0 OTG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_usbotg_allow:1; - /** reg_core0_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t coren_mm_hp_usbotg_allow:1; + /** coren_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP full-speed + * USB 2.0 OTG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_usbotg11_allow:1; - /** reg_core0_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t coren_mm_hp_usbotg11_allow:1; + /** coren_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP full-speed + * USB 2.0 OTG's wrap. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_usbotg11_wrap_allow:1; - /** reg_core0_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t coren_mm_hp_usbotg11_wrap_allow:1; + /** coren_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP DW-GDMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_gdma_allow:1; - /** reg_core0_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t coren_mm_hp_gdma_allow:1; + uint32_t reserved_4:1; + /** coren_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP SDMMC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_regdma_allow:1; - /** reg_core0_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t coren_mm_hp_sdmmc_allow:1; + /** coren_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access GDMA-AHB. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_sdmmc_allow:1; - /** reg_core0_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t coren_mm_hp_ahb_pdma_allow:1; + /** coren_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP JPEG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_ahb_pdma_allow:1; - /** reg_core0_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t coren_mm_hp_jpeg_allow:1; + /** coren_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP PPA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_jpeg_allow:1; - /** reg_core0_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t coren_mm_hp_ppa_allow:1; + /** coren_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP 2D-DMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_ppa_allow:1; - /** reg_core0_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t coren_mm_hp_dma2d_allow:1; + /** coren_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP key manager. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_dma2d_allow:1; - /** reg_core0_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t coren_mm_hp_key_manager_allow:1; + /** coren_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP GDMA-AXI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_key_manager_allow:1; - /** reg_core0_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t coren_mm_hp_axi_pdma_allow:1; + /** coren_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP flash MSPI + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_axi_pdma_allow:1; - /** reg_core0_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t coren_mm_hp_flash_allow:1; + /** coren_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP PSRAM MSPI + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_flash_allow:1; - /** reg_core0_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t coren_mm_hp_psram_allow:1; + /** coren_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP CRYPTO + * (including AES/SHA/RSA/HMAC Accelerators). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_psram_allow:1; - /** reg_core0_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t coren_mm_hp_crypto_allow:1; + /** coren_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP EMAC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_crypto_allow:1; - /** reg_core0_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t coren_mm_hp_gmac_allow:1; + /** coren_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP high-speed + * USB 2.0 OTG PHY. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_gmac_allow:1; - /** reg_core0_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t coren_mm_hp_usb_phy_allow:1; + /** coren_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP PVT. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_core0_mm_hp_usb_phy_allow:1; - /** reg_core0_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t coren_mm_hp_pvt_allow:1; + /** coren_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP MIPI CSI + * host. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_pvt_allow:1; - /** reg_core0_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t coren_mm_hp_csi_host_allow:1; + /** coren_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP MIPI DSI + * host. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_csi_host_allow:1; - /** reg_core0_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t coren_mm_hp_dsi_host_allow:1; + /** coren_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP ISP (Image + * Signal Processor). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_dsi_host_allow:1; - /** reg_core0_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1; - * NA + uint32_t coren_mm_hp_isp_allow:1; + /** coren_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP H264 + * Encoder. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_isp_allow:1; - /** reg_core0_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; - * NA + uint32_t coren_mm_hp_h264_core_allow:1; + /** coren_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP RMT. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_h264_core_allow:1; - /** reg_core0_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t coren_mm_hp_rmt_allow:1; + /** coren_mm_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP bit + * scrambler. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_rmt_allow:1; - /** reg_core0_mm_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t coren_mm_hp_bitscrambler_allow:1; + /** coren_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP AXI ICM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_bitscrambler_allow:1; - /** reg_core0_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t coren_mm_hp_axi_icm_allow:1; + /** coren_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access + * HP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_axi_icm_allow:1; - /** reg_core0_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; - * NA + uint32_t coren_mm_hp_peri_pms_allow:1; + /** coren_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access + * LP2HP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_peri_pms_allow:1; - /** reg_core0_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; - * NA + uint32_t coren_mm_lp2hp_peri_pms_allow:1; + /** coren_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP_DMA_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_lp2hp_peri_pms_allow:1; - /** reg_core0_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1; - * NA + uint32_t coren_mm_dma_pms_allow:1; + /** coren_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access 2D-DMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_dma_pms_allow:1; - /** reg_core0_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; - * NA + uint32_t coren_mm_hp_h264_dma2d_allow:1; + /** coren_mm_hp_h264_dma2d_allow : R/W; bitpos: [29]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access 2D-DMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_h264_dma2d_allow:1; - /** reg_core0_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t reg_core0_mm_axi_perf_mon_allow:1; + uint32_t coren_mm_hp_axi_perf_mon_allow:1; uint32_t reserved_30:2; }; uint32_t val; -} tee_core0_mm_pms_reg1_reg_t; +} pms_coren_mm_hp_peri_pms_reg1_reg_t; - -/** Group: TEE CORE0 MM PMS REG2 REG */ -/** Type of core0_mm_pms_reg2 register - * NA +/** Type of coren_mm_hp_peri_pms_reg2 register + * Permission control register2 for HP CPUn in machine mode */ typedef union { struct { - /** reg_core0_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; - * NA + /** coren_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP MCPWM0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_mcpwm0_allow:1; - /** reg_core0_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t coren_mm_hp_mcpwm0_allow:1; + /** coren_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP MCPWM1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_mcpwm1_allow:1; - /** reg_core0_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t coren_mm_hp_mcpwm1_allow:1; + /** coren_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP timer + * group0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_timer_group0_allow:1; - /** reg_core0_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t coren_mm_hp_timer_group0_allow:1; + /** coren_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP timer group1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_timer_group1_allow:1; - /** reg_core0_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t coren_mm_hp_timer_group1_allow:1; + /** coren_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP I2C0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_i2c0_allow:1; - /** reg_core0_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t coren_mm_hp_i2c0_allow:1; + /** coren_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP I2C1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_i2c1_allow:1; - /** reg_core0_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t coren_mm_hp_i2c1_allow:1; + /** coren_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP I2S0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_i2s0_allow:1; - /** reg_core0_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t coren_mm_hp_i2s0_allow:1; + /** coren_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP I2S1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_i2s1_allow:1; - /** reg_core0_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t coren_mm_hp_i2s1_allow:1; + /** coren_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP I2S2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_i2s2_allow:1; - /** reg_core0_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t coren_mm_hp_i2s2_allow:1; + /** coren_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP PCNT. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_pcnt_allow:1; - /** reg_core0_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t coren_mm_hp_pcnt_allow:1; + /** coren_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP UART0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_uart0_allow:1; - /** reg_core0_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t coren_mm_hp_uart0_allow:1; + /** coren_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP UART1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_uart1_allow:1; - /** reg_core0_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t coren_mm_hp_uart1_allow:1; + /** coren_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP UART2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_uart2_allow:1; - /** reg_core0_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t coren_mm_hp_uart2_allow:1; + /** coren_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP UART3. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_uart3_allow:1; - /** reg_core0_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t coren_mm_hp_uart3_allow:1; + /** coren_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP UART4. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_uart4_allow:1; - /** reg_core0_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t coren_mm_hp_uart4_allow:1; + /** coren_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP PARLIO. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_parlio_allow:1; - /** reg_core0_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t coren_mm_hp_parlio_allow:1; + /** coren_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP GP-SPI2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_gpspi2_allow:1; - /** reg_core0_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t coren_mm_hp_gpspi2_allow:1; + /** coren_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP GP-SPI3. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_gpspi3_allow:1; - /** reg_core0_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t coren_mm_hp_gpspi3_allow:1; + /** coren_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP USB + * Serial/JTAG Controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_usbdevice_allow:1; - /** reg_core0_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t coren_mm_hp_usbdevice_allow:1; + /** coren_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP LEDC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_ledc_allow:1; + uint32_t coren_mm_hp_ledc_allow:1; uint32_t reserved_20:1; - /** reg_core0_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1; - * NA + /** coren_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP ETM (Event + * Task Matrix). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_etm_allow:1; - /** reg_core0_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t coren_mm_hp_etm_allow:1; + /** coren_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP interrupt + * matrix. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_intrmtx_allow:1; - /** reg_core0_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t coren_mm_hp_intrmtx_allow:1; + /** coren_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP TWAI0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_twai0_allow:1; - /** reg_core0_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t coren_mm_hp_twai0_allow:1; + /** coren_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP TWAI1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_twai1_allow:1; - /** reg_core0_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1; - * NA + uint32_t coren_mm_hp_twai1_allow:1; + /** coren_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP TWAI2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_twai2_allow:1; - /** reg_core0_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; - * NA + uint32_t coren_mm_hp_twai2_allow:1; + /** coren_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP I3C master + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_i3c_mst_allow:1; - /** reg_core0_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; - * NA + uint32_t coren_mm_hp_i3c_mst_allow:1; + /** coren_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP I3C slave + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_i3c_slv_allow:1; - /** reg_core0_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; - * NA + uint32_t coren_mm_hp_i3c_slv_allow:1; + /** coren_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP LCD_CAM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_lcdcam_allow:1; + uint32_t coren_mm_hp_lcdcam_allow:1; uint32_t reserved_29:1; - /** reg_core0_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1; - * NA + /** coren_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP ADC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_adc_allow:1; - /** reg_core0_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1; - * NA + uint32_t coren_mm_hp_adc_allow:1; + /** coren_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP UHCI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_uhci_allow:1; + uint32_t coren_mm_hp_uhci_allow:1; }; uint32_t val; -} tee_core0_mm_pms_reg2_reg_t; +} pms_coren_mm_hp_peri_pms_reg2_reg_t; - -/** Group: TEE CORE0 MM PMS REG3 REG */ -/** Type of core0_mm_pms_reg3 register - * NA +/** Type of coren_mm_hp_peri_pms_reg3 register + * Permission control register3 for HP CPUn in machine mode */ typedef union { struct { - /** reg_core0_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1; - * NA + /** coren_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP GPIO Matrix. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_gpio_allow:1; - /** reg_core0_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t coren_mm_hp_gpio_allow:1; + /** coren_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP IO MUX. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_iomux_allow:1; - /** reg_core0_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t coren_mm_hp_iomux_allow:1; + /** coren_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP system + * timer. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_systimer_allow:1; - /** reg_core0_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t coren_mm_hp_systimer_allow:1; + /** coren_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP system + * register. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_sys_reg_allow:1; - /** reg_core0_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t coren_mm_hp_sys_reg_allow:1; + /** coren_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access HP_SYS_CLKRST. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_mm_hp_clkrst_allow:1; + uint32_t coren_mm_hp_clkrst_allow:1; uint32_t reserved_5:27; }; uint32_t val; -} tee_core0_mm_pms_reg3_reg_t; +} pms_coren_mm_hp_peri_pms_reg3_reg_t; - -/** Group: TEE CORE0 UM PMS REG0 REG */ -/** Type of core0_um_pms_reg0 register - * NA +/** Type of coren_um_hp_peri_pms_reg0 register + * Permission control register0 for HP CPUn in user mode */ typedef union { struct { - /** reg_core0_um_psram_allow : R/W; bitpos: [0]; default: 1; - * NA + /** coren_um_psram_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in user mode has permission to access external RAM + * without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_psram_allow:1; - /** reg_core0_um_flash_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t coren_um_psram_allow:1; + /** coren_um_flash_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in user mode has permission to access external flash + * without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_flash_allow:1; - /** reg_core0_um_l2mem_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t coren_um_flash_allow:1; + /** coren_um_l2mem_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP L2MEM without + * going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_l2mem_allow:1; - /** reg_core0_um_l2rom_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t coren_um_l2mem_allow:1; + /** coren_um_l2rom_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP ROM without + * going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_l2rom_allow:1; + uint32_t coren_um_l2rom_allow:1; uint32_t reserved_4:2; - /** reg_core0_um_trace0_allow : R/W; bitpos: [6]; default: 1; - * NA + /** coren_um_trace0_allow : R/W; bitpos: [6]; default: 1; + * Configures whether HP CPUn in user mode has permission to access TRACE0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_trace0_allow:1; - /** reg_core0_um_trace1_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t coren_um_trace0_allow:1; + /** coren_um_trace1_allow : R/W; bitpos: [7]; default: 1; + * Configures whether HP CPUn in user mode has permission to access TRACE1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_trace1_allow:1; - /** reg_core0_um_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t coren_um_trace1_allow:1; + /** coren_um_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; + * Configures whether HP CPUn in user mode has permission to access CPU bus monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_cpu_bus_mon_allow:1; - /** reg_core0_um_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t coren_um_cpu_bus_mon_allow:1; + /** coren_um_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; + * Configures whether HP CPUn in user mode has permission to access L2MEM monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_l2mem_mon_allow:1; - /** reg_core0_um_tcm_mon_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t coren_um_l2mem_mon_allow:1; + /** coren_um_spm_mon_allow : R/W; bitpos: [10]; default: 1; + * Configures whether HP CPUn in user mode has permission to access SPM monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_tcm_mon_allow:1; - /** reg_core0_um_cache_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t coren_um_spm_mon_allow:1; + /** coren_um_cache_allow : R/W; bitpos: [11]; default: 1; + * Configures whether HP CPUn in user mode has permission to access cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_cache_allow:1; + uint32_t coren_um_cache_allow:1; uint32_t reserved_12:20; }; uint32_t val; -} tee_core0_um_pms_reg0_reg_t; +} pms_coren_um_hp_peri_pms_reg0_reg_t; - -/** Group: TEE CORE0 UM PMS REG1 REG */ -/** Type of core0_um_pms_reg1 register - * NA +/** Type of coren_um_hp_peri_pms_reg1 register + * Permission control register1 for HP CPUn in user mode */ typedef union { struct { - /** reg_core0_um_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; - * NA + /** coren_um_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP high-speed USB + * 2.0 OTG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_usbotg_allow:1; - /** reg_core0_um_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t coren_um_hp_usbotg_allow:1; + /** coren_um_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP full-speed USB + * 2.0 OTG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_usbotg11_allow:1; - /** reg_core0_um_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t coren_um_hp_usbotg11_allow:1; + /** coren_um_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP full-speed USB + * 2.0 OTG's wrap. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_usbotg11_wrap_allow:1; - /** reg_core0_um_hp_gdma_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t coren_um_hp_usbotg11_wrap_allow:1; + /** coren_um_hp_gdma_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP DW-GDMA. + * 0: Not allowed + * 1: Allowed + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_gdma_allow:1; - /** reg_core0_um_hp_regdma_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t coren_um_hp_gdma_allow:1; + uint32_t reserved_4:1; + /** coren_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP SDMMC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_regdma_allow:1; - /** reg_core0_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t coren_um_hp_sdmmc_allow:1; + /** coren_um_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; + * Configures whether HP CPUn in user mode has permission to access GDMA-AHB. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_sdmmc_allow:1; - /** reg_core0_um_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t coren_um_hp_ahb_pdma_allow:1; + /** coren_um_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP JPEG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_ahb_pdma_allow:1; - /** reg_core0_um_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t coren_um_hp_jpeg_allow:1; + /** coren_um_hp_ppa_allow : R/W; bitpos: [8]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP PPA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_jpeg_allow:1; - /** reg_core0_um_hp_ppa_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t coren_um_hp_ppa_allow:1; + /** coren_um_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP 2D-DMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_ppa_allow:1; - /** reg_core0_um_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t coren_um_hp_dma2d_allow:1; + /** coren_um_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP key manager. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_dma2d_allow:1; - /** reg_core0_um_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t coren_um_hp_key_manager_allow:1; + /** coren_um_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP GDMA-AXI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_key_manager_allow:1; - /** reg_core0_um_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t coren_um_hp_axi_pdma_allow:1; + /** coren_um_hp_flash_allow : R/W; bitpos: [12]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP flash MSPI + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_axi_pdma_allow:1; - /** reg_core0_um_hp_flash_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t coren_um_hp_flash_allow:1; + /** coren_um_hp_psram_allow : R/W; bitpos: [13]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP PSRAM MSPI + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_flash_allow:1; - /** reg_core0_um_hp_psram_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t coren_um_hp_psram_allow:1; + /** coren_um_hp_crypto_allow : R/W; bitpos: [14]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP CRYPTO. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_psram_allow:1; - /** reg_core0_um_hp_crypto_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t coren_um_hp_crypto_allow:1; + /** coren_um_hp_gmac_allow : R/W; bitpos: [15]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP EMAC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_crypto_allow:1; - /** reg_core0_um_hp_gmac_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t coren_um_hp_gmac_allow:1; + /** coren_um_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP high-speed USB + * 2.0 OTG PHY. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_gmac_allow:1; - /** reg_core0_um_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t coren_um_hp_usb_phy_allow:1; + /** coren_um_hp_pvt_allow : R/W; bitpos: [17]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP PVT. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_core0_um_hp_usb_phy_allow:1; - /** reg_core0_um_hp_pvt_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t coren_um_hp_pvt_allow:1; + /** coren_um_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP MIPI CSI host. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_pvt_allow:1; - /** reg_core0_um_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t coren_um_hp_csi_host_allow:1; + /** coren_um_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP MIPI DSI host. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_csi_host_allow:1; - /** reg_core0_um_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t coren_um_hp_dsi_host_allow:1; + /** coren_um_hp_isp_allow : R/W; bitpos: [20]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP ISP. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_dsi_host_allow:1; - /** reg_core0_um_hp_isp_allow : R/W; bitpos: [20]; default: 1; - * NA + uint32_t coren_um_hp_isp_allow:1; + /** coren_um_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP H264 Encoder. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_isp_allow:1; - /** reg_core0_um_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; - * NA + uint32_t coren_um_hp_h264_core_allow:1; + /** coren_um_hp_rmt_allow : R/W; bitpos: [22]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP RMT. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_h264_core_allow:1; - /** reg_core0_um_hp_rmt_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t coren_um_hp_rmt_allow:1; + /** coren_um_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP bit scrambler. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_rmt_allow:1; - /** reg_core0_um_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t coren_um_hp_bitscrambler_allow:1; + /** coren_um_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP AXI ICM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_bitscrambler_allow:1; - /** reg_core0_um_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t coren_um_hp_axi_icm_allow:1; + /** coren_um_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_axi_icm_allow:1; - /** reg_core0_um_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; - * NA + uint32_t coren_um_hp_peri_pms_allow:1; + /** coren_um_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; + * Configures whether HP CPUn in user mode has permission to access + * LP2HP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_peri_pms_allow:1; - /** reg_core0_um_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; - * NA + uint32_t coren_um_lp2hp_peri_pms_allow:1; + /** coren_um_dma_pms_allow : R/W; bitpos: [27]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP_DMA_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_lp2hp_peri_pms_allow:1; - /** reg_core0_um_dma_pms_allow : R/W; bitpos: [27]; default: 1; - * NA + uint32_t coren_um_dma_pms_allow:1; + /** coren_um_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; + * Configures whether HP CPUn in user mode has permission to access 2D-DMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_dma_pms_allow:1; - /** reg_core0_um_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; - * NA + uint32_t coren_um_hp_h264_dma2d_allow:1; + /** coren_um_hp_h264_dma2d_allow : R/W; bitpos: [29]; default: 1; + * Configures whether HP CPUn in machine mode has permission to access 2D-DMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_h264_dma2d_allow:1; - /** reg_core0_um_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t reg_core0_um_axi_perf_mon_allow:1; + uint32_t coren_um_hp_axi_perf_mon_allow:1; uint32_t reserved_30:2; }; uint32_t val; -} tee_core0_um_pms_reg1_reg_t; +} pms_coren_um_hp_peri_pms_reg1_reg_t; - -/** Group: TEE CORE0 UM PMS REG2 REG */ -/** Type of core0_um_pms_reg2 register - * NA +/** Type of coren_um_hp_peri_pms_reg2 register + * Permission control register2 for HP CPUn in user mode */ typedef union { struct { - /** reg_core0_um_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; - * NA + /** coren_um_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP MCPWM0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_mcpwm0_allow:1; - /** reg_core0_um_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t coren_um_hp_mcpwm0_allow:1; + /** coren_um_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP MCPWM1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_mcpwm1_allow:1; - /** reg_core0_um_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t coren_um_hp_mcpwm1_allow:1; + /** coren_um_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP timer group0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_timer_group0_allow:1; - /** reg_core0_um_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t coren_um_hp_timer_group0_allow:1; + /** coren_um_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP timer group1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_timer_group1_allow:1; - /** reg_core0_um_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t coren_um_hp_timer_group1_allow:1; + /** coren_um_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP I2C0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_i2c0_allow:1; - /** reg_core0_um_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t coren_um_hp_i2c0_allow:1; + /** coren_um_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP I2C1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_i2c1_allow:1; - /** reg_core0_um_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t coren_um_hp_i2c1_allow:1; + /** coren_um_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP I2S0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_i2s0_allow:1; - /** reg_core0_um_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t coren_um_hp_i2s0_allow:1; + /** coren_um_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP I2S1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_i2s1_allow:1; - /** reg_core0_um_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t coren_um_hp_i2s1_allow:1; + /** coren_um_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP I2S2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_i2s2_allow:1; - /** reg_core0_um_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t coren_um_hp_i2s2_allow:1; + /** coren_um_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP PCNT. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_pcnt_allow:1; - /** reg_core0_um_hp_uart0_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t coren_um_hp_pcnt_allow:1; + /** coren_um_hp_uart0_allow : R/W; bitpos: [10]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP UART0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_uart0_allow:1; - /** reg_core0_um_hp_uart1_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t coren_um_hp_uart0_allow:1; + /** coren_um_hp_uart1_allow : R/W; bitpos: [11]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP UART1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_uart1_allow:1; - /** reg_core0_um_hp_uart2_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t coren_um_hp_uart1_allow:1; + /** coren_um_hp_uart2_allow : R/W; bitpos: [12]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP UART2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_uart2_allow:1; - /** reg_core0_um_hp_uart3_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t coren_um_hp_uart2_allow:1; + /** coren_um_hp_uart3_allow : R/W; bitpos: [13]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP UART3. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_uart3_allow:1; - /** reg_core0_um_hp_uart4_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t coren_um_hp_uart3_allow:1; + /** coren_um_hp_uart4_allow : R/W; bitpos: [14]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP UART4. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_uart4_allow:1; - /** reg_core0_um_hp_parlio_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t coren_um_hp_uart4_allow:1; + /** coren_um_hp_parlio_allow : R/W; bitpos: [15]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP PARLIO. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_parlio_allow:1; - /** reg_core0_um_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t coren_um_hp_parlio_allow:1; + /** coren_um_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP GP-SPI2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_gpspi2_allow:1; - /** reg_core0_um_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t coren_um_hp_gpspi2_allow:1; + /** coren_um_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP GP-SPI3. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_gpspi3_allow:1; - /** reg_core0_um_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t coren_um_hp_gpspi3_allow:1; + /** coren_um_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP USB/Serial JTAG + * Controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_usbdevice_allow:1; - /** reg_core0_um_hp_ledc_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t coren_um_hp_usbdevice_allow:1; + /** coren_um_hp_ledc_allow : R/W; bitpos: [19]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP LEDC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_ledc_allow:1; + uint32_t coren_um_hp_ledc_allow:1; uint32_t reserved_20:1; - /** reg_core0_um_hp_etm_allow : R/W; bitpos: [21]; default: 1; - * NA + /** coren_um_hp_etm_allow : R/W; bitpos: [21]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP ETM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_etm_allow:1; - /** reg_core0_um_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t coren_um_hp_etm_allow:1; + /** coren_um_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP interrupt + * matrix. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_intrmtx_allow:1; - /** reg_core0_um_hp_twai0_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t coren_um_hp_intrmtx_allow:1; + /** coren_um_hp_twai0_allow : R/W; bitpos: [23]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP TWAI0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_twai0_allow:1; - /** reg_core0_um_hp_twai1_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t coren_um_hp_twai0_allow:1; + /** coren_um_hp_twai1_allow : R/W; bitpos: [24]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP TWAI1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_twai1_allow:1; - /** reg_core0_um_hp_twai2_allow : R/W; bitpos: [25]; default: 1; - * NA + uint32_t coren_um_hp_twai1_allow:1; + /** coren_um_hp_twai2_allow : R/W; bitpos: [25]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP TWAI2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_twai2_allow:1; - /** reg_core0_um_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; - * NA + uint32_t coren_um_hp_twai2_allow:1; + /** coren_um_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP I3C master + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_i3c_mst_allow:1; - /** reg_core0_um_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; - * NA + uint32_t coren_um_hp_i3c_mst_allow:1; + /** coren_um_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP I3C slave + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_i3c_slv_allow:1; - /** reg_core0_um_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; - * NA + uint32_t coren_um_hp_i3c_slv_allow:1; + /** coren_um_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP LCD_CAM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_lcdcam_allow:1; + uint32_t coren_um_hp_lcdcam_allow:1; uint32_t reserved_29:1; - /** reg_core0_um_hp_adc_allow : R/W; bitpos: [30]; default: 1; - * NA + /** coren_um_hp_adc_allow : R/W; bitpos: [30]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP ADC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_adc_allow:1; - /** reg_core0_um_hp_uhci_allow : R/W; bitpos: [31]; default: 1; - * NA + uint32_t coren_um_hp_adc_allow:1; + /** coren_um_hp_uhci_allow : R/W; bitpos: [31]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP UHCI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_uhci_allow:1; + uint32_t coren_um_hp_uhci_allow:1; }; uint32_t val; -} tee_core0_um_pms_reg2_reg_t; +} pms_coren_um_hp_peri_pms_reg2_reg_t; - -/** Group: TEE CORE0 UM PMS REG3 REG */ -/** Type of core0_um_pms_reg3 register - * NA +/** Type of coren_um_hp_peri_pms_reg3 register + * Permission control register3 for HP CPUn in user mode */ typedef union { struct { - /** reg_core0_um_hp_gpio_allow : R/W; bitpos: [0]; default: 1; - * NA + /** coren_um_hp_gpio_allow : R/W; bitpos: [0]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP GPIO Matrix. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_gpio_allow:1; - /** reg_core0_um_hp_iomux_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t coren_um_hp_gpio_allow:1; + /** coren_um_hp_iomux_allow : R/W; bitpos: [1]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP IO MUX. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_iomux_allow:1; - /** reg_core0_um_hp_systimer_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t coren_um_hp_iomux_allow:1; + /** coren_um_hp_systimer_allow : R/W; bitpos: [2]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP system timer. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_systimer_allow:1; - /** reg_core0_um_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t coren_um_hp_systimer_allow:1; + /** coren_um_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP system + * register. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_sys_reg_allow:1; - /** reg_core0_um_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t coren_um_hp_sys_reg_allow:1; + /** coren_um_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; + * Configures whether HP CPUn in user mode has permission to access HP_SYS_CLKRST. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_core0_um_hp_clkrst_allow:1; + uint32_t coren_um_hp_clkrst_allow:1; uint32_t reserved_5:27; }; uint32_t val; -} tee_core0_um_pms_reg3_reg_t; +} pms_coren_um_hp_peri_pms_reg3_reg_t; - -/** Group: TEE CORE1 MM PMS REG0 REG */ -/** Type of core1_mm_pms_reg0 register - * NA +/** Group: TEE Peripheral Permission Control Register */ +/** Type of regdma_hp_peri_pms register + * HP Peripheral Permission register for REGDMA */ typedef union { struct { - /** reg_core1_mm_psram_allow : R/W; bitpos: [0]; default: 1; - * NA + /** regdma_peri_hp_peri_allow : R/W; bitpos: [0]; default: 1; + * Configures whether REGDMA has permission to access all HP peripherals. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_core1_mm_psram_allow:1; - /** reg_core1_mm_flash_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_core1_mm_flash_allow:1; - /** reg_core1_mm_l2mem_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_core1_mm_l2mem_allow:1; - /** reg_core1_mm_l2rom_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_core1_mm_l2rom_allow:1; - uint32_t reserved_4:2; - /** reg_core1_mm_trace0_allow : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t reg_core1_mm_trace0_allow:1; - /** reg_core1_mm_trace1_allow : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t reg_core1_mm_trace1_allow:1; - /** reg_core1_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t reg_core1_mm_cpu_bus_mon_allow:1; - /** reg_core1_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t reg_core1_mm_l2mem_mon_allow:1; - /** reg_core1_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t reg_core1_mm_tcm_mon_allow:1; - /** reg_core1_mm_cache_allow : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t reg_core1_mm_cache_allow:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} tee_core1_mm_pms_reg0_reg_t; - - -/** Group: TEE CORE1 MM PMS REG1 REG */ -/** Type of core1_mm_pms_reg1 register - * NA - */ -typedef union { - struct { - /** reg_core1_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_usbotg_allow:1; - /** reg_core1_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_usbotg11_allow:1; - /** reg_core1_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_usbotg11_wrap_allow:1; - /** reg_core1_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_gdma_allow:1; - /** reg_core1_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_regdma_allow:1; - /** reg_core1_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_sdmmc_allow:1; - /** reg_core1_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_ahb_pdma_allow:1; - /** reg_core1_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_jpeg_allow:1; - /** reg_core1_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_ppa_allow:1; - /** reg_core1_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_dma2d_allow:1; - /** reg_core1_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_key_manager_allow:1; - /** reg_core1_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_axi_pdma_allow:1; - /** reg_core1_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_flash_allow:1; - /** reg_core1_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_psram_allow:1; - /** reg_core1_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_crypto_allow:1; - /** reg_core1_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_gmac_allow:1; - /** reg_core1_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_usb_phy_allow:1; - /** reg_core1_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_pvt_allow:1; - /** reg_core1_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_csi_host_allow:1; - /** reg_core1_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_dsi_host_allow:1; - /** reg_core1_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_isp_allow:1; - /** reg_core1_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_h264_core_allow:1; - /** reg_core1_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_rmt_allow:1; - /** reg_core1_mm_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_bitscrambler_allow:1; - /** reg_core1_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_axi_icm_allow:1; - /** reg_core1_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_peri_pms_allow:1; - /** reg_core1_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; - * NA - */ - uint32_t reg_core1_mm_lp2hp_peri_pms_allow:1; - /** reg_core1_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t reg_core1_mm_dma_pms_allow:1; - /** reg_core1_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_h264_dma2d_allow:1; - /** reg_core1_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t reg_core1_mm_axi_perf_mon_allow:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} tee_core1_mm_pms_reg1_reg_t; - - -/** Group: TEE CORE1 MM PMS REG2 REG */ -/** Type of core1_mm_pms_reg2 register - * NA - */ -typedef union { - struct { - /** reg_core1_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_mcpwm0_allow:1; - /** reg_core1_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_mcpwm1_allow:1; - /** reg_core1_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_timer_group0_allow:1; - /** reg_core1_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_timer_group1_allow:1; - /** reg_core1_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_i2c0_allow:1; - /** reg_core1_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_i2c1_allow:1; - /** reg_core1_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_i2s0_allow:1; - /** reg_core1_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_i2s1_allow:1; - /** reg_core1_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_i2s2_allow:1; - /** reg_core1_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_pcnt_allow:1; - /** reg_core1_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_uart0_allow:1; - /** reg_core1_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_uart1_allow:1; - /** reg_core1_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_uart2_allow:1; - /** reg_core1_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_uart3_allow:1; - /** reg_core1_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_uart4_allow:1; - /** reg_core1_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_parlio_allow:1; - /** reg_core1_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_gpspi2_allow:1; - /** reg_core1_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_gpspi3_allow:1; - /** reg_core1_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_usbdevice_allow:1; - /** reg_core1_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_ledc_allow:1; - uint32_t reserved_20:1; - /** reg_core1_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_etm_allow:1; - /** reg_core1_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_intrmtx_allow:1; - /** reg_core1_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_twai0_allow:1; - /** reg_core1_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_twai1_allow:1; - /** reg_core1_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_twai2_allow:1; - /** reg_core1_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_i3c_mst_allow:1; - /** reg_core1_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_i3c_slv_allow:1; - /** reg_core1_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_lcdcam_allow:1; - uint32_t reserved_29:1; - /** reg_core1_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_adc_allow:1; - /** reg_core1_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_uhci_allow:1; - }; - uint32_t val; -} tee_core1_mm_pms_reg2_reg_t; - - -/** Group: TEE CORE1 MM PMS REG3 REG */ -/** Type of core1_mm_pms_reg3 register - * NA - */ -typedef union { - struct { - /** reg_core1_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_gpio_allow:1; - /** reg_core1_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_iomux_allow:1; - /** reg_core1_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_systimer_allow:1; - /** reg_core1_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_sys_reg_allow:1; - /** reg_core1_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t reg_core1_mm_hp_clkrst_allow:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} tee_core1_mm_pms_reg3_reg_t; - - -/** Group: TEE CORE1 UM PMS REG0 REG */ -/** Type of core1_um_pms_reg0 register - * NA - */ -typedef union { - struct { - /** reg_core1_um_psram_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_core1_um_psram_allow:1; - /** reg_core1_um_flash_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_core1_um_flash_allow:1; - /** reg_core1_um_l2mem_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_core1_um_l2mem_allow:1; - /** reg_core1_um_l2rom_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_core1_um_l2rom_allow:1; - uint32_t reserved_4:2; - /** reg_core1_um_trace0_allow : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t reg_core1_um_trace0_allow:1; - /** reg_core1_um_trace1_allow : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t reg_core1_um_trace1_allow:1; - /** reg_core1_um_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t reg_core1_um_cpu_bus_mon_allow:1; - /** reg_core1_um_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t reg_core1_um_l2mem_mon_allow:1; - /** reg_core1_um_tcm_mon_allow : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t reg_core1_um_tcm_mon_allow:1; - /** reg_core1_um_cache_allow : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t reg_core1_um_cache_allow:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} tee_core1_um_pms_reg0_reg_t; - - -/** Group: TEE CORE1 UM PMS REG1 REG */ -/** Type of core1_um_pms_reg1 register - * NA - */ -typedef union { - struct { - /** reg_core1_um_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_usbotg_allow:1; - /** reg_core1_um_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_usbotg11_allow:1; - /** reg_core1_um_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_usbotg11_wrap_allow:1; - /** reg_core1_um_hp_gdma_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_gdma_allow:1; - /** reg_core1_um_hp_regdma_allow : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_regdma_allow:1; - /** reg_core1_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_sdmmc_allow:1; - /** reg_core1_um_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_ahb_pdma_allow:1; - /** reg_core1_um_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_jpeg_allow:1; - /** reg_core1_um_hp_ppa_allow : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_ppa_allow:1; - /** reg_core1_um_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_dma2d_allow:1; - /** reg_core1_um_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_key_manager_allow:1; - /** reg_core1_um_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_axi_pdma_allow:1; - /** reg_core1_um_hp_flash_allow : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_flash_allow:1; - /** reg_core1_um_hp_psram_allow : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_psram_allow:1; - /** reg_core1_um_hp_crypto_allow : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_crypto_allow:1; - /** reg_core1_um_hp_gmac_allow : R/W; bitpos: [15]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_gmac_allow:1; - /** reg_core1_um_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_usb_phy_allow:1; - /** reg_core1_um_hp_pvt_allow : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_pvt_allow:1; - /** reg_core1_um_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_csi_host_allow:1; - /** reg_core1_um_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_dsi_host_allow:1; - /** reg_core1_um_hp_isp_allow : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_isp_allow:1; - /** reg_core1_um_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_h264_core_allow:1; - /** reg_core1_um_hp_rmt_allow : R/W; bitpos: [22]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_rmt_allow:1; - /** reg_core1_um_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_bitscrambler_allow:1; - /** reg_core1_um_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_axi_icm_allow:1; - /** reg_core1_um_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_peri_pms_allow:1; - /** reg_core1_um_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; - * NA - */ - uint32_t reg_core1_um_lp2hp_peri_pms_allow:1; - /** reg_core1_um_dma_pms_allow : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t reg_core1_um_dma_pms_allow:1; - /** reg_core1_um_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_h264_dma2d_allow:1; - /** reg_core1_um_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t reg_core1_um_axi_perf_mon_allow:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} tee_core1_um_pms_reg1_reg_t; - - -/** Group: TEE CORE1 UM PMS REG2 REG */ -/** Type of core1_um_pms_reg2 register - * NA - */ -typedef union { - struct { - /** reg_core1_um_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_mcpwm0_allow:1; - /** reg_core1_um_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_mcpwm1_allow:1; - /** reg_core1_um_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_timer_group0_allow:1; - /** reg_core1_um_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_timer_group1_allow:1; - /** reg_core1_um_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_i2c0_allow:1; - /** reg_core1_um_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_i2c1_allow:1; - /** reg_core1_um_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_i2s0_allow:1; - /** reg_core1_um_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_i2s1_allow:1; - /** reg_core1_um_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_i2s2_allow:1; - /** reg_core1_um_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_pcnt_allow:1; - /** reg_core1_um_hp_uart0_allow : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_uart0_allow:1; - /** reg_core1_um_hp_uart1_allow : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_uart1_allow:1; - /** reg_core1_um_hp_uart2_allow : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_uart2_allow:1; - /** reg_core1_um_hp_uart3_allow : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_uart3_allow:1; - /** reg_core1_um_hp_uart4_allow : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_uart4_allow:1; - /** reg_core1_um_hp_parlio_allow : R/W; bitpos: [15]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_parlio_allow:1; - /** reg_core1_um_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_gpspi2_allow:1; - /** reg_core1_um_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_gpspi3_allow:1; - /** reg_core1_um_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_usbdevice_allow:1; - /** reg_core1_um_hp_ledc_allow : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_ledc_allow:1; - uint32_t reserved_20:1; - /** reg_core1_um_hp_etm_allow : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_etm_allow:1; - /** reg_core1_um_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_intrmtx_allow:1; - /** reg_core1_um_hp_twai0_allow : R/W; bitpos: [23]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_twai0_allow:1; - /** reg_core1_um_hp_twai1_allow : R/W; bitpos: [24]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_twai1_allow:1; - /** reg_core1_um_hp_twai2_allow : R/W; bitpos: [25]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_twai2_allow:1; - /** reg_core1_um_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_i3c_mst_allow:1; - /** reg_core1_um_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_i3c_slv_allow:1; - /** reg_core1_um_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_lcdcam_allow:1; - uint32_t reserved_29:1; - /** reg_core1_um_hp_adc_allow : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_adc_allow:1; - /** reg_core1_um_hp_uhci_allow : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_uhci_allow:1; - }; - uint32_t val; -} tee_core1_um_pms_reg2_reg_t; - - -/** Group: TEE CORE1 UM PMS REG3 REG */ -/** Type of core1_um_pms_reg3 register - * NA - */ -typedef union { - struct { - /** reg_core1_um_hp_gpio_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_gpio_allow:1; - /** reg_core1_um_hp_iomux_allow : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_iomux_allow:1; - /** reg_core1_um_hp_systimer_allow : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_systimer_allow:1; - /** reg_core1_um_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_sys_reg_allow:1; - /** reg_core1_um_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t reg_core1_um_hp_clkrst_allow:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} tee_core1_um_pms_reg3_reg_t; - - -/** Group: TEE REGDMA PERI PMS REG */ -/** Type of regdma_peri_pms register - * NA - */ -typedef union { - struct { - /** reg_regdma_peri_allow : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t reg_regdma_peri_allow:1; + uint32_t regdma_peri_hp_peri_allow:1; uint32_t reserved_1:31; }; uint32_t val; -} tee_regdma_peri_pms_reg_t; - +} pms_regdma_hp_peri_pms_reg_t; typedef struct { - volatile tee_pms_date_reg_t pms_date; - volatile tee_pms_clk_en_reg_t pms_clk_en; - volatile tee_core0_mm_pms_reg0_reg_t core0_mm_pms_reg0; - volatile tee_core0_mm_pms_reg1_reg_t core0_mm_pms_reg1; - volatile tee_core0_mm_pms_reg2_reg_t core0_mm_pms_reg2; - volatile tee_core0_mm_pms_reg3_reg_t core0_mm_pms_reg3; - volatile tee_core0_um_pms_reg0_reg_t core0_um_pms_reg0; - volatile tee_core0_um_pms_reg1_reg_t core0_um_pms_reg1; - volatile tee_core0_um_pms_reg2_reg_t core0_um_pms_reg2; - volatile tee_core0_um_pms_reg3_reg_t core0_um_pms_reg3; - volatile tee_core1_mm_pms_reg0_reg_t core1_mm_pms_reg0; - volatile tee_core1_mm_pms_reg1_reg_t core1_mm_pms_reg1; - volatile tee_core1_mm_pms_reg2_reg_t core1_mm_pms_reg2; - volatile tee_core1_mm_pms_reg3_reg_t core1_mm_pms_reg3; - volatile tee_core1_um_pms_reg0_reg_t core1_um_pms_reg0; - volatile tee_core1_um_pms_reg1_reg_t core1_um_pms_reg1; - volatile tee_core1_um_pms_reg2_reg_t core1_um_pms_reg2; - volatile tee_core1_um_pms_reg3_reg_t core1_um_pms_reg3; - volatile tee_regdma_peri_pms_reg_t regdma_peri_pms; -} tee_dev_t; + volatile pms_hp_peri_pms_date_reg_t hp_peri_pms_date; + volatile pms_hp_peri_pms_clk_en_reg_t hp_peri_pms_clk_en; + volatile pms_coren_mm_hp_peri_pms_reg0_reg_t core0_mm_hp_peri_pms_reg0; + volatile pms_coren_mm_hp_peri_pms_reg1_reg_t core0_mm_hp_peri_pms_reg1; + volatile pms_coren_mm_hp_peri_pms_reg2_reg_t core0_mm_hp_peri_pms_reg2; + volatile pms_coren_mm_hp_peri_pms_reg3_reg_t core0_mm_hp_peri_pms_reg3; + volatile pms_coren_um_hp_peri_pms_reg0_reg_t core0_um_hp_peri_pms_reg0; + volatile pms_coren_um_hp_peri_pms_reg1_reg_t core0_um_hp_peri_pms_reg1; + volatile pms_coren_um_hp_peri_pms_reg2_reg_t core0_um_hp_peri_pms_reg2; + volatile pms_coren_um_hp_peri_pms_reg3_reg_t core0_um_hp_peri_pms_reg3; + volatile pms_coren_mm_hp_peri_pms_reg0_reg_t core1_mm_hp_peri_pms_reg0; + volatile pms_coren_mm_hp_peri_pms_reg1_reg_t core1_mm_hp_peri_pms_reg1; + volatile pms_coren_mm_hp_peri_pms_reg2_reg_t core1_mm_hp_peri_pms_reg2; + volatile pms_coren_mm_hp_peri_pms_reg3_reg_t core1_mm_hp_peri_pms_reg3; + volatile pms_coren_um_hp_peri_pms_reg0_reg_t core1_um_hp_peri_pms_reg0; + volatile pms_coren_um_hp_peri_pms_reg1_reg_t core1_um_hp_peri_pms_reg1; + volatile pms_coren_um_hp_peri_pms_reg2_reg_t core1_um_hp_peri_pms_reg2; + volatile pms_coren_um_hp_peri_pms_reg3_reg_t core1_um_hp_peri_pms_reg3; + volatile pms_regdma_hp_peri_pms_reg_t regdma_hp_peri_pms; +} hp_peri_pms_dev_t; -extern tee_dev_t HP_PERI_PMS; +extern hp_peri_pms_dev_t HP_PERI_PMS; #ifndef __cplusplus -_Static_assert(sizeof(tee_dev_t) == 0x4c, "Invalid size of tee_dev_t structure"); +_Static_assert(sizeof(hp_peri_pms_dev_t) == 0x4c, "Invalid size of hp_peri_pms_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_reg.h index 12482ab596d..c7d7f207812 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_reg.h @@ -13,7 +13,7 @@ extern "C" { /** ICM_VER_DATE_REG register * NA */ -#define ICM_VER_DATE_REG (DR_REG_ICM_BASE + 0x0) +#define ICM_VER_DATE_REG (DR_REG_AXI_ICM_BASE + 0x0) /** ICM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165204; * NA */ @@ -25,7 +25,7 @@ extern "C" { /** ICM_CLK_EN_REG register * NA */ -#define ICM_CLK_EN_REG (DR_REG_ICM_BASE + 0x4) +#define ICM_CLK_EN_REG (DR_REG_AXI_ICM_BASE + 0x4) /** ICM_REG_CLK_EN : R/W; bitpos: [0]; default: 0; * NA */ @@ -37,7 +37,7 @@ extern "C" { /** ICM_DLOCK_STATUS_REG register * NA */ -#define ICM_DLOCK_STATUS_REG (DR_REG_ICM_BASE + 0x8) +#define ICM_DLOCK_STATUS_REG (DR_REG_AXI_ICM_BASE + 0x8) /** ICM_REG_DLOCK_MST : RO; bitpos: [3:0]; default: 0; * Lowest numbered deadlocked master */ @@ -70,7 +70,7 @@ extern "C" { /** ICM_INT_RAW_REG register * NA */ -#define ICM_INT_RAW_REG (DR_REG_ICM_BASE + 0xc) +#define ICM_INT_RAW_REG (DR_REG_AXI_ICM_BASE + 0xc) /** ICM_REG_DLOCK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * NA */ @@ -96,7 +96,7 @@ extern "C" { /** ICM_INT_ST_REG register * NA */ -#define ICM_INT_ST_REG (DR_REG_ICM_BASE + 0x10) +#define ICM_INT_ST_REG (DR_REG_AXI_ICM_BASE + 0x10) /** ICM_REG_DLOCK_INT_ST : RO; bitpos: [0]; default: 0; * NA */ @@ -122,7 +122,7 @@ extern "C" { /** ICM_INT_ENA_REG register * NA */ -#define ICM_INT_ENA_REG (DR_REG_ICM_BASE + 0x14) +#define ICM_INT_ENA_REG (DR_REG_AXI_ICM_BASE + 0x14) /** ICM_REG_DLOCK_INT_ENA : R/W; bitpos: [0]; default: 1; * NA */ @@ -148,7 +148,7 @@ extern "C" { /** ICM_INT_CLR_REG register * NA */ -#define ICM_INT_CLR_REG (DR_REG_ICM_BASE + 0x18) +#define ICM_INT_CLR_REG (DR_REG_AXI_ICM_BASE + 0x18) /** ICM_REG_DLOCK_INT_CLR : WT; bitpos: [0]; default: 0; * NA */ @@ -174,7 +174,7 @@ extern "C" { /** ICM_MST_ARB_PRIORITY_REG0_REG register * NA */ -#define ICM_MST_ARB_PRIORITY_REG0_REG (DR_REG_ICM_BASE + 0x1c) +#define ICM_MST_ARB_PRIORITY_REG0_REG (DR_REG_AXI_ICM_BASE + 0x1c) /** ICM_REG_CPU_PRIORITY : R/W; bitpos: [3:0]; default: 0; * CPU arbitration priority for command channels between masters connected to sys_icm */ @@ -240,7 +240,7 @@ extern "C" { /** ICM_SLV_ARB_PRIORITY_REG register * NA */ -#define ICM_SLV_ARB_PRIORITY_REG (DR_REG_ICM_BASE + 0x24) +#define ICM_SLV_ARB_PRIORITY_REG (DR_REG_AXI_ICM_BASE + 0x24) /** ICM_REG_L2MEM_PRIORITY : R/W; bitpos: [5:3]; default: 0; * L2MEM arbitration priority for response channels between slaves connected to sys_icm */ @@ -284,7 +284,7 @@ extern "C" { /** ICM_MST_ARQOS_REG0_REG register * NA */ -#define ICM_MST_ARQOS_REG0_REG (DR_REG_ICM_BASE + 0x28) +#define ICM_MST_ARQOS_REG0_REG (DR_REG_AXI_ICM_BASE + 0x28) /** ICM_REG_CPU_ARQOS : R/W; bitpos: [3:0]; default: 0; * NA */ @@ -345,7 +345,7 @@ extern "C" { /** ICM_MST_AWQOS_REG0_REG register * NA */ -#define ICM_MST_AWQOS_REG0_REG (DR_REG_ICM_BASE + 0x30) +#define ICM_MST_AWQOS_REG0_REG (DR_REG_AXI_ICM_BASE + 0x30) /** ICM_REG_CPU_AWQOS : R/W; bitpos: [3:0]; default: 0; * NA */ @@ -406,7 +406,7 @@ extern "C" { /** ICM_SYS_ADDRHOLE_ADDR_REG register * icm sys addr hole address registers */ -#define ICM_SYS_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x38) +#define ICM_SYS_ADDRHOLE_ADDR_REG (DR_REG_AXI_ICM_BASE + 0x38) /** ICM_REG_ICM_SYS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0; * NA */ @@ -418,7 +418,7 @@ extern "C" { /** ICM_SYS_ADDRHOLE_INFO_REG register * NA */ -#define ICM_SYS_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x3c) +#define ICM_SYS_ADDRHOLE_INFO_REG (DR_REG_AXI_ICM_BASE + 0x3c) /** ICM_REG_ICM_SYS_ADDRHOLE_ID : RO; bitpos: [7:0]; default: 0; * master id = 4-bit CID + 4-bit UID(refer to related IP) . CID is used to verify * master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma, @@ -447,7 +447,7 @@ extern "C" { /** ICM_CPU_ADDRHOLE_ADDR_REG register * icm cpu addr hole address registers */ -#define ICM_CPU_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x40) +#define ICM_CPU_ADDRHOLE_ADDR_REG (DR_REG_AXI_ICM_BASE + 0x40) /** ICM_REG_ICM_CPU_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0; * It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it * the address without permission to access. @@ -460,7 +460,7 @@ extern "C" { /** ICM_CPU_ADDRHOLE_INFO_REG register * NA */ -#define ICM_CPU_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x44) +#define ICM_CPU_ADDRHOLE_INFO_REG (DR_REG_AXI_ICM_BASE + 0x44) /** ICM_REG_ICM_CPU_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0; * master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: * regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha @@ -488,7 +488,7 @@ extern "C" { /** ICM_DLOCK_TIMEOUT_REG register * NA */ -#define ICM_DLOCK_TIMEOUT_REG (DR_REG_ICM_BASE + 0x48) +#define ICM_DLOCK_TIMEOUT_REG (DR_REG_AXI_ICM_BASE + 0x48) /** ICM_REG_DLOCK_TIMEOUT : R/W; bitpos: [12:0]; default: 2048; * if no response until reg_dlock_timeout bus clock cycle, deadlock will happen */ @@ -500,7 +500,7 @@ extern "C" { /** ICM_RDN_ECO_CS_REG register * NA */ -#define ICM_RDN_ECO_CS_REG (DR_REG_ICM_BASE + 0x50) +#define ICM_RDN_ECO_CS_REG (DR_REG_AXI_ICM_BASE + 0x50) /** ICM_REG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0; * NA */ @@ -519,7 +519,7 @@ extern "C" { /** ICM_RDN_ECO_LOW_REG register * NA */ -#define ICM_RDN_ECO_LOW_REG (DR_REG_ICM_BASE + 0x54) +#define ICM_RDN_ECO_LOW_REG (DR_REG_AXI_ICM_BASE + 0x54) /** ICM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; * NA */ @@ -531,7 +531,7 @@ extern "C" { /** ICM_RDN_ECO_HIGH_REG register * NA */ -#define ICM_RDN_ECO_HIGH_REG (DR_REG_ICM_BASE + 0x58) +#define ICM_RDN_ECO_HIGH_REG (DR_REG_AXI_ICM_BASE + 0x58) /** ICM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; * NA */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h deleted file mode 100644 index e82770c04f5..00000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h +++ /dev/null @@ -1,584 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 OR MIT - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** TEE_LP2HP_PMS_DATE_REG register - * NA - */ -#define TEE_LP2HP_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0) -/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943; - * NA - */ -#define TEE_TEE_DATE 0xFFFFFFFFU -#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S) -#define TEE_TEE_DATE_V 0xFFFFFFFFU -#define TEE_TEE_DATE_S 0 - -/** TEE_PMS_CLK_EN_REG register - * NA - */ -#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4) -/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CLK_EN (BIT(0)) -#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S) -#define TEE_REG_CLK_EN_V 0x00000001U -#define TEE_REG_CLK_EN_S 0 - -/** TEE_LP_MM_PMS_REG0_REG register - * NA - */ -#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8) -/** TEE_REG_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_PSRAM_ALLOW (BIT(0)) -#define TEE_REG_LP_MM_PSRAM_ALLOW_M (TEE_REG_LP_MM_PSRAM_ALLOW_V << TEE_REG_LP_MM_PSRAM_ALLOW_S) -#define TEE_REG_LP_MM_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_PSRAM_ALLOW_S 0 -/** TEE_REG_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_FLASH_ALLOW (BIT(1)) -#define TEE_REG_LP_MM_FLASH_ALLOW_M (TEE_REG_LP_MM_FLASH_ALLOW_V << TEE_REG_LP_MM_FLASH_ALLOW_S) -#define TEE_REG_LP_MM_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_FLASH_ALLOW_S 1 -/** TEE_REG_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_L2MEM_ALLOW (BIT(2)) -#define TEE_REG_LP_MM_L2MEM_ALLOW_M (TEE_REG_LP_MM_L2MEM_ALLOW_V << TEE_REG_LP_MM_L2MEM_ALLOW_S) -#define TEE_REG_LP_MM_L2MEM_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_L2MEM_ALLOW_S 2 -/** TEE_REG_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_L2ROM_ALLOW (BIT(3)) -#define TEE_REG_LP_MM_L2ROM_ALLOW_M (TEE_REG_LP_MM_L2ROM_ALLOW_V << TEE_REG_LP_MM_L2ROM_ALLOW_S) -#define TEE_REG_LP_MM_L2ROM_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_L2ROM_ALLOW_S 3 -/** TEE_REG_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_TRACE0_ALLOW (BIT(6)) -#define TEE_REG_LP_MM_TRACE0_ALLOW_M (TEE_REG_LP_MM_TRACE0_ALLOW_V << TEE_REG_LP_MM_TRACE0_ALLOW_S) -#define TEE_REG_LP_MM_TRACE0_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_TRACE0_ALLOW_S 6 -/** TEE_REG_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_TRACE1_ALLOW (BIT(7)) -#define TEE_REG_LP_MM_TRACE1_ALLOW_M (TEE_REG_LP_MM_TRACE1_ALLOW_V << TEE_REG_LP_MM_TRACE1_ALLOW_S) -#define TEE_REG_LP_MM_TRACE1_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_TRACE1_ALLOW_S 7 -/** TEE_REG_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW (BIT(8)) -#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_M (TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S) -#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S 8 -/** TEE_REG_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_L2MEM_MON_ALLOW (BIT(9)) -#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_M (TEE_REG_LP_MM_L2MEM_MON_ALLOW_V << TEE_REG_LP_MM_L2MEM_MON_ALLOW_S) -#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_S 9 -/** TEE_REG_LP_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_TCM_MON_ALLOW (BIT(10)) -#define TEE_REG_LP_MM_TCM_MON_ALLOW_M (TEE_REG_LP_MM_TCM_MON_ALLOW_V << TEE_REG_LP_MM_TCM_MON_ALLOW_S) -#define TEE_REG_LP_MM_TCM_MON_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_TCM_MON_ALLOW_S 10 -/** TEE_REG_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_CACHE_ALLOW (BIT(11)) -#define TEE_REG_LP_MM_CACHE_ALLOW_M (TEE_REG_LP_MM_CACHE_ALLOW_V << TEE_REG_LP_MM_CACHE_ALLOW_S) -#define TEE_REG_LP_MM_CACHE_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_CACHE_ALLOW_S 11 - -/** TEE_LP_MM_PMS_REG1_REG register - * NA - */ -#define TEE_LP_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x30) -/** TEE_REG_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_USBOTG_ALLOW (BIT(0)) -#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG_ALLOW_S) -#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_S 0 -/** TEE_REG_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW (BIT(1)) -#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S) -#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S 1 -/** TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW (BIT(2)) -#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S) -#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S 2 -/** TEE_REG_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_GDMA_ALLOW (BIT(3)) -#define TEE_REG_LP_MM_HP_GDMA_ALLOW_M (TEE_REG_LP_MM_HP_GDMA_ALLOW_V << TEE_REG_LP_MM_HP_GDMA_ALLOW_S) -#define TEE_REG_LP_MM_HP_GDMA_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_GDMA_ALLOW_S 3 -/** TEE_REG_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_REGDMA_ALLOW (BIT(4)) -#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_M (TEE_REG_LP_MM_HP_REGDMA_ALLOW_V << TEE_REG_LP_MM_HP_REGDMA_ALLOW_S) -#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_S 4 -/** TEE_REG_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_SDMMC_ALLOW (BIT(5)) -#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_M (TEE_REG_LP_MM_HP_SDMMC_ALLOW_V << TEE_REG_LP_MM_HP_SDMMC_ALLOW_S) -#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_S 5 -/** TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW (BIT(6)) -#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_M (TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S) -#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S 6 -/** TEE_REG_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_JPEG_ALLOW (BIT(7)) -#define TEE_REG_LP_MM_HP_JPEG_ALLOW_M (TEE_REG_LP_MM_HP_JPEG_ALLOW_V << TEE_REG_LP_MM_HP_JPEG_ALLOW_S) -#define TEE_REG_LP_MM_HP_JPEG_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_JPEG_ALLOW_S 7 -/** TEE_REG_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_PPA_ALLOW (BIT(8)) -#define TEE_REG_LP_MM_HP_PPA_ALLOW_M (TEE_REG_LP_MM_HP_PPA_ALLOW_V << TEE_REG_LP_MM_HP_PPA_ALLOW_S) -#define TEE_REG_LP_MM_HP_PPA_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_PPA_ALLOW_S 8 -/** TEE_REG_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_DMA2D_ALLOW (BIT(9)) -#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_M (TEE_REG_LP_MM_HP_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_DMA2D_ALLOW_S) -#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_S 9 -/** TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW (BIT(10)) -#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_M (TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S) -#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S 10 -/** TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW (BIT(11)) -#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_M (TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S) -#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S 11 -/** TEE_REG_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_FLASH_ALLOW (BIT(12)) -#define TEE_REG_LP_MM_HP_FLASH_ALLOW_M (TEE_REG_LP_MM_HP_FLASH_ALLOW_V << TEE_REG_LP_MM_HP_FLASH_ALLOW_S) -#define TEE_REG_LP_MM_HP_FLASH_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_FLASH_ALLOW_S 12 -/** TEE_REG_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_PSRAM_ALLOW (BIT(13)) -#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_M (TEE_REG_LP_MM_HP_PSRAM_ALLOW_V << TEE_REG_LP_MM_HP_PSRAM_ALLOW_S) -#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_S 13 -/** TEE_REG_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW (BIT(14)) -#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_M (TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V << TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S) -#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S 14 -/** TEE_REG_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_GMAC_ALLOW (BIT(15)) -#define TEE_REG_LP_MM_HP_GMAC_ALLOW_M (TEE_REG_LP_MM_HP_GMAC_ALLOW_V << TEE_REG_LP_MM_HP_GMAC_ALLOW_S) -#define TEE_REG_LP_MM_HP_GMAC_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_GMAC_ALLOW_S 15 -/** TEE_REG_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW (BIT(16)) -#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_M (TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V << TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S) -#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S 16 -/** TEE_REG_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_PVT_ALLOW (BIT(17)) -#define TEE_REG_LP_MM_HP_PVT_ALLOW_M (TEE_REG_LP_MM_HP_PVT_ALLOW_V << TEE_REG_LP_MM_HP_PVT_ALLOW_S) -#define TEE_REG_LP_MM_HP_PVT_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_PVT_ALLOW_S 17 -/** TEE_REG_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW (BIT(18)) -#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_M (TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S) -#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S 18 -/** TEE_REG_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW (BIT(19)) -#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_M (TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S) -#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S 19 -/** TEE_REG_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_ISP_ALLOW (BIT(20)) -#define TEE_REG_LP_MM_HP_ISP_ALLOW_M (TEE_REG_LP_MM_HP_ISP_ALLOW_V << TEE_REG_LP_MM_HP_ISP_ALLOW_S) -#define TEE_REG_LP_MM_HP_ISP_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_ISP_ALLOW_S 20 -/** TEE_REG_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW (BIT(21)) -#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_M (TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V << TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S) -#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S 21 -/** TEE_REG_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_RMT_ALLOW (BIT(22)) -#define TEE_REG_LP_MM_HP_RMT_ALLOW_M (TEE_REG_LP_MM_HP_RMT_ALLOW_V << TEE_REG_LP_MM_HP_RMT_ALLOW_S) -#define TEE_REG_LP_MM_HP_RMT_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_RMT_ALLOW_S 22 -/** TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_S) -#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_S 23 -/** TEE_REG_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW (BIT(24)) -#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_M (TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S) -#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S 24 -/** TEE_REG_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW (BIT(25)) -#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_M (TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S) -#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S 25 -/** TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW (BIT(26)) -#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_M (TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S) -#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S 26 -/** TEE_REG_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_DMA_PMS_ALLOW (BIT(27)) -#define TEE_REG_LP_MM_DMA_PMS_ALLOW_M (TEE_REG_LP_MM_DMA_PMS_ALLOW_V << TEE_REG_LP_MM_DMA_PMS_ALLOW_S) -#define TEE_REG_LP_MM_DMA_PMS_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_DMA_PMS_ALLOW_S 27 -/** TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW (BIT(28)) -#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_M (TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S) -#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S 28 -/** TEE_REG_LP_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW (BIT(29)) -#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_M (TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S) -#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S 29 - -/** TEE_LP_MM_PMS_REG2_REG register - * NA - */ -#define TEE_LP_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0xa4) -/** TEE_REG_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW (BIT(0)) -#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_M (TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S) -#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S 0 -/** TEE_REG_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW (BIT(1)) -#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_M (TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S) -#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S 1 -/** TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW (BIT(2)) -#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_M (TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S) -#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S 2 -/** TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW (BIT(3)) -#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_M (TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S) -#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S 3 -/** TEE_REG_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_I2C0_ALLOW (BIT(4)) -#define TEE_REG_LP_MM_HP_I2C0_ALLOW_M (TEE_REG_LP_MM_HP_I2C0_ALLOW_V << TEE_REG_LP_MM_HP_I2C0_ALLOW_S) -#define TEE_REG_LP_MM_HP_I2C0_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_I2C0_ALLOW_S 4 -/** TEE_REG_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_I2C1_ALLOW (BIT(5)) -#define TEE_REG_LP_MM_HP_I2C1_ALLOW_M (TEE_REG_LP_MM_HP_I2C1_ALLOW_V << TEE_REG_LP_MM_HP_I2C1_ALLOW_S) -#define TEE_REG_LP_MM_HP_I2C1_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_I2C1_ALLOW_S 5 -/** TEE_REG_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_I2S0_ALLOW (BIT(6)) -#define TEE_REG_LP_MM_HP_I2S0_ALLOW_M (TEE_REG_LP_MM_HP_I2S0_ALLOW_V << TEE_REG_LP_MM_HP_I2S0_ALLOW_S) -#define TEE_REG_LP_MM_HP_I2S0_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_I2S0_ALLOW_S 6 -/** TEE_REG_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_I2S1_ALLOW (BIT(7)) -#define TEE_REG_LP_MM_HP_I2S1_ALLOW_M (TEE_REG_LP_MM_HP_I2S1_ALLOW_V << TEE_REG_LP_MM_HP_I2S1_ALLOW_S) -#define TEE_REG_LP_MM_HP_I2S1_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_I2S1_ALLOW_S 7 -/** TEE_REG_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_I2S2_ALLOW (BIT(8)) -#define TEE_REG_LP_MM_HP_I2S2_ALLOW_M (TEE_REG_LP_MM_HP_I2S2_ALLOW_V << TEE_REG_LP_MM_HP_I2S2_ALLOW_S) -#define TEE_REG_LP_MM_HP_I2S2_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_I2S2_ALLOW_S 8 -/** TEE_REG_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_PCNT_ALLOW (BIT(9)) -#define TEE_REG_LP_MM_HP_PCNT_ALLOW_M (TEE_REG_LP_MM_HP_PCNT_ALLOW_V << TEE_REG_LP_MM_HP_PCNT_ALLOW_S) -#define TEE_REG_LP_MM_HP_PCNT_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_PCNT_ALLOW_S 9 -/** TEE_REG_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_UART0_ALLOW (BIT(10)) -#define TEE_REG_LP_MM_HP_UART0_ALLOW_M (TEE_REG_LP_MM_HP_UART0_ALLOW_V << TEE_REG_LP_MM_HP_UART0_ALLOW_S) -#define TEE_REG_LP_MM_HP_UART0_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_UART0_ALLOW_S 10 -/** TEE_REG_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_UART1_ALLOW (BIT(11)) -#define TEE_REG_LP_MM_HP_UART1_ALLOW_M (TEE_REG_LP_MM_HP_UART1_ALLOW_V << TEE_REG_LP_MM_HP_UART1_ALLOW_S) -#define TEE_REG_LP_MM_HP_UART1_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_UART1_ALLOW_S 11 -/** TEE_REG_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_UART2_ALLOW (BIT(12)) -#define TEE_REG_LP_MM_HP_UART2_ALLOW_M (TEE_REG_LP_MM_HP_UART2_ALLOW_V << TEE_REG_LP_MM_HP_UART2_ALLOW_S) -#define TEE_REG_LP_MM_HP_UART2_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_UART2_ALLOW_S 12 -/** TEE_REG_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_UART3_ALLOW (BIT(13)) -#define TEE_REG_LP_MM_HP_UART3_ALLOW_M (TEE_REG_LP_MM_HP_UART3_ALLOW_V << TEE_REG_LP_MM_HP_UART3_ALLOW_S) -#define TEE_REG_LP_MM_HP_UART3_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_UART3_ALLOW_S 13 -/** TEE_REG_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_UART4_ALLOW (BIT(14)) -#define TEE_REG_LP_MM_HP_UART4_ALLOW_M (TEE_REG_LP_MM_HP_UART4_ALLOW_V << TEE_REG_LP_MM_HP_UART4_ALLOW_S) -#define TEE_REG_LP_MM_HP_UART4_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_UART4_ALLOW_S 14 -/** TEE_REG_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_PARLIO_ALLOW (BIT(15)) -#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_M (TEE_REG_LP_MM_HP_PARLIO_ALLOW_V << TEE_REG_LP_MM_HP_PARLIO_ALLOW_S) -#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_S 15 -/** TEE_REG_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW (BIT(16)) -#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_M (TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S) -#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S 16 -/** TEE_REG_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW (BIT(17)) -#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_M (TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S) -#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S 17 -/** TEE_REG_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW (BIT(18)) -#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_M (TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S) -#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S 18 -/** TEE_REG_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_LEDC_ALLOW (BIT(19)) -#define TEE_REG_LP_MM_HP_LEDC_ALLOW_M (TEE_REG_LP_MM_HP_LEDC_ALLOW_V << TEE_REG_LP_MM_HP_LEDC_ALLOW_S) -#define TEE_REG_LP_MM_HP_LEDC_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_LEDC_ALLOW_S 19 -/** TEE_REG_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_ETM_ALLOW (BIT(21)) -#define TEE_REG_LP_MM_HP_ETM_ALLOW_M (TEE_REG_LP_MM_HP_ETM_ALLOW_V << TEE_REG_LP_MM_HP_ETM_ALLOW_S) -#define TEE_REG_LP_MM_HP_ETM_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_ETM_ALLOW_S 21 -/** TEE_REG_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW (BIT(22)) -#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_M (TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V << TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S) -#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S 22 -/** TEE_REG_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_TWAI0_ALLOW (BIT(23)) -#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_M (TEE_REG_LP_MM_HP_TWAI0_ALLOW_V << TEE_REG_LP_MM_HP_TWAI0_ALLOW_S) -#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_S 23 -/** TEE_REG_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_TWAI1_ALLOW (BIT(24)) -#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_M (TEE_REG_LP_MM_HP_TWAI1_ALLOW_V << TEE_REG_LP_MM_HP_TWAI1_ALLOW_S) -#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_S 24 -/** TEE_REG_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_TWAI2_ALLOW (BIT(25)) -#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_M (TEE_REG_LP_MM_HP_TWAI2_ALLOW_V << TEE_REG_LP_MM_HP_TWAI2_ALLOW_S) -#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_S 25 -/** TEE_REG_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW (BIT(26)) -#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_M (TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V << TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S) -#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S 26 -/** TEE_REG_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW (BIT(27)) -#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_M (TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S) -#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S 27 -/** TEE_REG_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW (BIT(28)) -#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_M (TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V << TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S) -#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S 28 -/** TEE_REG_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_ADC_ALLOW (BIT(30)) -#define TEE_REG_LP_MM_HP_ADC_ALLOW_M (TEE_REG_LP_MM_HP_ADC_ALLOW_V << TEE_REG_LP_MM_HP_ADC_ALLOW_S) -#define TEE_REG_LP_MM_HP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_ADC_ALLOW_S 30 -/** TEE_REG_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_UHCI_ALLOW (BIT(31)) -#define TEE_REG_LP_MM_HP_UHCI_ALLOW_M (TEE_REG_LP_MM_HP_UHCI_ALLOW_V << TEE_REG_LP_MM_HP_UHCI_ALLOW_S) -#define TEE_REG_LP_MM_HP_UHCI_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_UHCI_ALLOW_S 31 - -/** TEE_LP_MM_PMS_REG3_REG register - * NA - */ -#define TEE_LP_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x11c) -/** TEE_REG_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_GPIO_ALLOW (BIT(0)) -#define TEE_REG_LP_MM_HP_GPIO_ALLOW_M (TEE_REG_LP_MM_HP_GPIO_ALLOW_V << TEE_REG_LP_MM_HP_GPIO_ALLOW_S) -#define TEE_REG_LP_MM_HP_GPIO_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_GPIO_ALLOW_S 0 -/** TEE_REG_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_IOMUX_ALLOW (BIT(1)) -#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_M (TEE_REG_LP_MM_HP_IOMUX_ALLOW_V << TEE_REG_LP_MM_HP_IOMUX_ALLOW_S) -#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_S 1 -/** TEE_REG_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW (BIT(2)) -#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_M (TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S) -#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S 2 -/** TEE_REG_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW (BIT(3)) -#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_M (TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V << TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S) -#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S 3 -/** TEE_REG_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP_CLKRST_ALLOW (BIT(4)) -#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_M (TEE_REG_LP_MM_HP_CLKRST_ALLOW_V << TEE_REG_LP_MM_HP_CLKRST_ALLOW_S) -#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_S 4 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h index 43b54a905ed..59d001b00b3 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { * Version control register */ #define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x0) -/** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790; +/** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2363943; * Version control register. */ #define PMS_LP2HP_PERI_PMS_DATE 0xFFFFFFFFU @@ -180,6 +180,15 @@ extern "C" { #define PMS_LP_MM_HP_GDMA_ALLOW_M (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S) #define PMS_LP_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_LP_MM_HP_GDMA_ALLOW_S 3 +/** PMS_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP REGDMA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_REGDMA_ALLOW (BIT(4)) +#define PMS_LP_MM_HP_REGDMA_ALLOW_M (PMS_LP_MM_HP_REGDMA_ALLOW_V << PMS_LP_MM_HP_REGDMA_ALLOW_S) +#define PMS_LP_MM_HP_REGDMA_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_REGDMA_ALLOW_S 4 /** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; * Configures whether the LP CPU in machine mode has permission to access HP SDMMC. * 0: Not allowed @@ -407,6 +416,15 @@ extern "C" { #define PMS_LP_MM_HP_H264_DMA2D_ALLOW_M (PMS_LP_MM_HP_H264_DMA2D_ALLOW_V << PMS_LP_MM_HP_H264_DMA2D_ALLOW_S) #define PMS_LP_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U #define PMS_LP_MM_HP_H264_DMA2D_ALLOW_S 28 +/** PMS_LP_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access AXI-PERFMON. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_AXI_PERF_MON_ALLOW (BIT(29)) +#define PMS_LP_MM_AXI_PERF_MON_ALLOW_M (PMS_LP_MM_AXI_PERF_MON_ALLOW_V << PMS_LP_MM_AXI_PERF_MON_ALLOW_S) +#define PMS_LP_MM_AXI_PERF_MON_ALLOW_V 0x00000001U +#define PMS_LP_MM_AXI_PERF_MON_ALLOW_S 29 /** PMS_LP_MM_PMS_REG2_REG register * Permission control register2 for the LP CPU in machine mode diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_struct.h index 569acda81b1..506df1e868c 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_struct.h @@ -10,403 +10,574 @@ extern "C" { #endif -/** Group: TEE LP2HP PMS DATE REG */ -/** Type of lp2hp_pms_date register - * NA +/** Group: Version Control Registers */ +/** Type of lp2hp_peri_pms_date register + * Version control register */ typedef union { struct { - /** tee_date : R/W; bitpos: [31:0]; default: 2363943; - * NA + /** lp2hp_peri_pms_date : R/W; bitpos: [31:0]; default: 2363943; + * Version control register. */ - uint32_t tee_date:32; + uint32_t lp2hp_peri_pms_date:32; }; uint32_t val; -} tee_lp2hp_pms_date_reg_t; +} pms_lp2hp_peri_pms_date_reg_t; -/** Group: TEE PMS CLK EN REG */ -/** Type of pms_clk_en register - * NA +/** Group: Clock Gating Registers */ +/** Type of lp2hp_peri_pms_clk_en register + * Clock gating register */ typedef union { struct { - /** reg_clk_en : R/W; bitpos: [0]; default: 1; - * NA + /** lp2hp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating. + * 1: Keep the clock always on. */ - uint32_t reg_clk_en:1; + uint32_t lp2hp_peri_pms_clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} tee_pms_clk_en_reg_t; +} pms_lp2hp_peri_pms_clk_en_reg_t; -/** Group: TEE LP MM PMS REG0 REG */ +/** Group: LP CPU Permission Control Registers */ /** Type of lp_mm_pms_reg0 register - * NA + * Permission control register0 for the LP CPU in machine mode */ typedef union { struct { - /** reg_lp_mm_psram_allow : R/W; bitpos: [0]; default: 1; - * NA + /** lp_mm_psram_allow : R/W; bitpos: [0]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access external RAM + * without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_psram_allow:1; - /** reg_lp_mm_flash_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t lp_mm_psram_allow:1; + /** lp_mm_flash_allow : R/W; bitpos: [1]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access external + * flash without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_flash_allow:1; - /** reg_lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t lp_mm_flash_allow:1; + /** lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP L2M2M + * without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_l2mem_allow:1; - /** reg_lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t lp_mm_l2mem_allow:1; + /** lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP ROM + * without going through cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_l2rom_allow:1; + uint32_t lp_mm_l2rom_allow:1; uint32_t reserved_4:2; - /** reg_lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1; - * NA + /** lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access TRACE0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_trace0_allow:1; - /** reg_lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t lp_mm_trace0_allow:1; + /** lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access TRACE1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_trace1_allow:1; - /** reg_lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t lp_mm_trace1_allow:1; + /** lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access CPU bus + * monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_cpu_bus_mon_allow:1; - /** reg_lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t lp_mm_cpu_bus_mon_allow:1; + /** lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access L2MEM + * monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_l2mem_mon_allow:1; - /** reg_lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t lp_mm_l2mem_mon_allow:1; + /** lp_mm_spm_mon_allow : R/W; bitpos: [10]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access SPM monitor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_tcm_mon_allow:1; - /** reg_lp_mm_cache_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t lp_mm_spm_mon_allow:1; + /** lp_mm_cache_allow : R/W; bitpos: [11]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access cache. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_cache_allow:1; + uint32_t lp_mm_cache_allow:1; uint32_t reserved_12:20; }; uint32_t val; -} tee_lp_mm_pms_reg0_reg_t; +} pms_lp_mm_pms_reg0_reg_t; - -/** Group: TEE LP MM PMS REG1 REG */ /** Type of lp_mm_pms_reg1 register - * NA + * Permission control register1 for the LP CPU in machine mode */ typedef union { struct { - /** reg_lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; - * NA + /** lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * high-speed USB 2.0 OTG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_usbotg_allow:1; - /** reg_lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t lp_mm_hp_usbotg_allow:1; + /** lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * full-speed USB 2.0 OTG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_usbotg11_allow:1; - /** reg_lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t lp_mm_hp_usbotg11_allow:1; + /** lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * full-speed USB 2.0 OTG's wrap. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_usbotg11_wrap_allow:1; - /** reg_lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t lp_mm_hp_usbotg11_wrap_allow:1; + /** lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP DW-GDMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_gdma_allow:1; - /** reg_lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t lp_mm_hp_gdma_allow:1; + uint32_t reserved_4:1; + /** lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP SDMMC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_regdma_allow:1; - /** reg_lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t lp_mm_hp_sdmmc_allow:1; + /** lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access GDMA-AHB. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_sdmmc_allow:1; - /** reg_lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t lp_mm_hp_ahb_pdma_allow:1; + /** lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP JPEG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_ahb_pdma_allow:1; - /** reg_lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t lp_mm_hp_jpeg_allow:1; + /** lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PPA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_jpeg_allow:1; - /** reg_lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t lp_mm_hp_ppa_allow:1; + /** lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP 2D-DMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_ppa_allow:1; - /** reg_lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t lp_mm_hp_dma2d_allow:1; + /** lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP key + * manager. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_dma2d_allow:1; - /** reg_lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t lp_mm_hp_key_manager_allow:1; + /** lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP GDMA-AXI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_key_manager_allow:1; - /** reg_lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t lp_mm_hp_axi_pdma_allow:1; + /** lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP flash + * MSPI controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_axi_pdma_allow:1; - /** reg_lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t lp_mm_hp_flash_allow:1; + /** lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PSRAM + * MSPI controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_flash_allow:1; - /** reg_lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t lp_mm_hp_psram_allow:1; + /** lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP CRYPTO. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_psram_allow:1; - /** reg_lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t lp_mm_hp_crypto_allow:1; + /** lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP EMAC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_crypto_allow:1; - /** reg_lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t lp_mm_hp_gmac_allow:1; + /** lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * high-speed USB 2.0 OTG PHY. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_gmac_allow:1; - /** reg_lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t lp_mm_hp_usb_phy_allow:1; + /** lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PVT. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_lp_mm_hp_usb_phy_allow:1; - /** reg_lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t lp_mm_hp_pvt_allow:1; + /** lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP MIPI CSI + * host. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_pvt_allow:1; - /** reg_lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t lp_mm_hp_csi_host_allow:1; + /** lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP MIPI DSI + * host. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_csi_host_allow:1; - /** reg_lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t lp_mm_hp_dsi_host_allow:1; + /** lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP ISP. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_dsi_host_allow:1; - /** reg_lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1; - * NA + uint32_t lp_mm_hp_isp_allow:1; + /** lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP H264 + * Encoder. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_isp_allow:1; - /** reg_lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; - * NA + uint32_t lp_mm_hp_h264_core_allow:1; + /** lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP RMT. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_h264_core_allow:1; - /** reg_lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t lp_mm_hp_rmt_allow:1; + /** lp_mm_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP bit + * scrambler. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_rmt_allow:1; - /** reg_lp_mm_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t lp_mm_hp_bitscrambler_allow:1; + /** lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP AXI ICM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_bitscrambler_allow:1; - /** reg_lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t lp_mm_hp_axi_icm_allow:1; + /** lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access + * HP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_axi_icm_allow:1; - /** reg_lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; - * NA + uint32_t lp_mm_hp_peri_pms_allow:1; + /** lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access + * LP2HP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_peri_pms_allow:1; - /** reg_lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; - * NA + uint32_t lp_mm_lp2hp_peri_pms_allow:1; + /** lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access + * HP_DMA_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp2hp_peri_pms_allow:1; - /** reg_lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1; - * NA + uint32_t lp_mm_dma_pms_allow:1; + /** lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access 2D-DMA. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_dma_pms_allow:1; - /** reg_lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; - * NA + uint32_t lp_mm_hp_h264_dma2d_allow:1; + /** lp_mm_hp_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access AXI PERFMON. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_h264_dma2d_allow:1; - /** reg_lp_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t reg_lp_mm_axi_perf_mon_allow:1; + uint32_t lp_mm_hp_axi_perf_mon_allow:1; uint32_t reserved_30:2; }; uint32_t val; -} tee_lp_mm_pms_reg1_reg_t; +} pms_lp_mm_pms_reg1_reg_t; - -/** Group: TEE LP MM PMS REG2 REG */ /** Type of lp_mm_pms_reg2 register - * NA + * Permission control register2 for the LP CPU in machine mode */ typedef union { struct { - /** reg_lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; - * NA + /** lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP MCPWM0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_mcpwm0_allow:1; - /** reg_lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t lp_mm_hp_mcpwm0_allow:1; + /** lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP MCPWM1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_mcpwm1_allow:1; - /** reg_lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t lp_mm_hp_mcpwm1_allow:1; + /** lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP timer + * group0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_timer_group0_allow:1; - /** reg_lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t lp_mm_hp_timer_group0_allow:1; + /** lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP timer + * group1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_timer_group1_allow:1; - /** reg_lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t lp_mm_hp_timer_group1_allow:1; + /** lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2C0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_i2c0_allow:1; - /** reg_lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t lp_mm_hp_i2c0_allow:1; + /** lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2C1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_i2c1_allow:1; - /** reg_lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t lp_mm_hp_i2c1_allow:1; + /** lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2S0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_i2s0_allow:1; - /** reg_lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t lp_mm_hp_i2s0_allow:1; + /** lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2S1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_i2s1_allow:1; - /** reg_lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t lp_mm_hp_i2s1_allow:1; + /** lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2S2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_i2s2_allow:1; - /** reg_lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t lp_mm_hp_i2s2_allow:1; + /** lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PCNT. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_pcnt_allow:1; - /** reg_lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t lp_mm_hp_pcnt_allow:1; + /** lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_uart0_allow:1; - /** reg_lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t lp_mm_hp_uart0_allow:1; + /** lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_uart1_allow:1; - /** reg_lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t lp_mm_hp_uart1_allow:1; + /** lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_uart2_allow:1; - /** reg_lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t lp_mm_hp_uart2_allow:1; + /** lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART3. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_uart3_allow:1; - /** reg_lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t lp_mm_hp_uart3_allow:1; + /** lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART4. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_uart4_allow:1; - /** reg_lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t lp_mm_hp_uart4_allow:1; + /** lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PARLIO. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_parlio_allow:1; - /** reg_lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t lp_mm_hp_parlio_allow:1; + /** lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP GP-SPI2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_gpspi2_allow:1; - /** reg_lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t lp_mm_hp_gpspi2_allow:1; + /** lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP GP-SPI3. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_gpspi3_allow:1; - /** reg_lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t lp_mm_hp_gpspi3_allow:1; + /** lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * USB/Serial JTAG Controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_usbdevice_allow:1; - /** reg_lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t lp_mm_hp_usbdevice_allow:1; + /** lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP LEDC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_ledc_allow:1; + uint32_t lp_mm_hp_ledc_allow:1; uint32_t reserved_20:1; - /** reg_lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1; - * NA + /** lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP ETM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_etm_allow:1; - /** reg_lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t lp_mm_hp_etm_allow:1; + /** lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP interrupt + * matrix. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_intrmtx_allow:1; - /** reg_lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t lp_mm_hp_intrmtx_allow:1; + /** lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP TWAI0. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_twai0_allow:1; - /** reg_lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t lp_mm_hp_twai0_allow:1; + /** lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP TWAI1. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_twai1_allow:1; - /** reg_lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1; - * NA + uint32_t lp_mm_hp_twai1_allow:1; + /** lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP TWAI2. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_twai2_allow:1; - /** reg_lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; - * NA + uint32_t lp_mm_hp_twai2_allow:1; + /** lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I3C + * master controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_i3c_mst_allow:1; - /** reg_lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; - * NA + uint32_t lp_mm_hp_i3c_mst_allow:1; + /** lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I3C slave + * controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_i3c_slv_allow:1; - /** reg_lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; - * NA + uint32_t lp_mm_hp_i3c_slv_allow:1; + /** lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP LCD_CAM. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_lcdcam_allow:1; + uint32_t lp_mm_hp_lcdcam_allow:1; uint32_t reserved_29:1; - /** reg_lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1; - * NA + /** lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP ADC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_adc_allow:1; - /** reg_lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1; - * NA + uint32_t lp_mm_hp_adc_allow:1; + /** lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UHCI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_uhci_allow:1; + uint32_t lp_mm_hp_uhci_allow:1; }; uint32_t val; -} tee_lp_mm_pms_reg2_reg_t; +} pms_lp_mm_pms_reg2_reg_t; - -/** Group: TEE LP MM PMS REG3 REG */ /** Type of lp_mm_pms_reg3 register - * NA + * Permission control register3 for the LP CPU in machine mode */ typedef union { struct { - /** reg_lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1; - * NA + /** lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP GPIO + * Matrix. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_gpio_allow:1; - /** reg_lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t lp_mm_hp_gpio_allow:1; + /** lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP IO MUX. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_iomux_allow:1; - /** reg_lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t lp_mm_hp_iomux_allow:1; + /** lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP system + * timer. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_systimer_allow:1; - /** reg_lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t lp_mm_hp_systimer_allow:1; + /** lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP system + * register. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_sys_reg_allow:1; - /** reg_lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t lp_mm_hp_sys_reg_allow:1; + /** lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access + * HP_SYS_CLKRST. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp_clkrst_allow:1; + uint32_t lp_mm_hp_clkrst_allow:1; uint32_t reserved_5:27; }; uint32_t val; -} tee_lp_mm_pms_reg3_reg_t; +} pms_lp_mm_pms_reg3_reg_t; typedef struct { - volatile tee_lp2hp_pms_date_reg_t lp2hp_pms_date; - volatile tee_pms_clk_en_reg_t pms_clk_en; - volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0; + volatile pms_lp2hp_peri_pms_date_reg_t lp2hp_peri_pms_date; + volatile pms_lp2hp_peri_pms_clk_en_reg_t lp2hp_peri_pms_clk_en; + volatile pms_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0; uint32_t reserved_00c[9]; - volatile tee_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1; + volatile pms_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1; uint32_t reserved_034[28]; - volatile tee_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2; + volatile pms_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2; uint32_t reserved_0a8[29]; - volatile tee_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3; -} tee_dev_t; + volatile pms_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3; +} lp2hp_peri_pms_dev_t; -extern tee_dev_t LP2HP_PERI_PMS; +extern lp2hp_peri_pms_dev_t LP2HP_PERI_PMS; #ifndef __cplusplus -_Static_assert(sizeof(tee_dev_t) == 0x120, "Invalid size of tee_dev_t structure"); +_Static_assert(sizeof(lp2hp_peri_pms_dev_t) == 0x120, "Invalid size of lp2hp_peri_pms_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_eco5_reg.h deleted file mode 100644 index cffe2a23d16..00000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_eco5_reg.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 OR MIT - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** TEE_PMS_DATE_REG register - * NA - */ -#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0) -/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943; - * NA - */ -#define TEE_TEE_DATE 0xFFFFFFFFU -#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S) -#define TEE_TEE_DATE_V 0xFFFFFFFFU -#define TEE_TEE_DATE_S 0 - -/** TEE_PMS_CLK_EN_REG register - * NA - */ -#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4) -/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_CLK_EN (BIT(0)) -#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S) -#define TEE_REG_CLK_EN_V 0x00000001U -#define TEE_REG_CLK_EN_S 0 - -/** TEE_LP_MM_PMS_REG0_REG register - * NA - */ -#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8) -/** TEE_REG_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_SYSREG_ALLOW (BIT(0)) -#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_M (TEE_REG_LP_MM_LP_SYSREG_ALLOW_V << TEE_REG_LP_MM_LP_SYSREG_ALLOW_S) -#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_S 0 -/** TEE_REG_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW (BIT(1)) -#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S) -#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S 1 -/** TEE_REG_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_TIMER_ALLOW (BIT(2)) -#define TEE_REG_LP_MM_LP_TIMER_ALLOW_M (TEE_REG_LP_MM_LP_TIMER_ALLOW_V << TEE_REG_LP_MM_LP_TIMER_ALLOW_S) -#define TEE_REG_LP_MM_LP_TIMER_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_TIMER_ALLOW_S 2 -/** TEE_REG_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW (BIT(3)) -#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_M (TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V << TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S) -#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S 3 -/** TEE_REG_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_PMU_ALLOW (BIT(4)) -#define TEE_REG_LP_MM_LP_PMU_ALLOW_M (TEE_REG_LP_MM_LP_PMU_ALLOW_V << TEE_REG_LP_MM_LP_PMU_ALLOW_S) -#define TEE_REG_LP_MM_LP_PMU_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_PMU_ALLOW_S 4 -/** TEE_REG_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_WDT_ALLOW (BIT(5)) -#define TEE_REG_LP_MM_LP_WDT_ALLOW_M (TEE_REG_LP_MM_LP_WDT_ALLOW_V << TEE_REG_LP_MM_LP_WDT_ALLOW_S) -#define TEE_REG_LP_MM_LP_WDT_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_WDT_ALLOW_S 5 -/** TEE_REG_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW (BIT(6)) -#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_M (TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V << TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S) -#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S 6 -/** TEE_REG_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_RTC_ALLOW (BIT(7)) -#define TEE_REG_LP_MM_LP_RTC_ALLOW_M (TEE_REG_LP_MM_LP_RTC_ALLOW_V << TEE_REG_LP_MM_LP_RTC_ALLOW_S) -#define TEE_REG_LP_MM_LP_RTC_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_RTC_ALLOW_S 7 -/** TEE_REG_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW (BIT(8)) -#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S) -#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S 8 -/** TEE_REG_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_UART_ALLOW (BIT(9)) -#define TEE_REG_LP_MM_LP_UART_ALLOW_M (TEE_REG_LP_MM_LP_UART_ALLOW_V << TEE_REG_LP_MM_LP_UART_ALLOW_S) -#define TEE_REG_LP_MM_LP_UART_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_UART_ALLOW_S 9 -/** TEE_REG_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_I2C_ALLOW (BIT(10)) -#define TEE_REG_LP_MM_LP_I2C_ALLOW_M (TEE_REG_LP_MM_LP_I2C_ALLOW_V << TEE_REG_LP_MM_LP_I2C_ALLOW_S) -#define TEE_REG_LP_MM_LP_I2C_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_I2C_ALLOW_S 10 -/** TEE_REG_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_SPI_ALLOW (BIT(11)) -#define TEE_REG_LP_MM_LP_SPI_ALLOW_M (TEE_REG_LP_MM_LP_SPI_ALLOW_V << TEE_REG_LP_MM_LP_SPI_ALLOW_S) -#define TEE_REG_LP_MM_LP_SPI_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_SPI_ALLOW_S 11 -/** TEE_REG_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_I2CMST_ALLOW (BIT(12)) -#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_M (TEE_REG_LP_MM_LP_I2CMST_ALLOW_V << TEE_REG_LP_MM_LP_I2CMST_ALLOW_S) -#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_S 12 -/** TEE_REG_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_I2S_ALLOW (BIT(13)) -#define TEE_REG_LP_MM_LP_I2S_ALLOW_M (TEE_REG_LP_MM_LP_I2S_ALLOW_V << TEE_REG_LP_MM_LP_I2S_ALLOW_S) -#define TEE_REG_LP_MM_LP_I2S_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_I2S_ALLOW_S 13 -/** TEE_REG_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_ADC_ALLOW (BIT(14)) -#define TEE_REG_LP_MM_LP_ADC_ALLOW_M (TEE_REG_LP_MM_LP_ADC_ALLOW_V << TEE_REG_LP_MM_LP_ADC_ALLOW_S) -#define TEE_REG_LP_MM_LP_ADC_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_ADC_ALLOW_S 14 -/** TEE_REG_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_TOUCH_ALLOW (BIT(15)) -#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_M (TEE_REG_LP_MM_LP_TOUCH_ALLOW_V << TEE_REG_LP_MM_LP_TOUCH_ALLOW_S) -#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_S 15 -/** TEE_REG_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_IOMUX_ALLOW (BIT(16)) -#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_M (TEE_REG_LP_MM_LP_IOMUX_ALLOW_V << TEE_REG_LP_MM_LP_IOMUX_ALLOW_S) -#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_S 16 -/** TEE_REG_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_INTR_ALLOW (BIT(17)) -#define TEE_REG_LP_MM_LP_INTR_ALLOW_M (TEE_REG_LP_MM_LP_INTR_ALLOW_V << TEE_REG_LP_MM_LP_INTR_ALLOW_S) -#define TEE_REG_LP_MM_LP_INTR_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_INTR_ALLOW_S 17 -/** TEE_REG_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_EFUSE_ALLOW (BIT(18)) -#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_M (TEE_REG_LP_MM_LP_EFUSE_ALLOW_V << TEE_REG_LP_MM_LP_EFUSE_ALLOW_S) -#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_S 18 -/** TEE_REG_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_PMS_ALLOW (BIT(19)) -#define TEE_REG_LP_MM_LP_PMS_ALLOW_M (TEE_REG_LP_MM_LP_PMS_ALLOW_V << TEE_REG_LP_MM_LP_PMS_ALLOW_S) -#define TEE_REG_LP_MM_LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_PMS_ALLOW_S 19 -/** TEE_REG_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW (BIT(20)) -#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_M (TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V << TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S) -#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S 20 -/** TEE_REG_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_TSENS_ALLOW (BIT(21)) -#define TEE_REG_LP_MM_LP_TSENS_ALLOW_M (TEE_REG_LP_MM_LP_TSENS_ALLOW_V << TEE_REG_LP_MM_LP_TSENS_ALLOW_S) -#define TEE_REG_LP_MM_LP_TSENS_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_TSENS_ALLOW_S 21 -/** TEE_REG_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_HUK_ALLOW (BIT(22)) -#define TEE_REG_LP_MM_LP_HUK_ALLOW_M (TEE_REG_LP_MM_LP_HUK_ALLOW_V << TEE_REG_LP_MM_LP_HUK_ALLOW_S) -#define TEE_REG_LP_MM_LP_HUK_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_HUK_ALLOW_S 22 -/** TEE_REG_LP_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW (BIT(23)) -#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S) -#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S 23 -/** TEE_REG_LP_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; - * NA - */ -#define TEE_REG_LP_MM_LP_TRNG_ALLOW (BIT(24)) -#define TEE_REG_LP_MM_LP_TRNG_ALLOW_M (TEE_REG_LP_MM_LP_TRNG_ALLOW_V << TEE_REG_LP_MM_LP_TRNG_ALLOW_S) -#define TEE_REG_LP_MM_LP_TRNG_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_LP_TRNG_ALLOW_S 24 - -/** TEE_PERI_REGION0_LOW_REG register - * NA - */ -#define TEE_PERI_REGION0_LOW_REG (DR_REG_TEE_BASE + 0xc) -/** TEE_REG_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0; - * NA - */ -#define TEE_REG_PERI_REGION0_LOW 0x3FFFFFFFU -#define TEE_REG_PERI_REGION0_LOW_M (TEE_REG_PERI_REGION0_LOW_V << TEE_REG_PERI_REGION0_LOW_S) -#define TEE_REG_PERI_REGION0_LOW_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION0_LOW_S 2 - -/** TEE_PERI_REGION0_HIGH_REG register - * NA - */ -#define TEE_PERI_REGION0_HIGH_REG (DR_REG_TEE_BASE + 0x10) -/** TEE_REG_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ -#define TEE_REG_PERI_REGION0_HIGH 0x3FFFFFFFU -#define TEE_REG_PERI_REGION0_HIGH_M (TEE_REG_PERI_REGION0_HIGH_V << TEE_REG_PERI_REGION0_HIGH_S) -#define TEE_REG_PERI_REGION0_HIGH_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION0_HIGH_S 2 - -/** TEE_PERI_REGION1_LOW_REG register - * NA - */ -#define TEE_PERI_REGION1_LOW_REG (DR_REG_TEE_BASE + 0x14) -/** TEE_REG_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0; - * NA - */ -#define TEE_REG_PERI_REGION1_LOW 0x3FFFFFFFU -#define TEE_REG_PERI_REGION1_LOW_M (TEE_REG_PERI_REGION1_LOW_V << TEE_REG_PERI_REGION1_LOW_S) -#define TEE_REG_PERI_REGION1_LOW_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION1_LOW_S 2 - -/** TEE_PERI_REGION1_HIGH_REG register - * NA - */ -#define TEE_PERI_REGION1_HIGH_REG (DR_REG_TEE_BASE + 0x18) -/** TEE_REG_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ -#define TEE_REG_PERI_REGION1_HIGH 0x3FFFFFFFU -#define TEE_REG_PERI_REGION1_HIGH_M (TEE_REG_PERI_REGION1_HIGH_V << TEE_REG_PERI_REGION1_HIGH_S) -#define TEE_REG_PERI_REGION1_HIGH_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION1_HIGH_S 2 - -/** TEE_PERI_REGION_PMS_REG register - * NA - */ -#define TEE_PERI_REGION_PMS_REG (DR_REG_TEE_BASE + 0x1c) -/** TEE_REG_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3; - * NA - */ -#define TEE_REG_LP_CORE_REGION_PMS 0x00000003U -#define TEE_REG_LP_CORE_REGION_PMS_M (TEE_REG_LP_CORE_REGION_PMS_V << TEE_REG_LP_CORE_REGION_PMS_S) -#define TEE_REG_LP_CORE_REGION_PMS_V 0x00000003U -#define TEE_REG_LP_CORE_REGION_PMS_S 0 -/** TEE_REG_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3; - * NA - */ -#define TEE_REG_HP_CORE0_UM_REGION_PMS 0x00000003U -#define TEE_REG_HP_CORE0_UM_REGION_PMS_M (TEE_REG_HP_CORE0_UM_REGION_PMS_V << TEE_REG_HP_CORE0_UM_REGION_PMS_S) -#define TEE_REG_HP_CORE0_UM_REGION_PMS_V 0x00000003U -#define TEE_REG_HP_CORE0_UM_REGION_PMS_S 2 -/** TEE_REG_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3; - * NA - */ -#define TEE_REG_HP_CORE0_MM_REGION_PMS 0x00000003U -#define TEE_REG_HP_CORE0_MM_REGION_PMS_M (TEE_REG_HP_CORE0_MM_REGION_PMS_V << TEE_REG_HP_CORE0_MM_REGION_PMS_S) -#define TEE_REG_HP_CORE0_MM_REGION_PMS_V 0x00000003U -#define TEE_REG_HP_CORE0_MM_REGION_PMS_S 4 -/** TEE_REG_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3; - * NA - */ -#define TEE_REG_HP_CORE1_UM_REGION_PMS 0x00000003U -#define TEE_REG_HP_CORE1_UM_REGION_PMS_M (TEE_REG_HP_CORE1_UM_REGION_PMS_V << TEE_REG_HP_CORE1_UM_REGION_PMS_S) -#define TEE_REG_HP_CORE1_UM_REGION_PMS_V 0x00000003U -#define TEE_REG_HP_CORE1_UM_REGION_PMS_S 6 -/** TEE_REG_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3; - * NA - */ -#define TEE_REG_HP_CORE1_MM_REGION_PMS 0x00000003U -#define TEE_REG_HP_CORE1_MM_REGION_PMS_M (TEE_REG_HP_CORE1_MM_REGION_PMS_V << TEE_REG_HP_CORE1_MM_REGION_PMS_S) -#define TEE_REG_HP_CORE1_MM_REGION_PMS_V 0x00000003U -#define TEE_REG_HP_CORE1_MM_REGION_PMS_S 8 - -/** TEE_PERI_REGION_2_TO_7_PMS_REG register - * NA - */ -#define TEE_PERI_REGION_2_TO_7_PMS_REG (DR_REG_TEE_BASE + 0x20) -/** TEE_REG_LP_CORE_REGION_2_TO_7_PMS : R/W; bitpos: [5:0]; default: 63; - * NA - */ -#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS 0x0000003FU -#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_M (TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V << TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S) -#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V 0x0000003FU -#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S 0 -/** TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS : R/W; bitpos: [11:6]; default: 63; - * NA - */ -#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS 0x0000003FU -#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S) -#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V 0x0000003FU -#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S 6 -/** TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS : R/W; bitpos: [17:12]; default: 63; - * NA - */ -#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS 0x0000003FU -#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S) -#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V 0x0000003FU -#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S 12 -/** TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS : R/W; bitpos: [23:18]; default: 63; - * NA - */ -#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS 0x0000003FU -#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S) -#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V 0x0000003FU -#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S 18 -/** TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS : R/W; bitpos: [29:24]; default: 63; - * NA - */ -#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS 0x0000003FU -#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S) -#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V 0x0000003FU -#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S 24 - -/** TEE_PERI_REGION2_LOW_REG register - * NA - */ -#define TEE_PERI_REGION2_LOW_REG (DR_REG_TEE_BASE + 0x24) -/** TEE_REG_PERI_REGION2_LOW : R/W; bitpos: [31:2]; default: 0; - * NA - */ -#define TEE_REG_PERI_REGION2_LOW 0x3FFFFFFFU -#define TEE_REG_PERI_REGION2_LOW_M (TEE_REG_PERI_REGION2_LOW_V << TEE_REG_PERI_REGION2_LOW_S) -#define TEE_REG_PERI_REGION2_LOW_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION2_LOW_S 2 - -/** TEE_PERI_REGION2_HIGH_REG register - * NA - */ -#define TEE_PERI_REGION2_HIGH_REG (DR_REG_TEE_BASE + 0x28) -/** TEE_REG_PERI_REGION2_HIGH : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ -#define TEE_REG_PERI_REGION2_HIGH 0x3FFFFFFFU -#define TEE_REG_PERI_REGION2_HIGH_M (TEE_REG_PERI_REGION2_HIGH_V << TEE_REG_PERI_REGION2_HIGH_S) -#define TEE_REG_PERI_REGION2_HIGH_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION2_HIGH_S 2 - -/** TEE_PERI_REGION3_LOW_REG register - * NA - */ -#define TEE_PERI_REGION3_LOW_REG (DR_REG_TEE_BASE + 0x2c) -/** TEE_REG_PERI_REGION3_LOW : R/W; bitpos: [31:2]; default: 0; - * NA - */ -#define TEE_REG_PERI_REGION3_LOW 0x3FFFFFFFU -#define TEE_REG_PERI_REGION3_LOW_M (TEE_REG_PERI_REGION3_LOW_V << TEE_REG_PERI_REGION3_LOW_S) -#define TEE_REG_PERI_REGION3_LOW_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION3_LOW_S 2 - -/** TEE_PERI_REGION3_HIGH_REG register - * NA - */ -#define TEE_PERI_REGION3_HIGH_REG (DR_REG_TEE_BASE + 0x30) -/** TEE_REG_PERI_REGION3_HIGH : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ -#define TEE_REG_PERI_REGION3_HIGH 0x3FFFFFFFU -#define TEE_REG_PERI_REGION3_HIGH_M (TEE_REG_PERI_REGION3_HIGH_V << TEE_REG_PERI_REGION3_HIGH_S) -#define TEE_REG_PERI_REGION3_HIGH_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION3_HIGH_S 2 - -/** TEE_PERI_REGION4_LOW_REG register - * NA - */ -#define TEE_PERI_REGION4_LOW_REG (DR_REG_TEE_BASE + 0x34) -/** TEE_REG_PERI_REGION4_LOW : R/W; bitpos: [31:2]; default: 0; - * NA - */ -#define TEE_REG_PERI_REGION4_LOW 0x3FFFFFFFU -#define TEE_REG_PERI_REGION4_LOW_M (TEE_REG_PERI_REGION4_LOW_V << TEE_REG_PERI_REGION4_LOW_S) -#define TEE_REG_PERI_REGION4_LOW_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION4_LOW_S 2 - -/** TEE_PERI_REGION4_HIGH_REG register - * NA - */ -#define TEE_PERI_REGION4_HIGH_REG (DR_REG_TEE_BASE + 0x38) -/** TEE_REG_PERI_REGION4_HIGH : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ -#define TEE_REG_PERI_REGION4_HIGH 0x3FFFFFFFU -#define TEE_REG_PERI_REGION4_HIGH_M (TEE_REG_PERI_REGION4_HIGH_V << TEE_REG_PERI_REGION4_HIGH_S) -#define TEE_REG_PERI_REGION4_HIGH_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION4_HIGH_S 2 - -/** TEE_PERI_REGION5_LOW_REG register - * NA - */ -#define TEE_PERI_REGION5_LOW_REG (DR_REG_TEE_BASE + 0x3c) -/** TEE_REG_PERI_REGION5_LOW : R/W; bitpos: [31:2]; default: 0; - * NA - */ -#define TEE_REG_PERI_REGION5_LOW 0x3FFFFFFFU -#define TEE_REG_PERI_REGION5_LOW_M (TEE_REG_PERI_REGION5_LOW_V << TEE_REG_PERI_REGION5_LOW_S) -#define TEE_REG_PERI_REGION5_LOW_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION5_LOW_S 2 - -/** TEE_PERI_REGION5_HIGH_REG register - * NA - */ -#define TEE_PERI_REGION5_HIGH_REG (DR_REG_TEE_BASE + 0x40) -/** TEE_REG_PERI_REGION5_HIGH : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ -#define TEE_REG_PERI_REGION5_HIGH 0x3FFFFFFFU -#define TEE_REG_PERI_REGION5_HIGH_M (TEE_REG_PERI_REGION5_HIGH_V << TEE_REG_PERI_REGION5_HIGH_S) -#define TEE_REG_PERI_REGION5_HIGH_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION5_HIGH_S 2 - -/** TEE_PERI_REGION6_LOW_REG register - * NA - */ -#define TEE_PERI_REGION6_LOW_REG (DR_REG_TEE_BASE + 0x44) -/** TEE_REG_PERI_REGION6_LOW : R/W; bitpos: [31:2]; default: 0; - * NA - */ -#define TEE_REG_PERI_REGION6_LOW 0x3FFFFFFFU -#define TEE_REG_PERI_REGION6_LOW_M (TEE_REG_PERI_REGION6_LOW_V << TEE_REG_PERI_REGION6_LOW_S) -#define TEE_REG_PERI_REGION6_LOW_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION6_LOW_S 2 - -/** TEE_PERI_REGION6_HIGH_REG register - * NA - */ -#define TEE_PERI_REGION6_HIGH_REG (DR_REG_TEE_BASE + 0x48) -/** TEE_REG_PERI_REGION6_HIGH : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ -#define TEE_REG_PERI_REGION6_HIGH 0x3FFFFFFFU -#define TEE_REG_PERI_REGION6_HIGH_M (TEE_REG_PERI_REGION6_HIGH_V << TEE_REG_PERI_REGION6_HIGH_S) -#define TEE_REG_PERI_REGION6_HIGH_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION6_HIGH_S 2 - -/** TEE_PERI_REGION7_LOW_REG register - * NA - */ -#define TEE_PERI_REGION7_LOW_REG (DR_REG_TEE_BASE + 0x4c) -/** TEE_REG_PERI_REGION7_LOW : R/W; bitpos: [31:2]; default: 0; - * NA - */ -#define TEE_REG_PERI_REGION7_LOW 0x3FFFFFFFU -#define TEE_REG_PERI_REGION7_LOW_M (TEE_REG_PERI_REGION7_LOW_V << TEE_REG_PERI_REGION7_LOW_S) -#define TEE_REG_PERI_REGION7_LOW_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION7_LOW_S 2 - -/** TEE_PERI_REGION7_HIGH_REG register - * NA - */ -#define TEE_PERI_REGION7_HIGH_REG (DR_REG_TEE_BASE + 0x50) -/** TEE_REG_PERI_REGION7_HIGH : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ -#define TEE_REG_PERI_REGION7_HIGH 0x3FFFFFFFU -#define TEE_REG_PERI_REGION7_HIGH_M (TEE_REG_PERI_REGION7_HIGH_V << TEE_REG_PERI_REGION7_HIGH_S) -#define TEE_REG_PERI_REGION7_HIGH_V 0x3FFFFFFFU -#define TEE_REG_PERI_REGION7_HIGH_S 2 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_reg.h index d2844d770ec..20630332edb 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { * Version control register */ #define PMS_LP_PERI_PMS_DATE_REG (DR_REG_LP_PERI_PMS_BASE + 0x0) -/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537; +/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2363943; * Version control register */ #define PMS_LP_PERI_PMS_DATE 0xFFFFFFFFU @@ -267,6 +267,15 @@ extern "C" { #define PMS_LP_MM_LP_SRAM_ALLOW_M (PMS_LP_MM_LP_SRAM_ALLOW_V << PMS_LP_MM_LP_SRAM_ALLOW_S) #define PMS_LP_MM_LP_SRAM_ALLOW_V 0x00000001U #define PMS_LP_MM_LP_SRAM_ALLOW_S 23 +/** PMS_LP_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; + * Configures whether LP CPU in machine mode has permission to access RNG. + * 0: Not allowed + * 1: Allow + */ +#define PMS_LP_MM_LP_TRNG_ALLOW (BIT(24)) +#define PMS_LP_MM_LP_TRNG_ALLOW_M (PMS_LP_MM_LP_TRNG_ALLOW_V << PMS_LP_MM_LP_TRNG_ALLOW_S) +#define PMS_LP_MM_LP_TRNG_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_TRNG_ALLOW_S 24 /** PMS_PERI_REGION0_LOW_REG register * Region0 start address configuration register @@ -371,6 +380,205 @@ extern "C" { #define PMS_HP_CORE1_MM_REGION_PMS_V 0x00000003U #define PMS_HP_CORE1_MM_REGION_PMS_S 8 +/** PMS_PERI_REGION_2_TO_7_PMS_REG register + * Permission register of region 2 to 7 + */ +#define PMS_PERI_REGION_2_TO_7_PMS_REG (DR_REG_LP_PERI_PMS_BASE + 0x20) +/** PMS_LP_CORE_REGION_2_TO_7_PMS : R/W; bitpos: [5:0]; default: 63; + * Configures whether LP core in machine mode has permission to access address region2 + * to region7. Bit0 corresponds to region2, bit1 to region3, ..., bit5 to region7. + * 0: Not allowed + * 1: Allow + */ +#define PMS_LP_CORE_REGION_2_TO_7_PMS 0x0000003FU +#define PMS_LP_CORE_REGION_2_TO_7_PMS_M (PMS_LP_CORE_REGION_2_TO_7_PMS_V << PMS_LP_CORE_REGION_2_TO_7_PMS_S) +#define PMS_LP_CORE_REGION_2_TO_7_PMS_V 0x0000003FU +#define PMS_LP_CORE_REGION_2_TO_7_PMS_S 0 +/** PMS_HP_CORE0_UM_REGION_2_TO_7_PMS : R/W; bitpos: [11:6]; default: 63; + * Configures whether HP CPU0 in user mode has permission to access address region2 + * to region7. Bit6 corresponds to region2, bit7 to region3, ..., bit11 to region7. + * 0: Not allowed + * 1: Allow + */ +#define PMS_HP_CORE0_UM_REGION_2_TO_7_PMS 0x0000003FU +#define PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_M (PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_V << PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_S) +#define PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_V 0x0000003FU +#define PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_S 6 +/** PMS_HP_CORE0_MM_REGION_2_TO_7_PMS : R/W; bitpos: [17:12]; default: 63; + * Configures whether HP CPU0 in machine mode has permission to access address region2 + * to region7. Bit12 corresponds to region2, bit13 to region3, ..., bit17 to region7. + * 0: Not allowed + * 1: Allow + */ +#define PMS_HP_CORE0_MM_REGION_2_TO_7_PMS 0x0000003FU +#define PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_M (PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_V << PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_S) +#define PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_V 0x0000003FU +#define PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_S 12 +/** PMS_HP_CORE1_UM_REGION_2_TO_7_PMS : R/W; bitpos: [23:18]; default: 63; + * Configures whether HP CPU1 in user mode has permission to access address region2 + * to region7. Bit18 corresponds to region2, bit19 to region3, ..., bit23 to region7. + * 0: Not allowed + * 1: Allow + */ +#define PMS_HP_CORE1_UM_REGION_2_TO_7_PMS 0x0000003FU +#define PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_M (PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_V << PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_S) +#define PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_V 0x0000003FU +#define PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_S 18 +/** PMS_HP_CORE1_MM_REGION_2_TO_7_PMS : R/W; bitpos: [29:24]; default: 63; + * Configures whether HP CPU1 in machine mode has permission to access address region2 + * to region7. Bit24 corresponds to region2, bit25 to region3, ..., bit29 to region7. + * 0: Not allowed + * 1: Allow + */ +#define PMS_HP_CORE1_MM_REGION_2_TO_7_PMS 0x0000003FU +#define PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_M (PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_V << PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_S) +#define PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_V 0x0000003FU +#define PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_S 24 + +/** PMS_PERI_REGION2_LOW_REG register + * Region2 start address configuration register + */ +#define PMS_PERI_REGION2_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x24) +/** PMS_PERI_REGION2_LOW : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's region2. + */ +#define PMS_PERI_REGION2_LOW 0x3FFFFFFFU +#define PMS_PERI_REGION2_LOW_M (PMS_PERI_REGION2_LOW_V << PMS_PERI_REGION2_LOW_S) +#define PMS_PERI_REGION2_LOW_V 0x3FFFFFFFU +#define PMS_PERI_REGION2_LOW_S 2 + +/** PMS_PERI_REGION2_HIGH_REG register + * Region2 end address configuration register + */ +#define PMS_PERI_REGION2_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x28) +/** PMS_PERI_REGION2_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's region2. + */ +#define PMS_PERI_REGION2_HIGH 0x3FFFFFFFU +#define PMS_PERI_REGION2_HIGH_M (PMS_PERI_REGION2_HIGH_V << PMS_PERI_REGION2_HIGH_S) +#define PMS_PERI_REGION2_HIGH_V 0x3FFFFFFFU +#define PMS_PERI_REGION2_HIGH_S 2 + +/** PMS_PERI_REGION3_LOW_REG register + * Region3 start address configuration register + */ +#define PMS_PERI_REGION3_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x2c) +/** PMS_PERI_REGION3_LOW : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's region3. + */ +#define PMS_PERI_REGION3_LOW 0x3FFFFFFFU +#define PMS_PERI_REGION3_LOW_M (PMS_PERI_REGION3_LOW_V << PMS_PERI_REGION3_LOW_S) +#define PMS_PERI_REGION3_LOW_V 0x3FFFFFFFU +#define PMS_PERI_REGION3_LOW_S 2 + +/** PMS_PERI_REGION3_HIGH_REG register + * Region3 end address configuration register + */ +#define PMS_PERI_REGION3_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x30) +/** PMS_PERI_REGION3_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's region3. + */ +#define PMS_PERI_REGION3_HIGH 0x3FFFFFFFU +#define PMS_PERI_REGION3_HIGH_M (PMS_PERI_REGION3_HIGH_V << PMS_PERI_REGION3_HIGH_S) +#define PMS_PERI_REGION3_HIGH_V 0x3FFFFFFFU +#define PMS_PERI_REGION3_HIGH_S 2 + +/** PMS_PERI_REGION4_LOW_REG register + * Region4 start address configuration register + */ +#define PMS_PERI_REGION4_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x34) +/** PMS_PERI_REGION4_LOW : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's region4. + */ +#define PMS_PERI_REGION4_LOW 0x3FFFFFFFU +#define PMS_PERI_REGION4_LOW_M (PMS_PERI_REGION4_LOW_V << PMS_PERI_REGION4_LOW_S) +#define PMS_PERI_REGION4_LOW_V 0x3FFFFFFFU +#define PMS_PERI_REGION4_LOW_S 2 + +/** PMS_PERI_REGION4_HIGH_REG register + * Region4 end address configuration register + */ +#define PMS_PERI_REGION4_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x38) +/** PMS_PERI_REGION4_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's region4. + */ +#define PMS_PERI_REGION4_HIGH 0x3FFFFFFFU +#define PMS_PERI_REGION4_HIGH_M (PMS_PERI_REGION4_HIGH_V << PMS_PERI_REGION4_HIGH_S) +#define PMS_PERI_REGION4_HIGH_V 0x3FFFFFFFU +#define PMS_PERI_REGION4_HIGH_S 2 + +/** PMS_PERI_REGION5_LOW_REG register + * Region5 start address configuration register + */ +#define PMS_PERI_REGION5_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x3c) +/** PMS_PERI_REGION5_LOW : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's region5. + */ +#define PMS_PERI_REGION5_LOW 0x3FFFFFFFU +#define PMS_PERI_REGION5_LOW_M (PMS_PERI_REGION5_LOW_V << PMS_PERI_REGION5_LOW_S) +#define PMS_PERI_REGION5_LOW_V 0x3FFFFFFFU +#define PMS_PERI_REGION5_LOW_S 2 + +/** PMS_PERI_REGION5_HIGH_REG register + * Region5 end address configuration register + */ +#define PMS_PERI_REGION5_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x40) +/** PMS_PERI_REGION5_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's region5. + */ +#define PMS_PERI_REGION5_HIGH 0x3FFFFFFFU +#define PMS_PERI_REGION5_HIGH_M (PMS_PERI_REGION5_HIGH_V << PMS_PERI_REGION5_HIGH_S) +#define PMS_PERI_REGION5_HIGH_V 0x3FFFFFFFU +#define PMS_PERI_REGION5_HIGH_S 2 + +/** PMS_PERI_REGION6_LOW_REG register + * Region6 start address configuration register + */ +#define PMS_PERI_REGION6_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x44) +/** PMS_PERI_REGION6_LOW : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's region6. + */ +#define PMS_PERI_REGION6_LOW 0x3FFFFFFFU +#define PMS_PERI_REGION6_LOW_M (PMS_PERI_REGION6_LOW_V << PMS_PERI_REGION6_LOW_S) +#define PMS_PERI_REGION6_LOW_V 0x3FFFFFFFU +#define PMS_PERI_REGION6_LOW_S 2 + +/** PMS_PERI_REGION6_HIGH_REG register + * Region6 end address configuration register + */ +#define PMS_PERI_REGION6_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x48) +/** PMS_PERI_REGION6_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's region6. + */ +#define PMS_PERI_REGION6_HIGH 0x3FFFFFFFU +#define PMS_PERI_REGION6_HIGH_M (PMS_PERI_REGION6_HIGH_V << PMS_PERI_REGION6_HIGH_S) +#define PMS_PERI_REGION6_HIGH_V 0x3FFFFFFFU +#define PMS_PERI_REGION6_HIGH_S 2 + +/** PMS_PERI_REGION7_LOW_REG register + * Region7 start address configuration register + */ +#define PMS_PERI_REGION7_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x4c) +/** PMS_PERI_REGION7_LOW : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's region7. + */ +#define PMS_PERI_REGION7_LOW 0x3FFFFFFFU +#define PMS_PERI_REGION7_LOW_M (PMS_PERI_REGION7_LOW_V << PMS_PERI_REGION7_LOW_S) +#define PMS_PERI_REGION7_LOW_V 0x3FFFFFFFU +#define PMS_PERI_REGION7_LOW_S 2 + +/** PMS_PERI_REGION7_HIGH_REG register + * Region7 end address configuration register + */ +#define PMS_PERI_REGION7_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x50) +/** PMS_PERI_REGION7_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's region7. + */ +#define PMS_PERI_REGION7_HIGH 0x3FFFFFFFU +#define PMS_PERI_REGION7_HIGH_M (PMS_PERI_REGION7_HIGH_V << PMS_PERI_REGION7_HIGH_S) +#define PMS_PERI_REGION7_HIGH_V 0x3FFFFFFFU +#define PMS_PERI_REGION7_HIGH_S 2 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_struct.h index dea648ca5bf..0236531f8a1 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_struct.h @@ -10,497 +10,362 @@ extern "C" { #endif -/** Group: TEE PMS DATE REG */ -/** Type of pms_date register - * NA +/** Group: Version Control Registers */ +/** Type of lp_peri_pms_date register + * Version control register */ typedef union { struct { - /** tee_date : R/W; bitpos: [31:0]; default: 2363943; - * NA + /** lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2363943; + * Version control register */ - uint32_t tee_date:32; + uint32_t lp_peri_pms_date:32; }; uint32_t val; -} tee_pms_date_reg_t; +} pms_lp_peri_pms_date_reg_t; -/** Group: TEE PMS CLK EN REG */ -/** Type of pms_clk_en register - * NA +/** Group: Clock Gating Registers */ +/** Type of lp_peri_pms_clk_en register + * Clock gating register */ typedef union { struct { - /** reg_clk_en : R/W; bitpos: [0]; default: 1; - * NA + /** lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ - uint32_t reg_clk_en:1; + uint32_t lp_peri_pms_clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} tee_pms_clk_en_reg_t; +} pms_lp_peri_pms_clk_en_reg_t; -/** Group: TEE LP MM PMS REG0 REG */ -/** Type of lp_mm_pms_reg0 register - * NA +/** Group: LP CPU Permission Control Registers */ +/** Type of lp_mm_lp_peri_pms_reg0 register + * Permission control register0 for LP CPU in machine mode */ typedef union { struct { - /** reg_lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; - * NA + /** lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP system + * registers. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_sysreg_allow:1; - /** reg_lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; - * NA + uint32_t lp_mm_lp_sysreg_allow:1; + /** lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP + * always-on clock and reset). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_aonclkrst_allow:1; - /** reg_lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1; - * NA + uint32_t lp_mm_lp_aonclkrst_allow:1; + /** lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP timer. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_timer_allow:1; - /** reg_lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; - * NA + uint32_t lp_mm_lp_timer_allow:1; + /** lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP ANAPERI + * (analog peripherals). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_anaperi_allow:1; - /** reg_lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1; - * NA + uint32_t lp_mm_lp_anaperi_allow:1; + /** lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP PMU (Power + * Management Unit). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_pmu_allow:1; - /** reg_lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1; - * NA + uint32_t lp_mm_lp_pmu_allow:1; + /** lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog + * timer). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_wdt_allow:1; - /** reg_lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; - * NA + uint32_t lp_mm_lp_wdt_allow:1; + /** lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP Mailbox + * Controller. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_mailbox_allow:1; - /** reg_lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1; - * NA + uint32_t lp_mm_lp_mailbox_allow:1; + /** lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP RTC. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_lp_mm_lp_rtc_allow:1; - /** reg_lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; - * NA + uint32_t lp_mm_lp_rtc_allow:1; + /** lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP PREICLKRST + * (peripheral clock and reset). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_periclkrst_allow:1; - /** reg_lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1; - * NA + uint32_t lp_mm_lp_periclkrst_allow:1; + /** lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP UART. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_uart_allow:1; - /** reg_lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1; - * NA + uint32_t lp_mm_lp_uart_allow:1; + /** lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP I2S. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_i2c_allow:1; - /** reg_lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1; - * NA + uint32_t lp_mm_lp_i2c_allow:1; + /** lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP SPI. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_spi_allow:1; - /** reg_lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; - * NA + uint32_t lp_mm_lp_spi_allow:1; + /** lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP I2C master. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_i2cmst_allow:1; - /** reg_lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1; - * NA + uint32_t lp_mm_lp_i2cmst_allow:1; + /** lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP I2S. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_i2s_allow:1; - /** reg_lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1; - * NA + uint32_t lp_mm_lp_i2s_allow:1; + /** lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP ADC. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_adc_allow:1; - /** reg_lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1; - * NA + uint32_t lp_mm_lp_adc_allow:1; + /** lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP touch sensor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_touch_allow:1; - /** reg_lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1; - * NA + uint32_t lp_mm_lp_touch_allow:1; + /** lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP IO MUX. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_iomux_allow:1; - /** reg_lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1; - * NA + uint32_t lp_mm_lp_iomux_allow:1; + /** lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP INTR + * (interrupt). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_intr_allow:1; - /** reg_lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1; - * NA + uint32_t lp_mm_lp_intr_allow:1; + /** lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP eFuse. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_efuse_allow:1; - /** reg_lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1; - * NA + uint32_t lp_mm_lp_efuse_allow:1; + /** lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_pms_allow:1; - /** reg_lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; - * NA + uint32_t lp_mm_lp_pms_allow:1; + /** lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; + * Configures whether LP CPU in machine mode has permission to access + * HP2LP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_hp2lp_pms_allow:1; - /** reg_lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1; - * NA + uint32_t lp_mm_hp2lp_pms_allow:1; + /** lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP temperature + * sensor. + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_tsens_allow:1; - /** reg_lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1; - * NA + uint32_t lp_mm_lp_tsens_allow:1; + /** lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware + * Unique Key). + * 0: Not allowed + * 1: Allowed */ - uint32_t reg_lp_mm_lp_huk_allow:1; - /** reg_lp_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1; - * NA + uint32_t lp_mm_lp_huk_allow:1; + /** lp_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP SRAM. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_lp_mm_lp_tcm_ram_allow:1; - /** reg_lp_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1; - * NA + uint32_t lp_mm_lp_sram_allow:1; + /** lp_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1; + * Configures whether LP CPU in machine mode has permission to access RNG. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_lp_mm_lp_trng_allow:1; + uint32_t lp_mm_lp_trng_allow:1; uint32_t reserved_25:7; }; uint32_t val; -} tee_lp_mm_pms_reg0_reg_t; +} pms_lp_mm_lp_peri_pms_reg0_reg_t; -/** Group: TEE PERI REGION0 LOW REG */ -/** Type of peri_region0_low register - * NA +/** Group: Configurable Address Range Configuration Registers */ +/** Type of peri_regionn_low register + * Regionn start address configuration register */ typedef union { struct { uint32_t reserved_0:2; - /** reg_peri_region0_low : R/W; bitpos: [31:2]; default: 0; - * NA + /** peri_regionn_low : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's regionn. */ - uint32_t reg_peri_region0_low:30; + uint32_t peri_regionn_low:30; }; uint32_t val; -} tee_peri_region0_low_reg_t; +} pms_peri_regionn_low_reg_t; - -/** Group: TEE PERI REGION0 HIGH REG */ -/** Type of peri_region0_high register - * NA +/** Type of peri_regionn_high register + * Regionn end address configuration register */ typedef union { struct { uint32_t reserved_0:2; - /** reg_peri_region0_high : R/W; bitpos: [31:2]; default: 1073741823; - * NA + /** peri_regionn_high : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's regionn. */ - uint32_t reg_peri_region0_high:30; + uint32_t peri_regionn_high:30; }; uint32_t val; -} tee_peri_region0_high_reg_t; +} pms_peri_regionn_high_reg_t; -/** Group: TEE PERI REGION1 LOW REG */ -/** Type of peri_region1_low register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region1_low : R/W; bitpos: [31:2]; default: 0; - * NA - */ - uint32_t reg_peri_region1_low:30; - }; - uint32_t val; -} tee_peri_region1_low_reg_t; - - -/** Group: TEE PERI REGION1 HIGH REG */ -/** Type of peri_region1_high register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region1_high : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ - uint32_t reg_peri_region1_high:30; - }; - uint32_t val; -} tee_peri_region1_high_reg_t; - - -/** Group: TEE PERI REGION PMS REG */ +/** Group: PMS Peripheral Region Permission Control Registers */ /** Type of peri_region_pms register - * NA + * Permission register of regions 0-1 */ typedef union { struct { - /** reg_lp_core_region_pms : R/W; bitpos: [1:0]; default: 3; - * NA + /** lp_core_region_pms : R/W; bitpos: [1:0]; default: 3; + * Configures whether LP core in machine mode has permission to access address region0 + * and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_lp_core_region_pms:2; - /** reg_hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3; - * NA + uint32_t lp_core_region_pms:2; + /** hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3; + * Configures whether HP CPU0 in user mode has permission to access address region0 + * and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core0_um_region_pms:2; - /** reg_hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3; - * NA + uint32_t hp_core0_um_region_pms:2; + /** hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3; + * Configures whether HP CPU0 in machine mode has permission to access address region0 + * and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core0_mm_region_pms:2; - /** reg_hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3; - * NA + uint32_t hp_core0_mm_region_pms:2; + /** hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3; + * Configures whether HP CPU1 in user mode has permission to access address region0 + * and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core1_um_region_pms:2; - /** reg_hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3; - * NA + uint32_t hp_core1_um_region_pms:2; + /** hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3; + * Configures whether HP CPU1 in machine mode has permission to access address region0 + * and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core1_mm_region_pms:2; + uint32_t hp_core1_mm_region_pms:2; uint32_t reserved_10:22; }; uint32_t val; -} tee_peri_region_pms_reg_t; +} pms_peri_region_pms_reg_t; - -/** Group: TEE PERI REGION 2 TO 7 PMS REG */ -/** Type of peri_region_2_to_7_pms register - * NA +/** Group: PMS Peripheral Region Permission Control Registers */ +/** Type of peri_region_pms register + * Permission register of regions 2-7 */ typedef union { struct { - /** reg_lp_core_region_2_to_7_pms : R/W; bitpos: [5:0]; default: 63; - * NA + /** lp_core_region_pms : R/W; bitpos: [5:0]; default: 63; + * Configures whether LP core in machine mode has permission to access address region2 + * to region7. Bit0 corresponds to region2, bit1 to region3, ..., bit5 to region7. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_lp_core_region_2_to_7_pms:6; - /** reg_hp_core0_um_region_2_to_7_pms : R/W; bitpos: [11:6]; default: 63; - * NA + uint32_t lp_core_region_pms:6; + /** hp_core0_um_region_pms : R/W; bitpos: [11:6]; default: 63; + * Configures whether HP CPU0 in user mode has permission to access address region2 + * to region7. Bit6 corresponds to region2, bit7 to region3, ..., bit11 to region7. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core0_um_region_2_to_7_pms:6; - /** reg_hp_core0_mm_region_2_to_7_pms : R/W; bitpos: [17:12]; default: 63; - * NA + uint32_t hp_core0_um_region_pms:6; + /** hp_core0_mm_region_pms : R/W; bitpos: [17:12]; default: 63; + * Configures whether HP CPU0 in machine mode has permission to access address region2 + * to region7. Bit12 corresponds to region2, bit13 to region3, ..., bit17 to region7. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core0_mm_region_2_to_7_pms:6; - /** reg_hp_core1_um_region_2_to_7_pms : R/W; bitpos: [23:18]; default: 63; - * NA + uint32_t hp_core0_mm_region_pms:6; + /** hp_core1_um_region_pms : R/W; bitpos: [23:18]; default: 63; + * Configures whether HP CPU1 in user mode has permission to access address region2 + * to region7. Bit18 corresponds to region2, bit19 to region3, ..., bit23 to region7. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core1_um_region_2_to_7_pms:6; - /** reg_hp_core1_mm_region_2_to_7_pms : R/W; bitpos: [29:24]; default: 63; - * NA + uint32_t hp_core1_um_region_pms:6; + /** hp_core1_mm_region_pms : R/W; bitpos: [29:24]; default: 63; + * Configures whether HP CPU1 in machine mode has permission to access address region2 + * to region7. Bit24 corresponds to region2, bit25 to region3, ..., bit29 to region7. + * 0: Not allowed + * 1: Allow */ - uint32_t reg_hp_core1_mm_region_2_to_7_pms:6; + uint32_t hp_core1_mm_region_pms:6; uint32_t reserved_30:2; }; uint32_t val; -} tee_peri_region_2_to_7_pms_reg_t; - - -/** Group: TEE PERI REGION2 LOW REG */ -/** Type of peri_region2_low register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region2_low : R/W; bitpos: [31:2]; default: 0; - * NA - */ - uint32_t reg_peri_region2_low:30; - }; - uint32_t val; -} tee_peri_region2_low_reg_t; - - -/** Group: TEE PERI REGION2 HIGH REG */ -/** Type of peri_region2_high register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region2_high : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ - uint32_t reg_peri_region2_high:30; - }; - uint32_t val; -} tee_peri_region2_high_reg_t; - - -/** Group: TEE PERI REGION3 LOW REG */ -/** Type of peri_region3_low register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region3_low : R/W; bitpos: [31:2]; default: 0; - * NA - */ - uint32_t reg_peri_region3_low:30; - }; - uint32_t val; -} tee_peri_region3_low_reg_t; - - -/** Group: TEE PERI REGION3 HIGH REG */ -/** Type of peri_region3_high register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region3_high : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ - uint32_t reg_peri_region3_high:30; - }; - uint32_t val; -} tee_peri_region3_high_reg_t; - - -/** Group: TEE PERI REGION4 LOW REG */ -/** Type of peri_region4_low register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region4_low : R/W; bitpos: [31:2]; default: 0; - * NA - */ - uint32_t reg_peri_region4_low:30; - }; - uint32_t val; -} tee_peri_region4_low_reg_t; - - -/** Group: TEE PERI REGION4 HIGH REG */ -/** Type of peri_region4_high register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region4_high : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ - uint32_t reg_peri_region4_high:30; - }; - uint32_t val; -} tee_peri_region4_high_reg_t; - - -/** Group: TEE PERI REGION5 LOW REG */ -/** Type of peri_region5_low register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region5_low : R/W; bitpos: [31:2]; default: 0; - * NA - */ - uint32_t reg_peri_region5_low:30; - }; - uint32_t val; -} tee_peri_region5_low_reg_t; - - -/** Group: TEE PERI REGION5 HIGH REG */ -/** Type of peri_region5_high register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region5_high : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ - uint32_t reg_peri_region5_high:30; - }; - uint32_t val; -} tee_peri_region5_high_reg_t; - - -/** Group: TEE PERI REGION6 LOW REG */ -/** Type of peri_region6_low register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region6_low : R/W; bitpos: [31:2]; default: 0; - * NA - */ - uint32_t reg_peri_region6_low:30; - }; - uint32_t val; -} tee_peri_region6_low_reg_t; - - -/** Group: TEE PERI REGION6 HIGH REG */ -/** Type of peri_region6_high register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region6_high : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ - uint32_t reg_peri_region6_high:30; - }; - uint32_t val; -} tee_peri_region6_high_reg_t; - - -/** Group: TEE PERI REGION7 LOW REG */ -/** Type of peri_region7_low register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region7_low : R/W; bitpos: [31:2]; default: 0; - * NA - */ - uint32_t reg_peri_region7_low:30; - }; - uint32_t val; -} tee_peri_region7_low_reg_t; - - -/** Group: TEE PERI REGION7 HIGH REG */ -/** Type of peri_region7_high register - * NA - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** reg_peri_region7_high : R/W; bitpos: [31:2]; default: 1073741823; - * NA - */ - uint32_t reg_peri_region7_high:30; - }; - uint32_t val; -} tee_peri_region7_high_reg_t; - +} pms_peri_region_pms_2_to_7_reg_t; typedef struct { - volatile tee_pms_date_reg_t pms_date; - volatile tee_pms_clk_en_reg_t pms_clk_en; - volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0; - volatile tee_peri_region0_low_reg_t peri_region0_low; - volatile tee_peri_region0_high_reg_t peri_region0_high; - volatile tee_peri_region1_low_reg_t peri_region1_low; - volatile tee_peri_region1_high_reg_t peri_region1_high; - volatile tee_peri_region_pms_reg_t peri_region_pms; - volatile tee_peri_region_2_to_7_pms_reg_t peri_region_2_to_7_pms; - volatile tee_peri_region2_low_reg_t peri_region2_low; - volatile tee_peri_region2_high_reg_t peri_region2_high; - volatile tee_peri_region3_low_reg_t peri_region3_low; - volatile tee_peri_region3_high_reg_t peri_region3_high; - volatile tee_peri_region4_low_reg_t peri_region4_low; - volatile tee_peri_region4_high_reg_t peri_region4_high; - volatile tee_peri_region5_low_reg_t peri_region5_low; - volatile tee_peri_region5_high_reg_t peri_region5_high; - volatile tee_peri_region6_low_reg_t peri_region6_low; - volatile tee_peri_region6_high_reg_t peri_region6_high; - volatile tee_peri_region7_low_reg_t peri_region7_low; - volatile tee_peri_region7_high_reg_t peri_region7_high; -} tee_dev_t; + volatile pms_lp_peri_pms_date_reg_t lp_peri_pms_date; + volatile pms_lp_peri_pms_clk_en_reg_t lp_peri_pms_clk_en; + volatile pms_lp_mm_lp_peri_pms_reg0_reg_t lp_mm_lp_peri_pms_reg0; + volatile pms_peri_regionn_low_reg_t peri_region0_low; + volatile pms_peri_regionn_high_reg_t peri_region0_high; + volatile pms_peri_regionn_low_reg_t peri_region1_low; + volatile pms_peri_regionn_high_reg_t peri_region1_high; + volatile pms_peri_region_pms_reg_t peri_region_pms; + volatile pms_peri_region_pms_2_to_7_reg_t peri_region_2_to_7_pms; + volatile pms_peri_regionn_low_reg_t peri_region2_low; + volatile pms_peri_regionn_high_reg_t peri_region2_high; + volatile pms_peri_regionn_low_reg_t peri_region3_low; + volatile pms_peri_regionn_high_reg_t peri_region3_high; + volatile pms_peri_regionn_low_reg_t peri_region4_low; + volatile pms_peri_regionn_high_reg_t peri_region4_high; + volatile pms_peri_regionn_low_reg_t peri_region5_low; + volatile pms_peri_regionn_high_reg_t peri_region5_high; + volatile pms_peri_regionn_low_reg_t peri_region6_low; + volatile pms_peri_regionn_high_reg_t peri_region6_high; + volatile pms_peri_regionn_low_reg_t peri_region7_low; + volatile pms_peri_regionn_high_reg_t peri_region7_high; +} lp_peri_pms_dev_t; -extern tee_dev_t LP_PERI_PMS; +extern lp_peri_pms_dev_t LP_PERI_PMS; #ifndef __cplusplus -_Static_assert(sizeof(tee_dev_t) == 0x54, "Invalid size of tee_dev_t structure"); +_Static_assert(sizeof(lp_peri_pms_dev_t) == 0x54, "Invalid size of lp_peri_pms_dev_t structure"); #endif #ifdef __cplusplus From 3acb4a3e0cab031b810e3cf12b3bd6cb82865e60 Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Fri, 6 Feb 2026 15:52:49 +0530 Subject: [PATCH 2/3] refactor(hal): Refactor and update the ESP32-P4 APM LL/HAL APIs --- components/esp_hal_security/apm_hal.c | 346 +++++++-- .../esp32p4/include/hal/apm_ll.h | 676 +++++++++--------- .../esp_hal_security/include/hal/apm_hal.h | 306 +++++--- .../esp_hal_security/include/hal/apm_types.h | 239 ++++++- .../hal/esp32p4/include/hal/axi_icm_ll.h | 128 +++- .../hal/esp32p4/include/hal/lp_sys_ll.h | 77 ++ components/soc/esp32p4/include/soc/apm_defs.h | 53 ++ 7 files changed, 1333 insertions(+), 492 deletions(-) create mode 100644 components/soc/esp32p4/include/soc/apm_defs.h diff --git a/components/esp_hal_security/apm_hal.c b/components/esp_hal_security/apm_hal.c index 6cc45772a99..2b85269da1e 100644 --- a/components/esp_hal_security/apm_hal.c +++ b/components/esp_hal_security/apm_hal.c @@ -1,59 +1,22 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include #include "soc/soc_caps.h" +#include "soc/interrupts.h" #include "hal/assert.h" #include "hal/apm_hal.h" #include "hal/apm_ll.h" #include "hal/log.h" +#if !SOC_APM_CTRL_FILTER_SUPPORTED +#include "hal/axi_icm_ll.h" +#include "hal/lp_sys_ll.h" +#endif -#if SOC_IS(ESP32P4) -void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri, - apm_ll_secure_mode_t sec_mode, bool enable) -{ - apm_ll_hp_peri_access_enable(master_id, hp_peri, sec_mode, enable); -} - -void apm_hal_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable) -{ - apm_ll_lp_peri_access_enable(lp_peri, enable); -} - -void apm_hal_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr) -{ - apm_ll_peri_region_config(regn_num, regn_low_addr, regn_high_addr); -} - -int apm_hal_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode, - uint32_t regn_num, uint32_t regn_pms) -{ - return apm_ll_peri_region_pms(master_id, sec_mode, regn_num, regn_pms); -} - -int apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) -{ - return apm_ll_apm_ctrl_clk_gating_enable(apm_ctrl, enable); -} - -void apm_hal_dma_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr) -{ - apm_ll_dma_region_set_low_address(regn_num, regn_low_addr); - apm_ll_dma_region_set_high_address(regn_num, regn_high_addr); -} - -void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data) -{ - HAL_ASSERT(pms_data); - - apm_ll_dma_region_r_pms(pms_data->dma_master, pms_data->pms_r_mask); - apm_ll_dma_region_w_pms(pms_data->dma_master, pms_data->pms_w_mask); -} -#else - +#if SOC_APM_CTRL_FILTER_SUPPORTED void apm_hal_set_master_sec_mode(uint32_t master_mask, apm_security_mode_t mode) { master_mask &= APM_MASTER_MASK_ALL; @@ -522,5 +485,298 @@ void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable) break; } } +#else +void apm_hal_dma_pms_set_region_bounds(uint32_t regn_num, uint32_t start_addr, uint32_t end_addr) +{ + apm_ll_dma_pms_set_region_start_addr(regn_num, start_addr); + apm_ll_dma_pms_set_region_end_addr(regn_num, end_addr); +} -#endif //SOC_IS(ESP32P4) +void apm_hal_dma_pms_set_master_region_attr(apm_master_dma_id_t mid, uint32_t regn_rd_mask, uint32_t regn_wr_mask) +{ + apm_ll_dma_pms_set_region_attr_r(mid, regn_rd_mask); + apm_ll_dma_pms_set_region_attr_w(mid, regn_wr_mask); +} + +void apm_hal_dma_pms_set_region_cfg(uint32_t regn_count, const apm_hal_pms_regn_cfg_t *regn_cfg) +{ + HAL_ASSERT(regn_cfg); + + for (uint32_t idx = 0; idx < regn_count; idx++) { + const apm_hal_pms_regn_cfg_t *region = ®n_cfg[idx]; + apm_hal_dma_pms_set_region_bounds(region->regn_num, region->regn_start_addr, region->regn_end_addr); + } +} + +void apm_hal_dma_pms_set_master_cfg(uint32_t master_count, const apm_hal_pms_master_cfg_t *master_cfg) +{ + HAL_ASSERT(master_cfg); + + for (uint32_t idx = 0; idx < master_count; idx++) { + const apm_hal_pms_master_cfg_t *master = &master_cfg[idx]; + apm_ll_dma_pms_set_region_attr_r(master->dma.id, master->dma.regn_pms_rd); + apm_ll_dma_pms_set_region_attr_w(master->dma.id, master->dma.regn_pms_wr); + } +} + +void apm_hal_hp2lp_peri_pms_set_hpcpu_access(int core_id, apm_security_mode_t mode, uint32_t enable_mask) +{ + HAL_ASSERT(core_id < SOC_CPU_CORES_NUM); + + enable_mask &= APM_SLAVE_LP_PERI_ALL_MASK; + for (int sid = 0; sid < APM_SLAVE_LP_PERIPH_MAX; sid++) { + apm_ll_hp2lp_peri_pms_enable_hpcpu_access(core_id, mode, (apm_slave_lp_periph_t)sid, + (enable_mask >> sid) & 1U); + } +} + +void apm_hal_lp_peri_pms_set_lpcpu_access(uint32_t enable_mask) +{ + enable_mask &= APM_SLAVE_LP_PERI_ALL_MASK; + for (int sid = 0; sid < APM_SLAVE_LP_PERIPH_MAX; sid++) { + apm_ll_lp_peri_pms_enable_lpcpu_access((apm_slave_lp_periph_t)sid, + (enable_mask >> sid) & 1U); + } +} + +void apm_hal_hp_peri_pms_set_hpcpu_access(int core_id, apm_security_mode_t mode, const apm_hal_pms_hp_peri_cfg_t *cfg) +{ + HAL_ASSERT(core_id < SOC_CPU_CORES_NUM); + HAL_ASSERT(cfg); + + const uint32_t cpu_peri = cfg->cpu_peri & APM_SLAVE_CPU_PERI_ALL_MASK; + const uint32_t hp_peri0 = cfg->hp_peri0 & APM_SLAVE_HP_PERI0_ALL_MASK; + const uint64_t hp_peri1 = cfg->hp_peri1 & APM_SLAVE_HP_PERI1_ALL_MASK; + + /* CPU_PERI */ + for (int sid = 0; sid < APM_SLAVE_CPU_PERIPH_MAX; sid++) { + apm_ll_hp_peri_pms_enable_hpcpu_cpu_peri_access(core_id, mode, (apm_slave_cpu_periph_id_t)sid, + (cpu_peri >> sid) & 1U); + } + /* HP_PERI0 */ + for (int sid = 0; sid < APM_SLAVE_HP_PERIPH0_MAX; sid++) { + apm_ll_hp_peri_pms_enable_hpcpu_hp_peri0_access(core_id, mode, (apm_slave_hp_periph0_id_t)sid, + (hp_peri0 >> sid) & 1U); + } + /* HP_PERI1 */ + for (int sid = 0; sid < APM_SLAVE_HP_PERIPH1_MAX; sid++) { + apm_ll_hp_peri_pms_enable_hpcpu_hp_peri1_access(core_id, mode, (apm_slave_hp_periph1_id_t)sid, + (hp_peri1 >> sid) & 1ULL); + } +} + +void apm_hal_lp2hp_peri_pms_set_lpcpu_access(const apm_hal_pms_hp_peri_cfg_t *cfg) +{ + HAL_ASSERT(cfg); + + const uint32_t cpu_peri = cfg->cpu_peri & APM_SLAVE_CPU_PERI_ALL_MASK; + const uint32_t hp_peri0 = cfg->hp_peri0 & APM_SLAVE_HP_PERI0_ALL_MASK; + const uint64_t hp_peri1 = cfg->hp_peri1 & APM_SLAVE_HP_PERI1_ALL_MASK; + + /* CPU_PERI */ + for (int sid = 0; sid < APM_SLAVE_CPU_PERIPH_MAX; sid++) { + apm_ll_lp2hp_peri_pms_enable_lpcpu_cpu_peri_access((apm_slave_cpu_periph_id_t)sid, + (cpu_peri >> sid) & 1U); + } + /* HP_PERI0 */ + for (int sid = 0; sid < APM_SLAVE_HP_PERIPH0_MAX; sid++) { + apm_ll_lp2hp_peri_pms_enable_lpcpu_hp_peri0_access((apm_slave_hp_periph0_id_t)sid, + (hp_peri0 >> sid) & 1U); + } + /* HP_PERI1 */ + for (int sid = 0; sid < APM_SLAVE_HP_PERIPH1_MAX; sid++) { + apm_ll_lp2hp_peri_pms_enable_lpcpu_hp_peri1_access((apm_slave_hp_periph1_id_t)sid, + (hp_peri1 >> sid) & 1ULL); + } +} + +void apm_hal_lp_peri_pms_set_region_bounds(uint32_t regn_num, uint32_t start_addr, uint32_t end_addr) +{ + apm_ll_lp_peri_pms_set_region_start_addr(regn_num, start_addr); + apm_ll_lp_peri_pms_set_region_end_addr(regn_num, end_addr); +} + +void apm_hal_lp_peri_pms_set_master_region_attr(apm_master_id_t mid, apm_security_mode_t mode, uint32_t regn_pms_mask) +{ + switch (mid) { + case APM_MASTER_HPCPU0: + apm_ll_lp_peri_pms_hpcpu0_set_region_access(mode, regn_pms_mask); + break; + case APM_MASTER_HPCPU1: + apm_ll_lp_peri_pms_hpcpu1_set_region_access(mode, regn_pms_mask); + break; + case APM_MASTER_LPCPU: + apm_ll_lp_peri_pms_lpcpu_set_region_access(regn_pms_mask); + break; + default: + break; + } +} + +void apm_hal_lp_peri_pms_set_region_cfg(uint32_t regn_count, const apm_hal_pms_regn_cfg_t *regn_cfg) +{ + HAL_ASSERT(regn_cfg); + + for (uint32_t idx = 0; idx < regn_count; idx++) { + const apm_hal_pms_regn_cfg_t *region = ®n_cfg[idx]; + apm_hal_lp_peri_pms_set_region_bounds(region->regn_num, region->regn_start_addr, region->regn_end_addr); + } +} + +void apm_hal_lp_peri_pms_set_master_cfg(uint32_t master_count, const apm_hal_pms_master_cfg_t *master_cfg) +{ + HAL_ASSERT(master_cfg); + + for (int idx = 0; idx < master_count; idx++) { + const apm_hal_pms_master_cfg_t *master = &master_cfg[idx]; + apm_hal_lp_peri_pms_set_master_region_attr(master->lp_peri.id, master->lp_peri.mode, master->lp_peri.regn_pms); + } +} + +void apm_hal_enable_intr(apm_ctrl_module_t ctrl_mod, bool enable) +{ + uint32_t mask = 0; + + switch (ctrl_mod) { + case APM_CTRL_DMA_PMS: + case APM_CTRL_HP_PERI_PMS: + case APM_CTRL_LP2HP_PERI_PMS: + mask = BIT(AXI_ICM_INTR_SYS_ADDRHOLE) | BIT(AXI_ICM_INTR_CPU_ADDRHOLE); + axi_icm_ll_enable_intr(mask, enable); + break; + case APM_CTRL_LP_PERI_PMS: + case APM_CTRL_HP2LP_PERI_PMS: + mask = BIT(LP_SYS_INTR_LP_ADDRHOLE) | BIT(LP_SYS_INTR_IDBUS_ADDRHOLE); + lp_sys_ll_enable_intr(mask, enable); + break; + default: + (void)mask; + break; + } +} + +void apm_hal_clear_intr(apm_ctrl_module_t ctrl_mod) +{ + uint32_t mask = 0; + + switch (ctrl_mod) { + case APM_CTRL_DMA_PMS: + case APM_CTRL_HP_PERI_PMS: + case APM_CTRL_LP2HP_PERI_PMS: + mask = BIT(AXI_ICM_INTR_SYS_ADDRHOLE) | BIT(AXI_ICM_INTR_CPU_ADDRHOLE); + axi_icm_ll_clear_intr(mask); + break; + case APM_CTRL_LP_PERI_PMS: + case APM_CTRL_HP2LP_PERI_PMS: + mask = BIT(LP_SYS_INTR_LP_ADDRHOLE) | BIT(LP_SYS_INTR_IDBUS_ADDRHOLE); + lp_sys_ll_clear_intr(mask); + break; + default: + (void)mask; + break; + } +} + +uint32_t apm_hal_get_intr_status(void) +{ + uint32_t status = 0, mask = 0; + + mask = BIT(AXI_ICM_INTR_SYS_ADDRHOLE) | BIT(AXI_ICM_INTR_CPU_ADDRHOLE); + uint32_t hp_intr_st = axi_icm_ll_get_intr_status(mask); + if (hp_intr_st & BIT(AXI_ICM_INTR_SYS_ADDRHOLE)) { + status |= APM_EXCP_HP_AXI; + } + if (hp_intr_st & BIT(AXI_ICM_INTR_CPU_ADDRHOLE)) { + status |= APM_EXCP_HP_AHB; + } + + mask = BIT(LP_SYS_INTR_LP_ADDRHOLE) | BIT(LP_SYS_INTR_IDBUS_ADDRHOLE); + uint32_t lp_intr_st = lp_sys_ll_get_intr_status(mask); + if (lp_intr_st & BIT(LP_SYS_INTR_LP_ADDRHOLE)) { + status |= APM_EXCP_LP_AHB; + } + if (lp_intr_st & BIT(LP_SYS_INTR_IDBUS_ADDRHOLE)) { + status |= APM_EXCP_LP_IDBUS; + } + + return status; +} + +void apm_hal_get_exception_info(apm_ctrl_exception_type type, apm_ctrl_exception_info_t *excp_info) +{ + HAL_ASSERT(excp_info); + + switch (type) { + case APM_EXCP_HP_AXI: + case APM_EXCP_HP_AHB: { + axi_icm_ll_excp_info_t info = {0}; + if (type == APM_EXCP_HP_AXI) { + axi_icm_ll_get_sys_excp_info(&info); + /* NOTE: Master ID = 4-bit CID + 4-bit UID, extracting only CID here */ + info.id = (info.id >> 0x04U) & 0x0FU; + } else { + axi_icm_ll_get_cpu_excp_info(&info); + } + excp_info->addr = info.addr; + excp_info->id = info.id; + excp_info->is_wr = info.is_wr; + excp_info->is_secure = info.is_secure; + break; + } + case APM_EXCP_LP_AHB: + case APM_EXCP_LP_IDBUS: { + lp_sys_ll_excp_info_t info = {0}; + if (type == APM_EXCP_LP_AHB) { + lp_sys_ll_get_ahb_excp_info(&info); + } else { + lp_sys_ll_get_idbus_excp_info(&info); + } + excp_info->addr = info.addr; + excp_info->id = info.id; + excp_info->is_wr = info.is_wr; + excp_info->is_secure = info.is_secure; + break; + } + default: + break; + } +} + +int apm_hal_get_intr_src_num(apm_ctrl_module_t ctrl_mod) +{ + switch (ctrl_mod) { + case APM_CTRL_DMA_PMS: + case APM_CTRL_HP_PERI_PMS: + case APM_CTRL_LP2HP_PERI_PMS: + return ETS_SYS_ICM_INTR_SOURCE; + case APM_CTRL_LP_PERI_PMS: + case APM_CTRL_HP2LP_PERI_PMS: + return ETS_LP_SYSREG_INTR_SOURCE; + default: + return -1; + } +} + +void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable) +{ + switch (ctrl_mod) { + case APM_CTRL_DMA_PMS: + apm_ll_dma_pms_enable_clk_gating(enable); + break; + case APM_CTRL_HP_PERI_PMS: + apm_ll_hp_peri_pms_enable_clk_gating(enable); + break; + case APM_CTRL_HP2LP_PERI_PMS: + apm_ll_hp2lp_peri_pms_enable_clk_gating(enable); + break; + case APM_CTRL_LP_PERI_PMS: + apm_ll_lp_peri_pms_enable_clk_gating(enable); + break; + case APM_CTRL_LP2HP_PERI_PMS: + apm_ll_lp2hp_peri_pms_enable_clk_gating(enable); + break; + default: + break; + } +} +#endif // SOC_APM_CTRL_FILTER_SUPPORTED diff --git a/components/esp_hal_security/esp32p4/include/hal/apm_ll.h b/components/esp_hal_security/esp32p4/include/hal/apm_ll.h index 8cdf5412f84..374c496bfce 100644 --- a/components/esp_hal_security/esp32p4/include/hal/apm_ll.h +++ b/components/esp_hal_security/esp32p4/include/hal/apm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,419 +8,425 @@ #include #include #include "hal/assert.h" +#include "hal/config.h" #include "soc/dma_pms_reg.h" #include "soc/hp2lp_peri_pms_reg.h" #include "soc/hp_peri_pms_reg.h" #include "soc/lp2hp_peri_pms_reg.h" #include "soc/lp_peri_pms_reg.h" +#include "hal/apm_types.h" +#include "soc/apm_defs.h" + #ifdef __cplusplus extern "C" { #endif -/** - * @brief Master Secure Mode - */ -typedef enum { - APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode (Machine mode). */ - APM_LL_SECURE_MODE_REE = 1, /* Rich execution environment mode (User mode). */ - APM_LL_SECURE_MODE_INV = 2, /* Invalid mode. */ -} apm_ll_secure_mode_t; +/* Offsets for indexing R/W attribute registers for DMA masters */ +#define APM_LL_DMA_PMS_ATTR_RD_OFFSET 0x04U +#define APM_LL_DMA_PMS_ATTR_WR_OFFSET_1 0x04U +#define APM_LL_DMA_PMS_ATTR_WR_OFFSET_2 0x14U + +/* Offsets for indexing HP2LP_PERI_PMS registers by CPU core and security mode */ +#define APM_LL_HP2LP_PERI_PMS_CORE_OFFSET 0x08U +#define APM_LL_HP2LP_PERI_PMS_MODE_OFFSET 0x04U + +/* Bit-field masks/shifts for extracting LP_PERI_PMS region permission fields */ +#define APM_LL_LP_PERI_PMS_REGN0_1_MASK 0x03U +#define APM_LL_LP_PERI_PMS_REGN2_7_SHIFT 2U +#define APM_LL_LP_PERI_PMS_REGN2_7_MASK 0x3FU + +/* Helper macro for indexing HP_PERI_PMS registers by core, mode, and register index */ +#define APM_LL_HP_PERI_PMS_CORE_OFFSET 0x20U +#define APM_LL_HP_PERI_PMS_MODE_OFFSET 0x10U +#define APM_LL_HP_PERI_PMS_REG_OFFSET 0x04U + +#define HP_PERI_PMS_COREn_xM_REGk_REG(cid, mode, regk) \ + (PMS_CORE0_MM_HP_PERI_PMS_REG0_REG \ + + ((cid) * APM_LL_HP_PERI_PMS_CORE_OFFSET) \ + + ((mode) * APM_LL_HP_PERI_PMS_MODE_OFFSET) \ + + ((regk) * APM_LL_HP_PERI_PMS_REG_OFFSET)) + +/* Helper macros for indexing LP_PERI_PMS configurable region address registers */ +#define APM_LL_LP_PERI_PMS_REGION_OFFSET 0x08U +#define APM_LL_LP_PERI_PMS_REGION_GAP 0x08U + +#define PMS_PERI_REGION_LOW_REG(regn) \ + (PMS_PERI_REGION0_LOW_REG \ + + ((regn) * APM_LL_LP_PERI_PMS_REGION_OFFSET) \ + + (((regn) >= 2U) ? APM_LL_LP_PERI_PMS_REGION_GAP : 0U)) + +#define PMS_PERI_REGION_HIGH_REG(regn) \ + (PMS_PERI_REGION0_HIGH_REG \ + + ((regn) * APM_LL_LP_PERI_PMS_REGION_OFFSET) \ + + (((regn) >= 2U) ? APM_LL_LP_PERI_PMS_REGION_GAP : 0U)) /** - * @brief Bus Masters. - */ -typedef enum { - APM_LL_MASTER_LPCPU = 0, - APM_LL_MASTER_HPCPU0, - APM_LL_MASTER_HPCPU1, - APM_LL_MASTER_DMA, -} apm_ll_master_id_t; - -/** - * @brief APM Controller - */ -typedef enum { - LP_APM_CTRL = 0, - HP2LP_APM_CTRL, - HP_APM_CTRL, - LP2HP_APM_CTRL, - DMA_APM_CTRL, - MAX_APM_CTRL, -} apm_ll_apm_ctrl_t; - -/** - * @brief HP CPU Peripherals. - */ -typedef enum { - PMS_COREn_XM_PSRAM_ALLOW = 0, - PMS_COREn_XM_FLASH_ALLOW, - PMS_COREn_XM_L2MEM_ALLOW, - PMS_COREn_XM_L2ROM_ALLOW, - PMS_COREn_XM_TRACE0_ALLOW = 6, - PMS_COREn_XM_TRACE1_ALLOW, - PMS_COREn_XM_CPU_BUS_MON_ALLOW, - PMS_COREn_XM_L2MEM_MON_ALLOW, - PMS_COREn_XM_TCM_MON_ALLOW, - PMS_COREn_XM_CACHE_ALLOW, - - PMS_COREn_XM_HP_USBOTG_ALLOW = 32, - PMS_COREn_XM_HP_USBOTG11_ALLOW, - PMS_COREn_XM_HP_USBOTG11_WRAP_ALLOW, - PMS_COREn_XM_HP_GDMA_ALLOW, - PMS_COREn_XM_HP_SDMMC_ALLOW = 37, - PMS_COREn_XM_HP_AHB_PDMA_ALLOW, - PMS_COREn_XM_HP_JPEG_ALLOW, - PMS_COREn_XM_HP_PPA_ALLOW, - PMS_COREn_XM_HP_DMA2D_ALLOW, - PMS_COREn_XM_HP_KEY_MANAGER_ALLOW, - PMS_COREn_XM_HP_AXI_PDMA_ALLOW, - PMS_COREn_XM_HP_FLASH_ALLOW, - PMS_COREn_XM_HP_PSRAM_ALLOW, - PMS_COREn_XM_HP_CRYPTO_ALLOW, - PMS_COREn_XM_HP_GMAC_ALLOW, - PMS_COREn_XM_HP_USB_PHY_ALLOW, - PMS_COREn_XM_HP_CSI_HOST_ALLOW = 50, - PMS_COREn_XM_HP_DSI_HOST_ALLOW, - PMS_COREn_XM_HP_ISP_ALLOW, - PMS_COREn_XM_HP_H264_CORE_ALLOW, - PMS_COREn_XM_HP_RMT_ALLOW, - PMS_COREn_XM_HP_BITSCRAMBLER_ALLOW, - PMS_COREn_XM_HP_AXI_ICM_ALLOW, - PMS_COREn_XM_HP_PERI_PMS_ALLOW, - PMS_COREn_XM_LP2HP_PERI_PMS_ALLOW, - PMS_COREn_XM_DMA_PMS_ALLOW, - PMS_COREn_XM_HP_H264_DMA2D_ALLOW = 60, - - PMS_COREn_XM_HP_MCPWM0_ALLOW = 64, - PMS_COREn_XM_HP_MCPWM1_ALLOW, - PMS_COREn_XM_HP_TIMER_GROUP0_ALLOW, - PMS_COREn_XM_HP_TIMER_GROUP1_ALLOW, - PMS_COREn_XM_HP_I2C0_ALLOW, - PMS_COREn_XM_HP_I2C1_ALLOW, - PMS_COREn_XM_HP_I2S0_ALLOW, - PMS_COREn_XM_HP_I2S1_ALLOW, - PMS_COREn_XM_HP_I2S2_ALLOW, - PMS_COREn_XM_HP_PCNT_ALLOW, - PMS_COREn_XM_HP_UART0_ALLOW, - PMS_COREn_XM_HP_UART1_ALLOW, - PMS_COREn_XM_HP_UART2_ALLOW, - PMS_COREn_XM_HP_UART3_ALLOW, - PMS_COREn_XM_HP_UART4_ALLOW, - PMS_COREn_XM_HP_PARLIO_ALLOW269, - PMS_COREn_XM_HP_GPSPI2_ALLOW270, - PMS_COREn_XM_HP_GPSPI3_ALLOW271, - PMS_COREn_XM_HP_USBDEVICE_ALLOW, - PMS_COREn_XM_HP_LEDC_ALLOW, - PMS_COREn_XM_HP_ETM_ALLOW = 85, - PMS_COREn_XM_HP_INTRMTX_ALLOW, - PMS_COREn_XM_HP_TWAI0_ALLOW, - PMS_COREn_XM_HP_TWAI1_ALLOW, - PMS_COREn_XM_HP_TWAI2_ALLOW, - PMS_COREn_XM_HP_I3C_MST_ALLOW, - PMS_COREn_XM_HP_I3C_SLV_ALLOW, - PMS_COREn_XM_HP_LCDCAM_ALLOW, - PMS_COREn_XM_HP_ADC_ALLOW = 94, - PMS_COREn_XM_HP_UHCI_ALLOW, - - PMS_COREn_XM_HP_GPIO_ALLOW = 96, - PMS_COREn_XM_HP_IOMUX_ALLOW, - PMS_COREn_XM_HP_SYSTIMER_ALLOW, - PMS_COREn_XM_HP_SYS_REG_ALLOW, - PMS_COREn_XM_HP_CLKRST_ALLOW, - PMS_COREn_XM_HP_PERI_MAX, -} apm_ll_hp_peri_t; - -/** - * @brief LP CPU Peripherals. - */ -typedef enum { - PMS_MM_LP_SYSREG_ALLOW = 0, - PMS_MM_LP_AONCLKRST_ALLOW, - PMS_MM_LP_TIMER_ALLOW, - PMS_MM_LP_ANAPERI_ALLOW, - PMS_MM_LP_PMU_ALLOW, - PMS_MM_LP_WDT_ALLOW, - PMS_MM_LP_MAILBOX_ALLOW, - PMS_MM_LP_PERICLKRST_ALLOW = 8, - PMS_MM_LP_UART_ALLOW, - PMS_MM_LP_I2C_ALLOW, - PMS_MM_LP_SPI_ALLOW, - PMS_MM_LP_I2CMST_ALLOW, - PMS_MM_LP_I2S_ALLOW, - PMS_MM_LP_ADC_ALLOW, - PMS_MM_LP_TOUCH_ALLOW, - PMS_MM_LP_IOMUX_ALLOW, - PMS_MM_LP_INTR_ALLOW, - PMS_MM_LP_EFUSE_ALLOW, - PMS_MM_LP_PMS_ALLOW, - PMS_MM_HP2LP_PMS_ALLOW, - PMS_MM_LP_TSENS_ALLOW, - PMS_MM_LP_HUK_ALLOW, - PMS_HP_COREn_MM_LP_SRAM_ALLOW, - PMS_LP_MM_PERI_MAX, -} apm_ll_lp_peri_t; - -/** - * @brief LP CPU Peripherals. - */ -typedef enum { - PMS_DMA_GDMA_CH0 = 0, - PMS_DMA_GDMA_CH1, - PMS_DMA_GDMA_CH2, - PMS_DMA_GDMA_CH3, - PMS_DMA_AHB_PDMA_ADC, - PMS_DMA_AHB_PDMA_I2S0, - PMS_DMA_AHB_PDMA_I2S1, - PMS_DMA_AHB_PDMA_I2S2, - PMS_DMA_AHB_PDMA_I3C_MST, - PMS_DMA_AHB_PDMA_UHCI0, - PMS_DMA_AHB_PDMA_RMT, - PMS_DMA_AXI_PDMA_LCDCAM, - PMS_DMA_AXI_PDMA_GPSPI2, - PMS_DMA_AXI_PDMA_GPSPI3, - PMS_DMA_AXI_PDMA_PARLIO, - PMS_DMA_AXI_PDMA_AES, - PMS_DMA_AXI_PDMA_SHA, - PMS_DMA_DMA2D_JPEG, - PMS_DMA_USB, - PMS_DMA_GMAC, - PMS_DMA_SDMMC, - PMS_DMA_USBOTG11, - PMS_DMA_TRACE0, - PMS_DMA_TRACE1, - PMS_DMA_L2MEM_MON, - PMS_DMA_TCM_MON, - PMS_DMA_H264, - PMS_DMA_DMA2D_PPA, - PMS_DMA_DMA2D_DUMMY, - PMS_DMA_AHB_PDMA_DUMMY, - PMS_DMA_AXI_PDMA_DUMMY, - PMS_DMA_MAX, -} apm_ll_dma_master_t; - -#define PMS_PERI_MAX_REGION_NUM 2 -#define PMS_DMA_MAX_REGION_NUM 32 - -#define PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri) \ - ({\ - (PMS_CORE0_MM_HP_PERI_PMS_REG0_REG + (master_id * 0x20) \ - + (sec_mode * 0x10) + ((hp_peri/32) * 0x4) ); \ - }) - -#define PMS_PERI_REGION_LOW_REG(regn_num) \ - ({\ - (PMS_PERI_REGION0_LOW_REG + (regn_num * 8)); \ - }) - -#define PMS_PERI_REGION_HIGH_REG(regn_num) \ - ({\ - (PMS_PERI_REGION0_HIGH_REG + (regn_num * 8)); \ - }) - -#define PMS_DMA_PMS_R_REG(dma_master) \ - ({\ - (PMS_DMA_GDMA_CH0_R_PMS_REG + (dma_master * 8)); \ - }) - -#define PMS_DMA_PMS_W_REG(dma_master) \ - ({\ - (PMS_DMA_GDMA_CH0_W_PMS_REG + (dma_master * 8)); \ - }) - -/** - * @brief Configure HP peripherals access permission for the HP CPU0/1. + * @brief Enable/disable clock gating for DMA_PMS * - * @param master_id HP CPU0/1 - * @param hp_peri HP peripheral whose access permission to be configured. - * @param enable Permission enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_ll_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri, - apm_ll_secure_mode_t sec_mode, bool enable) +static inline void apm_ll_dma_pms_enable_clk_gating(bool enable) { - HAL_ASSERT((master_id > APM_LL_MASTER_LPCPU) && (master_id < APM_LL_MASTER_DMA) - && (hp_peri < PMS_COREn_XM_HP_PERI_MAX) && (sec_mode < APM_LL_SECURE_MODE_INV)); - if (enable) { - REG_SET_BIT(PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri), BIT(hp_peri % 32)); + REG_CLR_BIT(PMS_DMA_CLK_EN_REG, PMS_DMA_CLK_EN); } else { - REG_CLR_BIT(PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri), BIT(hp_peri % 32)); + REG_SET_BIT(PMS_DMA_CLK_EN_REG, PMS_DMA_CLK_EN); } } /** - * @brief Configure LP peripherals access permission for the LP CPU. + * @brief Set region start address in DMA_PMS * - * @param lp_peri LP peripheral whose access permission to be configured. - * @param enable Permission enable/disable + * @param regn_num Region number + * @param addr Start address */ -static inline void apm_ll_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable) +static inline void apm_ll_dma_pms_set_region_start_addr(uint32_t regn_num, uint32_t addr) { - HAL_ASSERT(lp_peri < PMS_LP_MM_PERI_MAX); + REG_WRITE(PMS_DMA_REGION0_LOW_REG + APM_DMA_PMS_REGION_ADDR_OFFSET * regn_num, addr); +} +/** + * @brief Set region end address in DMA_PMS + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_dma_pms_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(PMS_DMA_REGION0_HIGH_REG + APM_DMA_PMS_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set read-access region mask for a DMA master in DMA_PMS + * + * @param mid DMA master ID + * @param regn_mask Bitmask of regions the master is permitted to read + */ +static inline void apm_ll_dma_pms_set_region_attr_r(apm_master_dma_id_t mid, uint32_t regn_mask) +{ + uint32_t offs = APM_DMA_PMS_REGION_ATTR_OFFSET * (uint32_t)mid; + if (mid >= APM_MASTER_DMA_AXI_PDMA_LCDCAM) { + offs += APM_LL_DMA_PMS_ATTR_RD_OFFSET; + } + + REG_WRITE(PMS_DMA_GDMA_CH0_R_PMS_REG + offs, regn_mask); +} + +/** + * @brief Set write-access region mask for a DMA master in DMA_PMS + * + * @param mid DMA master ID + * @param regn_mask Bitmask of regions the master is permitted to write + */ +static inline void apm_ll_dma_pms_set_region_attr_w(apm_master_dma_id_t mid, uint32_t regn_mask) +{ + uint32_t offs = APM_DMA_PMS_REGION_ATTR_OFFSET * (uint32_t)mid; + if (mid == APM_MASTER_DMA_AHB_PDMA_RMT) { + offs += APM_LL_DMA_PMS_ATTR_WR_OFFSET_2; + } else if (mid >= APM_MASTER_DMA_AXI_PDMA_LCDCAM) { + offs += APM_LL_DMA_PMS_ATTR_WR_OFFSET_1; + } + + REG_WRITE(PMS_DMA_GDMA_CH0_W_PMS_REG + offs, regn_mask); +} + +/** + * @brief Enable/disable clock gating for HP_PERI_PMS + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_peri_pms_enable_clk_gating(bool enable) +{ if (enable) { - REG_SET_BIT(PMS_LP_MM_LP_PERI_PMS_REG0_REG, BIT(lp_peri)); + REG_CLR_BIT(PMS_HP_PERI_PMS_CLK_EN_REG, PMS_HP_PERI_PMS_CLK_EN); } else { - REG_CLR_BIT(PMS_LP_MM_LP_PERI_PMS_REG0_REG, BIT(lp_peri)); + REG_SET_BIT(PMS_HP_PERI_PMS_CLK_EN_REG, PMS_HP_PERI_PMS_CLK_EN); } } /** - * @brief Configure peripherals configurable address ranges. + * @brief Enable/disable HP CPU access to a CPU peripheral in HP_PERI_PMS * - * @param regn_num Configurable address range number. - * @param regn_low_addr Configurable address range start address. - * @param regn_high_addr Configurable address range end address. + * @param core_id CPU core ID + * @param mode Security mode + * @param sid CPU peripheral slave ID + * @param enable True to enable access, false to disable */ -static inline void apm_ll_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr, - uint32_t regn_high_addr) +static inline void apm_ll_hp_peri_pms_enable_hpcpu_cpu_peri_access(const int core_id, apm_security_mode_t mode, apm_slave_cpu_periph_id_t sid, bool enable) { - HAL_ASSERT(regn_num < PMS_PERI_MAX_REGION_NUM); - - REG_WRITE(PMS_PERI_REGION_LOW_REG(regn_num), regn_low_addr); - REG_WRITE(PMS_PERI_REGION_HIGH_REG(regn_num), regn_high_addr); + if (enable) { + REG_SET_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, 0), BIT(sid)); + } else { + REG_CLR_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, 0), BIT(sid)); + } } /** - * @brief Configure peripherals configurable address ranges. + * @brief Enable/disable HP CPU access to an HP peripheral (group 0) in HP_PERI_PMS * - * @param master_id LP CPU and HP CPU0/1 - * @param sec_mode CPU privilege mode (Machine/User) which corresponds to (TEE/REE). - * @param regn_num Configurable address range number. - * @param regn_pms Configurable address range permission setting(2-bits field). - * Bit 0: Region 0 permission enable/disable. - * Bit 1: Region 1 permission enable/disable. - * @return Configuration performed successfully? + * @param core_id CPU core ID + * @param mode Security mode + * @param sid HP peripheral group 0 slave ID + * @param enable True to enable access, false to disable */ -static inline int apm_ll_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode, - uint32_t regn_num, uint32_t regn_pms) +static inline void apm_ll_hp_peri_pms_enable_hpcpu_hp_peri0_access(const int core_id, apm_security_mode_t mode, apm_slave_hp_periph0_id_t sid, bool enable) { - HAL_ASSERT((master_id < APM_LL_MASTER_DMA) && (sec_mode < APM_LL_SECURE_MODE_INV)); + if (enable) { + REG_SET_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, 1), BIT(sid)); + } else { + REG_CLR_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, 1), BIT(sid)); + } +} - regn_pms &= 0x3; +/** + * @brief Enable/disable HP CPU access to an HP peripheral (group 1) in HP_PERI_PMS + * + * @param core_id CPU core ID + * @param mode Security mode + * @param sid HP peripheral group 1 slave ID + * @param enable True to enable access, false to disable + */ +static inline void apm_ll_hp_peri_pms_enable_hpcpu_hp_peri1_access(const int core_id, apm_security_mode_t mode, apm_slave_hp_periph1_id_t sid, bool enable) +{ + uint32_t regk = (sid < 32) ? 2U : 3U; + if (enable) { + REG_SET_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, regk), BIT(sid & 0x1FU)); + } else { + REG_CLR_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, regk), BIT(sid & 0x1FU)); + } +} - switch (master_id) { - case APM_LL_MASTER_LPCPU: - REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_LP_CORE_REGION_PMS, regn_pms); +/** + * @brief Enable/disable clock gating for HP2LP_PERI_PMS + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp2lp_peri_pms_enable_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(PMS_HP2LP_PERI_PMS_CLK_EN_REG, PMS_HP2LP_PERI_PMS_CLK_EN); + } else { + REG_SET_BIT(PMS_HP2LP_PERI_PMS_CLK_EN_REG, PMS_HP2LP_PERI_PMS_CLK_EN); + } +} + +/** + * @brief Enable/disable HP CPU access to an LP peripheral in HP2LP_PERI_PMS + * + * @param core_id CPU core ID + * @param mode Security mode + * @param sid LP peripheral slave ID + * @param enable True to enable access, false to disable + */ +static inline void apm_ll_hp2lp_peri_pms_enable_hpcpu_access(const int core_id, apm_security_mode_t mode, apm_slave_lp_periph_t sid, bool enable) +{ + uint32_t reg = PMS_HP_CORE0_MM_PMS_REG0_REG + + (core_id * APM_LL_HP2LP_PERI_PMS_CORE_OFFSET) + + (mode * APM_LL_HP2LP_PERI_PMS_MODE_OFFSET); + if (enable) { + REG_SET_BIT(reg, BIT(sid)); + } else { + REG_CLR_BIT(reg, BIT(sid)); + } +} + +/** + * @brief Enable/disable clock gating for LP_PERI_PMS + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_peri_pms_enable_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(PMS_LP_PERI_PMS_CLK_EN_REG, PMS_LP_PERI_PMS_CLK_EN); + } else { + REG_SET_BIT(PMS_LP_PERI_PMS_CLK_EN_REG, PMS_LP_PERI_PMS_CLK_EN); + } +} + +/** + * @brief Enable/disable LP CPU access to an LP peripheral in LP_PERI_PMS + * + * @param sid LP peripheral slave ID + * @param enable True to enable access, false to disable + */ +static inline void apm_ll_lp_peri_pms_enable_lpcpu_access(apm_slave_lp_periph_t sid, bool enable) +{ + if (enable) { + REG_SET_BIT(PMS_LP_MM_LP_PERI_PMS_REG0_REG, BIT(sid)); + } else { + REG_CLR_BIT(PMS_LP_MM_LP_PERI_PMS_REG0_REG, BIT(sid)); + } +} + +/** + * @brief Set region start address in LP_PERI_PMS + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_lp_peri_pms_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(PMS_PERI_REGION_LOW_REG(regn_num), addr); +} + +/** + * @brief Set region end address in LP_PERI_PMS + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_lp_peri_pms_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(PMS_PERI_REGION_HIGH_REG(regn_num), addr); +} + +/** + * @brief Set LP_PERI_PMS region access permissions for HP CPU core 0 + * + * @param mode Security mode + * @param regn_mask Bitmask of regions the core is permitted to access + */ +static inline void apm_ll_lp_peri_pms_hpcpu0_set_region_access(apm_security_mode_t mode, uint32_t regn_mask) +{ + uint32_t regn01 = regn_mask & APM_LL_LP_PERI_PMS_REGN0_1_MASK; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + uint32_t regn27 = (regn_mask >> APM_LL_LP_PERI_PMS_REGN2_7_SHIFT) & APM_LL_LP_PERI_PMS_REGN2_7_MASK; +#endif + + switch (mode) { + case APM_SEC_MODE_TEE: + /* regions 0–1 */ + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_MM_REGION_PMS, regn01); +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + /* regions 2–7 */ + REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_HP_CORE0_MM_REGION_2_TO_7_PMS, regn27); +#endif break; - case APM_LL_MASTER_HPCPU0: - if (sec_mode) { - REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_UM_REGION_PMS, regn_pms); - } else { - REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_MM_REGION_PMS, regn_pms); - } - break; - case APM_LL_MASTER_HPCPU1: - if (sec_mode) { - REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_UM_REGION_PMS, regn_pms); - } else { - REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_MM_REGION_PMS, regn_pms); - } + case APM_SEC_MODE_REE: + /* regions 0–1 */ + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_UM_REGION_PMS, regn01); +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + /* regions 2–7 */ + REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_HP_CORE0_UM_REGION_2_TO_7_PMS, regn27); +#endif break; default: - return -1; + break; } - - return 0; } /** - * @brief Configure APM controller clock gating. + * @brief Set LP_PERI_PMS region access permissions for HP CPU core 1 * - * @param apm_ctrl APM controller (LP_PERI/HP_PERI/HP_DMA/LP2HP_PERI/HP2LP_PERI). - * @param enable Permission enable/disable. - * enable: Enable automatic clock gating. - * disable: Keep the clock always on. + * @param mode Security mode + * @param regn_mask Bitmask of regions the core is permitted to access */ -static inline int apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) +static inline void apm_ll_lp_peri_pms_hpcpu1_set_region_access(apm_security_mode_t mode, uint32_t regn_mask) { - uint32_t reg = 0; + uint32_t regn01 = regn_mask & APM_LL_LP_PERI_PMS_REGN0_1_MASK; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + uint32_t regn27 = (regn_mask >> APM_LL_LP_PERI_PMS_REGN2_7_SHIFT) & APM_LL_LP_PERI_PMS_REGN2_7_MASK; +#endif - HAL_ASSERT(apm_ctrl < MAX_APM_CTRL); - - switch (apm_ctrl) { - case LP_APM_CTRL: - reg = PMS_LP_PERI_PMS_CLK_EN_REG; + switch (mode) { + case APM_SEC_MODE_TEE: + /* regions 0–1 */ + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_MM_REGION_PMS, regn01); +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + /* regions 2–7 */ + REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_HP_CORE1_MM_REGION_2_TO_7_PMS, regn27); +#endif break; - case HP2LP_APM_CTRL: - reg = PMS_HP2LP_PERI_PMS_CLK_EN_REG; - break; - case HP_APM_CTRL: - reg = PMS_HP_PERI_PMS_CLK_EN_REG; - break; - case LP2HP_APM_CTRL: - reg = PMS_LP2HP_PERI_PMS_CLK_EN_REG; - break; - case DMA_APM_CTRL: - reg = PMS_DMA_CLK_EN_REG; + case APM_SEC_MODE_REE: + /* regions 0–1 */ + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_UM_REGION_PMS, regn01); +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + /* regions 2–7 */ + REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_HP_CORE1_UM_REGION_2_TO_7_PMS, regn27); +#endif break; default: - return -1; + break; } +} +/** + * @brief Set LP_PERI_PMS region access permissions for LP CPU + * + * @param regn_mask Bitmask of regions the LP CPU is permitted to access + */ +static inline void apm_ll_lp_peri_pms_lpcpu_set_region_access(uint32_t regn_mask) +{ + /* regions 0–1 */ + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_LP_CORE_REGION_PMS, regn_mask & APM_LL_LP_PERI_PMS_REGN0_1_MASK); + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + /* regions 2–7 */ + REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_LP_CORE_REGION_2_TO_7_PMS, + (regn_mask >> APM_LL_LP_PERI_PMS_REGN2_7_SHIFT) & APM_LL_LP_PERI_PMS_REGN2_7_MASK); +#endif +} + +/** + * @brief Enable/disable clock gating for LP2HP_PERI_PMS + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp2hp_peri_pms_enable_clk_gating(bool enable) +{ if (enable) { - REG_CLR_BIT(reg, BIT(0)); + REG_CLR_BIT(PMS_LP2HP_PERI_PMS_CLK_EN_REG, PMS_LP2HP_PERI_PMS_CLK_EN); } else { - REG_SET_BIT(reg, BIT(0)); + REG_SET_BIT(PMS_LP2HP_PERI_PMS_CLK_EN_REG, PMS_LP2HP_PERI_PMS_CLK_EN); } - - return 0; } /** - * @brief Configure DMA configurable address range low address. + * @brief Enable/disable LP CPU access to a CPU peripheral in LP2HP_PERI_PMS * - * @param regn_num Configurable DMA address range number. - * @param regn_low_addr Configurable DMA address range start address. + * @param sid CPU peripheral slave ID + * @param enable True to enable access, false to disable */ -static inline void apm_ll_dma_region_set_low_address(uint32_t regn_num, uint32_t regn_low_addr) +static inline void apm_ll_lp2hp_peri_pms_enable_lpcpu_cpu_peri_access(apm_slave_cpu_periph_id_t sid, bool enable) { - HAL_ASSERT(regn_num < PMS_DMA_MAX_REGION_NUM); - - REG_WRITE((PMS_DMA_REGION0_LOW_REG + (regn_num * 8)), regn_low_addr); + if (enable) { + REG_SET_BIT(PMS_LP_MM_PMS_REG0_REG, BIT(sid)); + } else { + REG_CLR_BIT(PMS_LP_MM_PMS_REG0_REG, BIT(sid)); + } } /** - * @brief Configure DMA configurable address range high address. + * @brief Enable/disable LP CPU access to an HP peripheral (group 0) in LP2HP_PERI_PMS * - * @param regn_num Configurable DMA address range number. - * @param regn_high_addr Configurable DMA address range end address. + * @param sid HP peripheral group 0 slave ID + * @param enable True to enable access, false to disable */ -static inline void apm_ll_dma_region_set_high_address(uint32_t regn_num, uint32_t regn_high_addr) +static inline void apm_ll_lp2hp_peri_pms_enable_lpcpu_hp_peri0_access(apm_slave_hp_periph0_id_t sid, bool enable) { - HAL_ASSERT(regn_num < PMS_DMA_MAX_REGION_NUM); - - REG_WRITE((PMS_DMA_REGION0_HIGH_REG + (regn_num * 8)), regn_high_addr); + if (enable) { + REG_SET_BIT(PMS_LP_MM_PMS_REG1_REG, BIT(sid)); + } else { + REG_CLR_BIT(PMS_LP_MM_PMS_REG1_REG, BIT(sid)); + } } /** - * @brief Configure DMA configurable address range read permission. + * @brief Enable/disable LP CPU access to an HP peripheral (group 1) in LP2HP_PERI_PMS * - * @param dma_master DMA master whose access permission to be configured. - * @param regn_mask 32-bits field, each bit for corresponding DMA configurable address range permission. - * 0: Disable read permission. - * 1: Enable read permission. + * @param sid HP peripheral group 1 slave ID + * @param enable True to enable access, false to disable */ -static inline void apm_ll_dma_region_r_pms(apm_ll_dma_master_t dma_master, uint32_t regn_mask) +static inline void apm_ll_lp2hp_peri_pms_enable_lpcpu_hp_peri1_access(apm_slave_hp_periph1_id_t sid, bool enable) { - HAL_ASSERT(dma_master < PMS_DMA_MAX); - - REG_WRITE(PMS_DMA_PMS_R_REG(dma_master), regn_mask); -} - -/** - * @brief Configure DMA configurable address range write permission. - * - * @param dma_master DMA master whose access permission to be configured. - * @param regn_mask 32-bits field, each bit for corresponding DMA configurable address range permission. - * 0: Disable write permission. - * 1: Enable write permission. - */ -static inline void apm_ll_dma_region_w_pms(apm_ll_dma_master_t dma_master, uint32_t regn_mask) -{ - HAL_ASSERT(dma_master < PMS_DMA_MAX); - - REG_WRITE(PMS_DMA_PMS_W_REG(dma_master), regn_mask); + uint32_t reg = (sid < 32U) ? PMS_LP_MM_PMS_REG2_REG : PMS_LP_MM_PMS_REG3_REG; + if (enable) { + REG_SET_BIT(reg, BIT(sid & 0x1FU)); + } else { + REG_CLR_BIT(reg, BIT(sid & 0x1FU)); + } } #ifdef __cplusplus diff --git a/components/esp_hal_security/include/hal/apm_hal.h b/components/esp_hal_security/include/hal/apm_hal.h index 637009c3343..d4c2dee2e07 100644 --- a/components/esp_hal_security/include/hal/apm_hal.h +++ b/components/esp_hal_security/include/hal/apm_hal.h @@ -16,92 +16,7 @@ extern "C" { #include "hal/apm_ll.h" #include "hal/apm_types.h" -#if SOC_IS(ESP32P4) - -/** - * @brief DMA configurable region configuration data. - */ -typedef struct { - apm_ll_dma_master_t dma_master; /* DMA master whose access permission to be configured.*/ - uint32_t pms_r_mask; /* Read permission mask. */ - uint32_t pms_w_mask; /* Write permission mask. */ -} apm_hal_dma_region_config_data_t; - -/** - * @brief Configure HP peripherals access permission for the HP CPU0/1. - * - * @param master_id HP CPU0/1 - * @param hp_peri HP peripheral whose access permission to be configured. - * @param enable Permission enable/disable - */ -void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri, - apm_ll_secure_mode_t sec_mode, bool enable); - -/** - * @brief Configure LP peripherals access permission for the LP CPU. - * - * @param lp_peri LP peripheral whose access permission to be configured. - * @param enable Permission enable/disable - */ -void apm_hal_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable); - -/** - * @brief Configure peripherals configurable address ranges. - * - * @param regn_num Configurable address range number. - * @param regn_low_addr Configurable address range start address. - * @param regn_high_addr Configurable address range end address. - */ -void apm_hal_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr, - uint32_t regn_high_addr); - -/** - * @brief Configure peripherals configurable address ranges. - * - * @param master_id LP CPU and HP CPU0/1 - * @param sec_mode CPU privilege mode (Machine/User) which corresponds to (TEE/REE). - * @param regn_num Configurable address range number. - * @param regn_pms Configurable address range permission setting(2-bits field). - * Bit 0: Region 0 permission enable/disable. - * Bit 1: Region 1 permission enable/disable. - * @return Configuration performed successfully? - */ -int apm_hal_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode, - uint32_t regn_num, uint32_t regn_pms); - -/** - * @brief Configure APM controller clock gating. - * - * @param apm_ctrl APM controller (LP_PERI/HP_PERI/HP_DMA/LP2HP_PERI/HP2LP_PERI). - * @param enable Permission enable/disable. - * enable: Enable automatic clock gating. - * disable: Keep the clock always on. - * @return Clock gating set successfully? - */ -int apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable); - -/** - * @brief Configure DMA configurable address range low address. - * - * @param regn_num Configurable DMA address range number. - * @param regn_low_addr Configurable DMA address range start address. - * @param regn_high_addr Configurable DMA address range end address. - */ -void apm_hal_dma_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr); - -/** - * @brief Configure DMA configurable address range read permission. - * - * @param pms_data DMA configurable region configuration data. - * @param dma_master DMA master whose access permission to be configured. - * @param regn_mask 32-bits field, each bit for corresponding DMA configurable address range permission. - * 0: Disable read permission. - * 1: Enable read permission. - */ -void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data); - -#else - +#if SOC_APM_CTRL_FILTER_SUPPORTED /** * @brief Helper macro to create a region entry configuration * @@ -357,10 +272,225 @@ void apm_hal_enable_reset_event_bypass(bool enable); * @param enable True to enable, false to disable */ void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable); +#else +/** + * @brief HP_PERI_PMS permission configuration structure + */ +typedef struct { + uint32_t cpu_peri; /*!< Bitmask for CPU_PERIPH slaves */ + uint32_t hp_peri0; /*!< Bitmask for HP_PERIPH0 slaves */ + uint64_t hp_peri1; /*!< Bitmask for HP_PERIPH1 slaves */ +} apm_hal_pms_hp_peri_cfg_t; -#endif //SOC_IS(ESP32P4) +/** + * @brief PMS region configuration structure + */ +typedef struct { + uint32_t regn_num; /*!< Region number */ + uint32_t regn_start_addr; /*!< Region start address */ + uint32_t regn_end_addr; /*!< Region end address */ +} apm_hal_pms_regn_cfg_t; -#elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOCKconfig_APM_SUPPORTED +/** + * @brief PMS master configuration structure + */ +typedef struct { + union { + struct { + apm_master_dma_id_t id; /*!< DMA master ID */ + uint32_t regn_pms_rd; /*!< Bitmask of regions the master is permitted to read */ + uint32_t regn_pms_wr; /*!< Bitmask of regions the master is permitted to write */ + } dma; + struct { + apm_master_id_t id; /*!< Master ID */ + apm_security_mode_t mode; /*!< Security mode */ + uint32_t regn_pms; /*!< Bitmask of regions the master is permitted to access */ + } lp_peri; + }; +} apm_hal_pms_master_cfg_t; + +/** + * @brief Helper macro to create a PMS region entry configuration + */ +#define APM_HAL_PMS_REGION_ENTRY(NUM, START, END) \ + { \ + .regn_num = (NUM), \ + .regn_start_addr = (START), \ + .regn_end_addr = (END), \ + } + +/** + * @brief Helper macro to create a DMA_PMS master entry configuration + */ +#define APM_HAL_DMA_PMS_MASTER_ENTRY(ID, R_PMS, W_PMS) \ + { \ + .dma = { \ + .id = (ID), \ + .regn_pms_rd = (R_PMS), \ + .regn_pms_wr = (W_PMS), \ + }, \ + } + +/** + * @brief Helper macro to create an LP_PERI_PMS master entry configuration + */ +#define APM_HAL_LP_PERI_PMS_MASTER_ENTRY(ID, MODE, REGN_PMS) \ + { \ + .lp_peri = { \ + .id = (ID), \ + .mode = (MODE), \ + .regn_pms = (REGN_PMS), \ + }, \ + } + +/** + * @brief Set DMA_PMS region address bounds + * + * @param regn_num Region number + * @param start_addr Region start address + * @param end_addr Region end address + */ +void apm_hal_dma_pms_set_region_bounds(uint32_t regn_num, uint32_t start_addr, uint32_t end_addr); + +/** + * @brief Set DMA_PMS read/write region access mask for a DMA master + * + * @param mid DMA master ID + * @param regn_rd_mask Bitmask of regions the master is permitted to read + * @param regn_wr_mask Bitmask of regions the master is permitted to write + */ +void apm_hal_dma_pms_set_master_region_attr(apm_master_dma_id_t mid, uint32_t regn_rd_mask, uint32_t regn_wr_mask); + +/** + * @brief Set DMA_PMS region configurations + * + * @param regn_count Number of regions to configure + * @param regn_cfg Array of region configurations + */ +void apm_hal_dma_pms_set_region_cfg(uint32_t regn_count, const apm_hal_pms_regn_cfg_t *regn_cfg); + +/** + * @brief Set DMA_PMS master configurations + * + * @param master_count Number of masters to configure + * @param cfg Array of master configurations + */ +void apm_hal_dma_pms_set_master_cfg(uint32_t master_count, const apm_hal_pms_master_cfg_t *cfg); + +/** + * @brief Set HP2LP_PERI_PMS access permissions for HP CPU + * + * @param core_id CPU core ID + * @param mode Security mode + * @param enable_mask Bitmask of LP peripherals to enable access to + */ +void apm_hal_hp2lp_peri_pms_set_hpcpu_access(int core_id, apm_security_mode_t mode, uint32_t enable_mask); + +/** + * @brief Set LP_PERI_PMS access permissions for LP CPU + * + * @param enable_mask Bitmask of LP peripherals to enable access to + */ +void apm_hal_lp_peri_pms_set_lpcpu_access(uint32_t enable_mask); + +/** + * @brief Set HP_PERI PMS access permissions for HP CPU + * + * @param core_id CPU core ID + * @param mode Security mode + * @param cfg HP peripheral permission configuration + */ +void apm_hal_hp_peri_pms_set_hpcpu_access(int core_id, apm_security_mode_t mode, const apm_hal_pms_hp_peri_cfg_t *cfg); + +/** + * @brief Set LP2HP_PERI PMS access permissions for LP CPU + * + * @param cfg HP peripheral permission configuration + */ +void apm_hal_lp2hp_peri_pms_set_lpcpu_access(const apm_hal_pms_hp_peri_cfg_t *cfg); + +/** + * @brief Set LP_PERI_PMS region address bounds + * + * @param regn_num Region number + * @param start_addr Region start address + * @param end_addr Region end address + */ +void apm_hal_lp_peri_pms_set_region_bounds(uint32_t regn_num, uint32_t start_addr, uint32_t end_addr); + +/** + * @brief Set LP_PERI_PMS region access mask for a master + * + * @param mid Master ID + * @param mode Security mode + * @param regn_pms_mask Bitmask of regions the master is permitted to access + */ +void apm_hal_lp_peri_pms_set_master_region_attr(apm_master_id_t mid, apm_security_mode_t mode, uint32_t regn_pms_mask); + +/** + * @brief Set LP_PERI_PMS region configurations + * + * @param regn_count Number of regions to configure + * @param regn_cfg Array of region configurations + */ +void apm_hal_lp_peri_pms_set_region_cfg(uint32_t regn_count, const apm_hal_pms_regn_cfg_t *regn_cfg); + +/** + * @brief Set LP_PERI_PMS master configurations + * + * @param master_count Number of masters to configure + * @param master_cfg Array of master configurations + */ +void apm_hal_lp_peri_pms_set_master_cfg(uint32_t master_count, const apm_hal_pms_master_cfg_t *master_cfg); + +/** + * @brief Enable/disable PMS violation interrupt for a controller module + * + * @param ctrl_mod APM controller module + * @param enable True to enable, false to disable + */ +void apm_hal_enable_intr(apm_ctrl_module_t ctrl_mod, bool enable); + +/** + * @brief Clear PMS violation interrupt for a controller module + * + * @param ctrl_mod APM controller module + */ +void apm_hal_clear_intr(apm_ctrl_module_t ctrl_mod); + +/** + * @brief Get the combined interrupt status for all PMS controller modules + * + * @return Bitmask of modules with a pending interrupt + */ +uint32_t apm_hal_get_intr_status(void); + +/** + * @brief Get PMS violation exception information + * + * @param type Exception type identifier + * @param excp_info Pointer to structure to fill with exception details + */ +void apm_hal_get_exception_info(apm_ctrl_exception_type type, apm_ctrl_exception_info_t *excp_info); + +/** + * @brief Get interrupt source number for a PMS controller module + * + * @param ctrl_mod APM controller module + * @return Interrupt source number + */ +int apm_hal_get_intr_src_num(apm_ctrl_module_t ctrl_mod); + +/** + * @brief Enable/disable clock gating for a PMS controller module + * + * @param ctrl_mod APM controller module + * @param enable True to enable, false to disable + */ +void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable); +#endif // SOC_APM_CTRL_FILTER_SUPPORTED + +#elif SOC_APM_CTRL_FILTER_SUPPORTED // SOC_APM_CTRL_FILTER_SUPPORTED #if SOC_IS(ESP32H4) #include "soc/hp_apm_reg.h" diff --git a/components/esp_hal_security/include/hal/apm_types.h b/components/esp_hal_security/include/hal/apm_types.h index b01633c3f75..8e84d78d489 100644 --- a/components/esp_hal_security/include/hal/apm_types.h +++ b/components/esp_hal_security/include/hal/apm_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,11 +7,14 @@ #include #include "soc/soc_caps.h" +#include "esp_bit_defs.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { #endif +#if SOC_APM_CTRL_FILTER_SUPPORTED /** * @brief Master IDs for APM */ @@ -95,6 +98,229 @@ typedef enum { APM_SEC_MODE_REE2 = 3, /*!< Rich Execution Environment mode 2 */ } apm_security_mode_t; +/** + * @brief APM controller exception info structure + */ +typedef struct { + uint32_t regn; /*!< Region number */ + uint32_t mode; /*!< Security mode */ + uint32_t id; /*!< Master ID */ + uint32_t type; /*!< Exception type */ + uint32_t addr; /*!< Exception address */ +} apm_ctrl_exception_info_t; +#else +/** + * @brief Security modes for APM + */ +typedef enum { + APM_SEC_MODE_TEE = 0, /*!< Trusted Execution Environment mode (M-mode) */ + APM_SEC_MODE_REE = 1, /*!< Rich Execution Environment mode (U-mode) */ +} apm_security_mode_t; + +/** + * @brief APM controller modules + */ +typedef enum { + APM_CTRL_DMA_PMS = 0, /*!< DMA APM controller */ + APM_CTRL_HP_PERI_PMS, /*!< High-performance APM controller */ + APM_CTRL_HP2LP_PERI_PMS, /*!< High-performance to Low-power APM controller */ + APM_CTRL_LP_PERI_PMS, /*!< Low-power APM controller */ + APM_CTRL_LP2HP_PERI_PMS, /*!< Low-power to High-performance APM controller */ +} apm_ctrl_module_t; + +/** + * @brief Master IDs for APM + */ +typedef enum { + APM_MASTER_HPCPU0 = 0, /*!< High-performance CPU core 0 */ + APM_MASTER_HPCPU1, /*!< High-performance CPU core 1 */ + APM_MASTER_LPCPU, /*!< Low-power CPU */ + APM_MASTER_DMA, /*!< DMA masters */ +} apm_master_id_t; + +/** + * @brief DMA master IDs for APM + */ +typedef enum { + APM_MASTER_DMA_GDMA_CH0 = 0, + APM_MASTER_DMA_GDMA_CH1, + APM_MASTER_DMA_GDMA_CH2, + APM_MASTER_DMA_GDMA_CH3, + APM_MASTER_DMA_AHB_PDMA_ADC, + APM_MASTER_DMA_AHB_PDMA_I2S0, + APM_MASTER_DMA_AHB_PDMA_I2S1, + APM_MASTER_DMA_AHB_PDMA_I2S2, + APM_MASTER_DMA_AHB_PDMA_I3C_MST, + APM_MASTER_DMA_AHB_PDMA_UHCI0, + APM_MASTER_DMA_AHB_PDMA_RMT, + APM_MASTER_DMA_AXI_PDMA_LCDCAM = 13, + APM_MASTER_DMA_AXI_PDMA_GPSPI2, + APM_MASTER_DMA_AXI_PDMA_GPSPI3, + APM_MASTER_DMA_AXI_PDMA_PARLIO, + APM_MASTER_DMA_AXI_PDMA_AES, + APM_MASTER_DMA_AXI_PDMA_SHA, + APM_MASTER_DMA_DMA2D_JPEG, + APM_MASTER_DMA_USBOTG_HS, + APM_MASTER_DMA_GMAC, + APM_MASTER_DMA_SDMMC, + APM_MASTER_DMA_USBOTG_FS, + APM_MASTER_DMA_TRACE0, + APM_MASTER_DMA_TRACE1, + APM_MASTER_DMA_L2MEM_MON, + APM_MASTER_DMA_SPM_MON, + APM_MASTER_DMA_H264 = 30, + APM_MASTER_DMA_DMA2D_PPA, + APM_MASTER_DMA_DMA2D_DUMMY, + APM_MASTER_DMA_AHB_PDMA_DUMMY, + APM_MASTER_DMA_AXI_PDMA_DUMMY, + APM_MASTER_DMA_MAX, +} apm_master_dma_id_t; + +/** + * @brief HP peripheral slave IDs for APM + */ +typedef enum { + APM_SLAVE_PSRAM = 0, + APM_SLAVE_FLASH, + APM_SLAVE_L2MEM, + APM_SLAVE_L2ROM, + APM_SLAVE_TRACE0 = 6, + APM_SLAVE_TRACE1, + APM_SLAVE_CPU_BUS_MON, + APM_SLAVE_L2MEM_MON, + APM_SLAVE_SPM_MON, + APM_SLAVE_CACHE, + APM_SLAVE_CPU_PERIPH_MAX, +} apm_slave_cpu_periph_id_t; + +typedef enum { + APM_SLAVE_HP_USBOTG_HS = 0, + APM_SLAVE_HP_USBOTG_FS, + APM_SLAVE_HP_USBOTG_FS_WRAP, + APM_SLAVE_HP_GDMA, + APM_SLAVE_HP_SDMMC = 5, + APM_SLAVE_HP_AHB_PDMA, + APM_SLAVE_HP_JPEG, + APM_SLAVE_HP_PPA, + APM_SLAVE_HP_DMA2D, + APM_SLAVE_HP_KEY_MANAGER, + APM_SLAVE_HP_AXI_PDMA, + APM_SLAVE_HP_FLASH_MSPI, + APM_SLAVE_HP_PSRAM_MSPI, + APM_SLAVE_HP_CRYPTO, + APM_SLAVE_HP_GMAC, + APM_SLAVE_HP_USB_PHY, + APM_SLAVE_HP_PVT, + APM_SLAVE_HP_CSI_HOST, + APM_SLAVE_HP_DSI_HOST, + APM_SLAVE_HP_ISP, + APM_SLAVE_HP_H264_CORE, + APM_SLAVE_HP_RMT, + APM_SLAVE_HP_BITSCRAMBLER, + APM_SLAVE_HP_AXI_ICM, + APM_SLAVE_HP_PERI_PMS, + APM_SLAVE_LP2HP_PERI_PMS, + APM_SLAVE_DMA_PMS, + APM_SLAVE_HP_H264_DMA2D, + APM_SLAVE_AXI_PERF_MON, + APM_SLAVE_HP_PERIPH0_MAX, +} apm_slave_hp_periph0_id_t; + +typedef enum { + APM_SLAVE_HP_MCPWM0, + APM_SLAVE_HP_MCPWM1, + APM_SLAVE_HP_TG0, + APM_SLAVE_HP_TG1, + APM_SLAVE_HP_I2C0, + APM_SLAVE_HP_I2C1, + APM_SLAVE_HP_I2S0, + APM_SLAVE_HP_I2S1, + APM_SLAVE_HP_I2S2, + APM_SLAVE_HP_PCNT, + APM_SLAVE_HP_UART0, + APM_SLAVE_HP_UART1, + APM_SLAVE_HP_UART2, + APM_SLAVE_HP_UART3, + APM_SLAVE_HP_UART4, + APM_SLAVE_HP_PARLIO, + APM_SLAVE_HP_GPSPI2, + APM_SLAVE_HP_GPSPI3, + APM_SLAVE_HP_USBDEVICE, + APM_SLAVE_HP_LEDC, + APM_SLAVE_HP_ETM = 21, + APM_SLAVE_HP_INTMTX, + APM_SLAVE_HP_TWAI0, + APM_SLAVE_HP_TWAI1, + APM_SLAVE_HP_TWAI2, + APM_SLAVE_HP_I3C_MST, + APM_SLAVE_HP_I3C_SLV, + APM_SLAVE_HP_LCDCAM, + APM_SLAVE_HP_ADC = 30, + APM_SLAVE_HP_UHCI, + APM_SLAVE_HP_GPIO = 32, + APM_SLAVE_HP_IOMUX, + APM_SLAVE_HP_SYSTIMER, + APM_SLAVE_HP_SYS_REG, + APM_SLAVE_HP_CLKRST, + APM_SLAVE_HP_PERIPH1_MAX, +} apm_slave_hp_periph1_id_t; + +/** + * @brief LP peripheral slave IDs for APM + */ +typedef enum { + APM_SLAVE_LP_SYSREG = 0, + APM_SLAVE_LP_AONCLKRST, + APM_SLAVE_LP_TIMER, + APM_SLAVE_LP_ANAPERI, + APM_SLAVE_LP_PMU, + APM_SLAVE_LP_WDT, + APM_SLAVE_LP_MAILBOX, + APM_SLAVE_LP_RTC, + APM_SLAVE_LP_PERICLKRST, + APM_SLAVE_LP_UART, + APM_SLAVE_LP_I2C, + APM_SLAVE_LP_SPI, + APM_SLAVE_LP_I2CMST, + APM_SLAVE_LP_I2S, + APM_SLAVE_LP_ADC, + APM_SLAVE_LP_TOUCH, + APM_SLAVE_LP_IOMUX, + APM_SLAVE_LP_INTR, + APM_SLAVE_LP_EFUSE, + APM_SLAVE_LP_PERI_PMS, + APM_SLAVE_HP2LP_PERI_PMS, + APM_SLAVE_LP_TSENS, + APM_SLAVE_LP_HUK, + APM_SLAVE_LP_SRAM, +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + APM_SLAVE_LP_TRNG, +#endif + APM_SLAVE_LP_PERIPH_MAX, +} apm_slave_lp_periph_t; + +/** + * @brief APM ADDRHOLE exception types + */ +typedef enum { + APM_EXCP_NONE = 0, /*!< No exception */ + APM_EXCP_HP_AXI = BIT(0), /*!< Exception from illegal access in HP AXI matrix */ + APM_EXCP_HP_AHB = BIT(1), /*!< Exception from illegal access in HP CPU and AHB matrix */ + APM_EXCP_LP_AHB = BIT(2), /*!< Exception from illegal access in LP AHB matrix */ + APM_EXCP_LP_IDBUS = BIT(3), /*!< Exception from illegal access on LP CPU IBUS or DBUS */ +} apm_ctrl_exception_type; + +/** + * @brief Exception info structure + */ +typedef struct { + uint32_t addr; /*!< Faulting address */ + uint8_t id; /*!< Master ID */ + bool is_wr; /*!< True indicates Write transaction, else Read transaction */ + bool is_secure; /*!< True indicates illegal address access (space exception), else access without permission (authority exception) */ +} apm_ctrl_exception_info_t; +#endif + /** * @brief Access permission flags */ @@ -106,17 +332,6 @@ typedef enum { APM_PERM_ALL = 7, /*!< All access */ } apm_perm_t; -/** - * @brief APM controller exception info structure - */ -typedef struct { - uint32_t regn; /*!< Region number */ - uint32_t mode; /*!< Security mode */ - uint32_t id; /*!< Master ID */ - uint32_t type; /*!< Exception type */ - uint32_t addr; /*!< Exception address */ -} apm_ctrl_exception_info_t; - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/axi_icm_ll.h b/components/hal/esp32p4/include/hal/axi_icm_ll.h index bfeb5225b95..18ce0dee579 100644 --- a/components/hal/esp32p4/include/hal/axi_icm_ll.h +++ b/components/hal/esp32p4/include/hal/axi_icm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,15 +17,38 @@ extern "C" { #endif typedef enum { - AXI_ICM_MASTER_CPU = 0, // An aggregate master port for other users, like HP CPU, LP CPU, USB, EMAC, SDMMC, AHB-GDMA, etc - AXI_ICM_MASTER_CACHE = 1, // Cache master port - AXI_ICM_MASTER_DW_GDMA_M0 = 5, // DW-GDMA master port 0 - AXI_ICM_MASTER_DW_GDMA_M1 = 6, // DW-GDMA master port 1 - AXI_ICM_MASTER_GDMA = 8, // AXI-GDMA - AXI_ICM_MASTER_DMA2D = 10, // DMA2D - AXI_ICM_MASTER_H264_M0 = 11, // H264 master port 0 - AXI_ICM_MASTER_H264_M1 = 12, // H264 master port 1 -} axi_icm_ll_master_id_t; + AXI_ICM_MASTER_CPU = 0, // An aggregate master port for other users, like HP CPU, LP CPU, USB, EMAC, SDMMC, AHB-GDMA, etc + AXI_ICM_MASTER_CACHE = 1, // Cache master port + AXI_ICM_MASTER_DW_GDMA_M0 = 5, // DW-GDMA master port 0 + AXI_ICM_MASTER_DW_GDMA_M1 = 6, // DW-GDMA master port 1 + AXI_ICM_MASTER_GDMA = 8, // AXI-GDMA + AXI_ICM_MASTER_DMA2D = 10, // DMA2D + AXI_ICM_MASTER_H264_M0 = 11, // H264 master port 0 + AXI_ICM_MASTER_H264_M1 = 12, // H264 master port 1 +} axi_icm_ll_sys_master_id_t; + +typedef enum { + AXI_ICM_CPU_MASTER_HP_CPU0 = 0, // HP CPU core 0 + AXI_ICM_CPU_MASTER_HP_CPU1 = 1, // HP CPU core 1 + AXI_ICM_CPU_MASTER_LP_CPU = 2, // LP CPU + AXI_ICM_CPU_MASTER_USBOTG_FS = 3, // USB OTG full-speed + AXI_ICM_CPU_MASTER_REGDMA = 4, // REGDMA + AXI_ICM_CPU_MASTER_GMAC = 5, // GMAC + AXI_ICM_CPU_MASTER_SDMMC = 6, // SDMMC + AXI_ICM_CPU_MASTER_USBOTG_HS = 7, // USB OTG high-speed + AXI_ICM_CPU_MASTER_TRACE0 = 8, // Trace 0 + AXI_ICM_CPU_MASTER_TRACE1 = 9, // Trace 1 + AXI_ICM_CPU_MASTER_TCM_MON = 10, // TCM monitor + AXI_ICM_CPU_MASTER_L2MEM_MON = 11, // L2MEM monitor + AXI_ICM_CPU_MASTER_AHB_PDMA_I3C = 16, // AHB PDMA I3C + AXI_ICM_CPU_MASTER_AHB_PDMA_UHCI = 18, // AHB PDMA UHCI + AXI_ICM_CPU_MASTER_AHB_PDMA_I2S0 = 19, // AHB PDMA I2S0 + AXI_ICM_CPU_MASTER_AHB_PDMA_I2S1 = 20, // AHB PDMA I2S1 + AXI_ICM_CPU_MASTER_AHB_PDMA_I2S2 = 21, // AHB PDMA I2S + AXI_ICM_CPU_MASTER_AHB_PDMA_ADC = 24, // AHB PDMA ADC + AXI_ICM_CPU_MASTER_AHB_PDMA_RMT = 26, // AHB PDMA RMT + AXI_ICM_CPU_MASTER_MAX = 31, +} axi_icm_ll_cpu_master_id_t; /** * @brief AXI ICM has independent channels for read and write access. @@ -35,6 +58,25 @@ typedef enum { AXI_ICM_ACCESS_WRITE = 1, } axi_icm_ll_access_type_t; +/** + * @brief AXI ICM interrupt types + */ +typedef enum { + AXI_ICM_INTR_DEADLOCK = 0, /*!< Deadlock interrupt */ + AXI_ICM_INTR_SYS_ADDRHOLE = 1, /*!< System addrhole interrupt */ + AXI_ICM_INTR_CPU_ADDRHOLE = 2, /*!< CPU addrhole interrupt */ +} axi_icm_ll_intr_type_t; + +/** + * @brief AXI ICM addrhole exception info + */ +typedef struct { + uint32_t addr; /*!< Faulting address */ + uint8_t id; /*!< Master ID */ + bool is_wr; /*!< Write access */ + bool is_secure; /*!< Secure access */ +} axi_icm_ll_excp_info_t; + /** * @brief Set QoS burstiness for a master port, also enable the regulator * @@ -42,7 +84,7 @@ typedef enum { * @param burstiness Burstiness value. It represents the depth of the token bucket. * @param access_type 0: read, 1: write */ -static inline void axi_icm_ll_set_qos_burstiness(axi_icm_ll_master_id_t mid, uint32_t burstiness, axi_icm_ll_access_type_t access_type) +static inline void axi_icm_ll_set_qos_burstiness(axi_icm_ll_sys_master_id_t mid, uint32_t burstiness, axi_icm_ll_access_type_t access_type) { HAL_ASSERT(burstiness >= 1 && burstiness <= 256); // wait for the previous command to finish @@ -80,7 +122,7 @@ static inline void axi_icm_ll_set_qos_burstiness(axi_icm_ll_master_id_t mid, uin * @param transaction_level Transaction level, lower value means higher rate * @param access_type 0: read, 1: write */ -static inline void axi_icm_ll_set_qos_peak_transaction_rate(axi_icm_ll_master_id_t mid, uint32_t peak_level, +static inline void axi_icm_ll_set_qos_peak_transaction_rate(axi_icm_ll_sys_master_id_t mid, uint32_t peak_level, uint32_t transaction_level, axi_icm_ll_access_type_t access_type) { HAL_ASSERT(peak_level < transaction_level && transaction_level <= 11); @@ -186,6 +228,68 @@ static inline void axi_icm_ll_set_cpu_qos_arbiter_prio(uint32_t write_prio, uint AXI_ICM.mst_arqos_reg0.reg_cpu_arqos = read_prio; } +/** + * @brief Enable/disable AXI ICM interrupt + * + * @param mask Interrupt mask (use BIT(axi_icm_ll_intr_type_t)) + * @param enable true to enable, false to disable + */ +static inline void axi_icm_ll_enable_intr(uint32_t mask, bool enable) +{ + if (enable) { + AXI_ICM.int_ena.val |= mask; + } else { + AXI_ICM.int_ena.val &= ~mask; + } +} + +/** + * @brief Get AXI ICM interrupt status + * + * @param mask Interrupt mask + * @return Status mask + */ +static inline uint32_t axi_icm_ll_get_intr_status(uint32_t mask) +{ + return AXI_ICM.int_st.val & mask; +} + +/** + * @brief Clear AXI ICM interrupt + * + * @param mask Interrupt mask + */ +static inline void axi_icm_ll_clear_intr(uint32_t mask) +{ + AXI_ICM.int_clr.val = mask; +} + +/** + * @brief Get SYS addrhole exception info + * + * @param[out] info Pointer to store exception information + */ +static inline void axi_icm_ll_get_sys_excp_info(axi_icm_ll_excp_info_t *info) +{ + info->addr = AXI_ICM.sys_addrhole_addr.reg_icm_sys_addrhole_addr; + info->id = AXI_ICM.sys_addrhole_info.reg_icm_sys_addrhole_id; + info->is_wr = AXI_ICM.sys_addrhole_info.reg_icm_sys_addrhole_wr; + info->is_secure = AXI_ICM.sys_addrhole_info.reg_icm_sys_addrhole_secure; +} + +/** + * @brief Get CPU addrhole exception info + * + * @param[out] info Pointer to store exception information + */ +static inline void axi_icm_ll_get_cpu_excp_info(axi_icm_ll_excp_info_t *info) +{ + info->addr = AXI_ICM.cpu_addrhole_addr.reg_icm_cpu_addrhole_addr; + info->id = AXI_ICM.cpu_addrhole_info.reg_icm_cpu_addrhole_id; + info->is_wr = AXI_ICM.cpu_addrhole_info.reg_icm_cpu_addrhole_wr; + info->is_secure = AXI_ICM.cpu_addrhole_info.reg_icm_cpu_addrhole_secure; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/lp_sys_ll.h b/components/hal/esp32p4/include/hal/lp_sys_ll.h index 71d5371e9ac..0f630c658fa 100644 --- a/components/hal/esp32p4/include/hal/lp_sys_ll.h +++ b/components/hal/esp32p4/include/hal/lp_sys_ll.h @@ -25,6 +25,29 @@ extern "C" { #define MEM_AUX_LIGHTSLEEP BIT(1) #define MEM_AUX_DEEPSLEEP BIT(2) +/** + * @brief LP SYS interrupt types + */ +typedef enum { + LP_SYS_INTR_LP_ADDRHOLE = 0, /*!< LP addrhole interrupt (LP peri, LP RAM TEE APM, LP matrix default slave) */ + LP_SYS_INTR_IDBUS_ADDRHOLE = 1, /*!< IDBUS addrhole interrupt (LP CPU ibus and dbus) */ + LP_SYS_INTR_LP_CORE_AHB_TOUT = 2, /*!< LP core AHB bus timeout interrupt */ + LP_SYS_INTR_LP_CORE_IBUS_TOUT = 3, /*!< LP core ibus timeout interrupt */ + LP_SYS_INTR_LP_CORE_DBUS_TOUT = 4, /*!< LP core dbus timeout interrupt */ + LP_SYS_INTR_ETM_TASK_ULP = 5, /*!< ETM task ULP interrupt */ + LP_SYS_INTR_SLOW_CLK_TICK = 6, /*!< Slow clock tick interrupt */ +} lp_sys_ll_intr_type_t; + +/** + * @brief LP SYS addrhole exception info + */ +typedef struct { + uint32_t addr; /*!< Faulting address */ + uint8_t id; /*!< Master ID */ + bool is_wr; /*!< Write access */ + bool is_secure; /*!< Secure access */ +} lp_sys_ll_excp_info_t; + /** * @brief ROM obtains the wake-up type through LP_SYS_STORE9_REG[0]. * Set the flag to inform @@ -100,6 +123,60 @@ static inline uint32_t lp_sys_ll_load_wakeup_cause(void) return REG_READ(RTC_LP_CORE_STORE_WAKEUP_REG); } +FORCE_INLINE_ATTR void lp_sys_ll_enable_intr(uint32_t mask, bool enable) +{ + if (enable) { + LP_SYS.int_ena.val |= mask; + } else { + LP_SYS.int_ena.val &= ~mask; + } +} + +FORCE_INLINE_ATTR uint32_t lp_sys_ll_get_intr_status(uint32_t mask) +{ + return LP_SYS.int_st.val & mask; +} + +FORCE_INLINE_ATTR void lp_sys_ll_clear_intr(uint32_t mask) +{ + LP_SYS.int_clr.val = mask; +} + +FORCE_INLINE_ATTR uint32_t lp_sys_ll_get_ahb_excp_addr(void) +{ + return LP_SYS.lp_addrhole_addr.lp_addrhole_addr; +} + +FORCE_INLINE_ATTR void lp_sys_ll_get_ahb_excp_info(lp_sys_ll_excp_info_t *info) +{ + info->addr = LP_SYS.lp_addrhole_addr.lp_addrhole_addr; + info->id = LP_SYS.lp_addrhole_info.lp_addrhole_id; + info->is_wr = LP_SYS.lp_addrhole_info.lp_addrhole_wr; + info->is_secure = LP_SYS.lp_addrhole_info.lp_addrhole_secure; +} + +FORCE_INLINE_ATTR uint32_t lp_sys_ll_get_idbus_excp_addr(void) +{ + return LP_SYS.idbus_addrhole_addr.idbus_addrhole_addr; +} + +FORCE_INLINE_ATTR void lp_sys_ll_get_idbus_excp_info(lp_sys_ll_excp_info_t *info) +{ + info->addr = LP_SYS.idbus_addrhole_addr.idbus_addrhole_addr; + info->id = LP_SYS.idbus_addrhole_info.idbus_addrhole_id; + info->is_wr = LP_SYS.idbus_addrhole_info.idbus_addrhole_wr; + info->is_secure = LP_SYS.idbus_addrhole_info.idbus_addrhole_secure; +} + +FORCE_INLINE_ATTR void lp_sys_ll_enable_lp_core_err_resp(bool enable) +{ + if (enable) { + LP_SYS.lp_core_err_resp_dis.val = 0x00U; + } else { + LP_SYS.lp_core_err_resp_dis.val = 0x07U; + } +} + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/apm_defs.h b/components/soc/esp32p4/include/soc/apm_defs.h new file mode 100644 index 00000000000..2461baacb6f --- /dev/null +++ b/components/soc/esp32p4/include/soc/apm_defs.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Number of configurable DMA_PMS regions */ +#define APM_DMA_PMS_REGION_NUM (32) +/* Alignment required for start/end addresses for DMA_PMS regions */ +#define APM_DMA_PMS_REGION_ADDR_ALIGN (0x1000) +/* Register offset between DMA_PMS region bound address registers */ +#define APM_DMA_PMS_REGION_ADDR_OFFSET (0x08) +/* Register offset between DMA_PMS region attribute registers */ +#define APM_DMA_PMS_REGION_ATTR_OFFSET (0x08) + +/* Number of configurable LP_PERI_PMS regions */ +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define APM_LP_PERI_PMS_REGION_NUM (2) +#else +#define APM_LP_PERI_PMS_REGION_NUM (8) +#endif +/* Alignment required for start/end addresses for LP_PERI_PMS regions */ +#define APM_LP_PERI_PMS_REGION_ADDR_ALIGN (4) + +/* Number of configurable MSPI PMS regions (flash/PSRAM) */ +#define APM_MSPI_PMS_REGION_NUM (4) +/* Alignment required for start/end addresses for MSPI_PMS regions */ +#define APM_MSPI_PMS_REGION_ADDR_ALIGN (0x1000) + +/* CPU_PERIPH slave mask */ +#define APM_SLAVE_CPU_PERI_ALL_MASK (0x0FCFU) +/* HP_PERIPH0 slave mask */ +#define APM_SLAVE_HP_PERI0_ALL_MASK (0x3FFFFFEFU) +/* HP_PERIPH1 slave mask */ +#define APM_SLAVE_HP_PERI1_ALL_MASK (0x1FDFEFFFFFULL) +/* LP_PERIPH slave mask */ +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define APM_SLAVE_LP_PERI_ALL_MASK (0x00FFFFFFU) +#else +#define APM_SLAVE_LP_PERI_ALL_MASK (0x01FFFFFFU) +#endif + +#ifdef __cplusplus +} +#endif From 4c39f0d006ccd74406ed98c80a0bfdd35eaaf933 Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Wed, 25 Feb 2026 17:54:36 +0530 Subject: [PATCH 3/3] ci(hal): Extend support for ESP32-P4 for the PMS HAL test-app --- .../pms_and_cpu_intr/CMakeLists.txt | 12 +- .../pms_and_cpu_intr/include/test_pms.h | 22 +- .../priv_include/esp32c5/test_pms_params.h | 4 +- .../priv_include/esp32c6/test_pms_params.h | 2 +- .../priv_include/esp32c61/test_pms_params.h | 2 +- .../priv_include/esp32h2/test_pms_params.h | 2 +- .../priv_include/esp32p4/test_pms_params.h | 63 ++ .../priv_include/test_pms_priv.h | 36 +- .../src/common/test_apm_utils.c | 239 +++++- .../src/common/test_panic_handler.c | 13 +- .../src/common/test_setup_utils.c | 53 +- .../src/pms/test_tee_peri_apm.c | 25 +- .../pms_and_cpu_intr/src/pms/test_tee_pms.c | 740 ++++++++++++++++++ .../src/pms/test_tee_sys_apm.c | 77 +- .../src/ulp/ulp_lp_core_main.c | 35 +- .../test_apps/tee/main/test_pms.c | 114 ++- .../test_apps/tee/pytest_pms_and_cpu_intr.py | 4 +- .../test_apps/tee/sdkconfig.defaults.esp32p4 | 8 + 18 files changed, 1344 insertions(+), 107 deletions(-) create mode 100644 components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32p4/test_pms_params.h create mode 100644 components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_pms.c diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/CMakeLists.txt b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/CMakeLists.txt index 663c9e76214..54747409590 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/CMakeLists.txt +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/CMakeLists.txt @@ -5,11 +5,13 @@ set(srcs "src/common/test_intr_utils.c" "src/common/test_panic_handler.c") if(CONFIG_SOC_SUPPORT_TEE_SYS_APM_TEST) + list(APPEND srcs "src/common/test_apm_utils.c" + "src/common/test_setup_utils.c" + "src/pms/test_tee_vectors.S") if(CONFIG_SOC_APM_CTRL_FILTER_SUPPORTED) - list(APPEND srcs "src/common/test_apm_utils.c" - "src/common/test_setup_utils.c" - "src/pms/test_tee_sys_apm.c" - "src/pms/test_tee_vectors.S") + list(APPEND srcs "src/pms/test_tee_sys_apm.c") + else() + list(APPEND srcs "src/pms/test_tee_pms.c") endif() endif() @@ -27,7 +29,7 @@ idf_component_register(SRCS "${srcs}" INCLUDE_DIRS "include" "priv_include" PRIV_INCLUDE_DIRS "priv_include/${target}" REQUIRES ulp unity esp_hal_security - PRIV_REQUIRES esp_hal_timg + PRIV_REQUIRES esp_hal_timg esp_mm LDFRAGMENTS linker.lf) if(CONFIG_ULP_COPROC_ENABLED) diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/include/test_pms.h b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/include/test_pms.h index 3eef2c8a6d4..113614b3891 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/include/test_pms.h +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/include/test_pms.h @@ -1,10 +1,13 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include "soc/soc_caps.h" + /* Test-cases */ +#if SOC_APM_CTRL_FILTER_SUPPORTED void test_sys_apm_master_hp_cpu_slave_hp_peri(void); void test_sys_apm_master_hp_cpu_slave_cpu_peri(void); @@ -34,3 +37,20 @@ void test_peri_apm_master_lp_cpu_slave_hp_peri(void); void test_peri_apm_master_lp_cpu_slave_lp_peri(void); void test_tee_mode_default_access(void); +#else +void test_sys_pms_master_hp_cpu_slave_hp_peri(void); + +void test_sys_pms_master_hp_cpu_slave_lp_peri(void); + +void test_sys_pms_master_hp_cpu_peri_regn_access(void); + +void test_sys_pms_master_lp_cpu_slave_hp_peri(void); + +void test_sys_pms_master_lp_cpu_slave_lp_peri(void); + +void test_sys_pms_master_lp_cpu_peri_regn_access(void); + +void test_sys_pms_master_gdma_slave_hp_mem(void); + +void test_sys_pms_master_gdma_slave_ext_mem(void); +#endif diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c5/test_pms_params.h b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c5/test_pms_params.h index b8ff56f4f9f..46edb21c5ec 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c5/test_pms_params.h +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c5/test_pms_params.h @@ -23,7 +23,7 @@ #define SOC_APM_CTRL_TEE_MODE_ACCESS_BUG 0 /********* GDMA APM master ID *********/ -#define TEST_GDMA_APM_MASTER_ID 26 /* GDMA_DUMMY10 */ +#define TEST_GDMA_APM_MASTER_ID 27 /* GDMA_DUMMY11 */ /********* APM controller and path definitions *********/ #define HP_CPU_CPUPERI_APM_CTRL APM_CTRL_HP_APM @@ -202,8 +202,6 @@ /********* For PERI_APM *********/ #include "soc/reg_base.h" - -/********* For PERI_APM *********/ #include "soc/uart_reg.h" #include "soc/i2c_reg.h" #include "soc/i2s_reg.h" diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c6/test_pms_params.h b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c6/test_pms_params.h index e3a0f9478c7..e975e389af7 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c6/test_pms_params.h +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c6/test_pms_params.h @@ -21,7 +21,7 @@ #define SOC_APM_CTRL_TEE_MODE_ACCESS_BUG 1 /********* GDMA APM master ID *********/ -#define TEST_GDMA_APM_MASTER_ID APM_MASTER_GDMA_GPSPI +#define TEST_GDMA_APM_MASTER_ID 27 /* GDMA_DUMMY11 */ /********* APM controller and path definitions *********/ #define HP_CPU_CPUPERI_APM_CTRL APM_CTRL_HP_APM diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c61/test_pms_params.h b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c61/test_pms_params.h index e313af9cf35..65ecc7b239c 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c61/test_pms_params.h +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32c61/test_pms_params.h @@ -23,7 +23,7 @@ #define SOC_APM_CTRL_TEE_MODE_ACCESS_BUG 0 /********* GDMA APM master ID *********/ -#define TEST_GDMA_APM_MASTER_ID 26 /* GDMA_DUMMY10 */ +#define TEST_GDMA_APM_MASTER_ID 27 /* GDMA_DUMMY11 */ /********* APM controller and path definitions *********/ #define HP_CPU_CPUPERI_APM_CTRL APM_CTRL_HP_APM diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32h2/test_pms_params.h b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32h2/test_pms_params.h index b22a7ce8c93..349dd905274 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32h2/test_pms_params.h +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32h2/test_pms_params.h @@ -21,7 +21,7 @@ #define SOC_APM_CTRL_TEE_MODE_ACCESS_BUG 1 /********* GDMA APM master ID *********/ -#define TEST_GDMA_APM_MASTER_ID APM_MASTER_GDMA_GPSPI +#define TEST_GDMA_APM_MASTER_ID 27 /* GDMA_DUMMY11 */ /********* APM controller and path definitions *********/ #define HP_CPU_CPUPERI_APM_CTRL APM_CTRL_HP_APM diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32p4/test_pms_params.h b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32p4/test_pms_params.h new file mode 100644 index 00000000000..8c539bd4eba --- /dev/null +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/esp32p4/test_pms_params.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "hal/apm_types.h" +#include "soc/apm_defs.h" + +#define ALIGN_TO_NEXT_4KB(addr) (((addr) + 0x1000) & ~0xFFF) + +/********* For DMA_PMS *********/ + +#define GDMA_HPMEM_TEST_REGN_NUM APM_DMA_PMS_REGION_NUM +#define GDMA_HPMEM_TEST_REGN_SIZE APM_DMA_PMS_REGION_ADDR_ALIGN +/* Reserved regions for HPMEM test: [0] pre-buf, [1] post-buf */ +#define GDMA_HPMEM_TEST_REGN_RESV_NUM 2 + +#define GDMA_EXTMEM_TEST_REGN_NUM APM_DMA_PMS_REGION_NUM +#define GDMA_EXTMEM_TEST_REGN_SIZE APM_DMA_PMS_REGION_ADDR_ALIGN +/* Reserved regions for EXTMEM test: [0] pre-buf, [1] post-buf, [2] full HP-mem + * TODO: Investigate why [2] is required for EXT_MEM case + */ +#define GDMA_EXTMEM_TEST_REGN_RESV_NUM 3 + +/********* For HP_PERI_PMS *********/ + +#include "soc/timer_group_reg.h" +#include "soc/i2c_reg.h" +#include "soc/i2s_reg.h" +#include "soc/pcnt_reg.h" +#include "soc/uart_reg.h" +#include "soc/spi_reg.h" +#include "soc/ledc_reg.h" +#include "soc/adc_reg.h" +#include "soc/parl_io_reg.h" +#include "soc/rmt_reg.h" +#include "soc/gpio_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/cache_reg.h" +#include "soc/hp_system_reg.h" +#include "soc/bitscrambler_reg.h" +#include "soc/trace_reg.h" +#include "soc/sha_reg.h" +#include "soc/assist_debug_reg.h" +#include "soc/parl_io_reg.h" +#include "soc/io_mux_reg.h" + +/********* For HP2LP_PERI_PMS *********/ + +#include "soc/lp_timer_reg.h" +#include "soc/lp_analog_peri_reg.h" +#include "soc/pmu_reg.h" +#include "soc/lp_wdt_reg.h" +#include "soc/lp_uart_reg.h" +#include "soc/lp_i2c_reg.h" +#include "soc/lp_i2c_ana_mst_reg.h" +#include "soc/huk_reg.h" +#include "soc/efuse_reg.h" +#include "soc/lp_iomux_reg.h" +#include "soc/trng_reg.h" diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/test_pms_priv.h b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/test_pms_priv.h index a11275e29af..6b1c1d705f6 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/test_pms_priv.h +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/priv_include/test_pms_priv.h @@ -18,6 +18,7 @@ #include "soc/lp_system_reg.h" #define LP_STORE_REG_PREFIX(reg) LP_SYSTEM_REG_LP_STORE##reg##_REG #endif + #include "hal/apm_types.h" /********* Panic Handler *********/ @@ -35,8 +36,8 @@ #define SEND_ADDR(addr) REG_WRITE(LP_STORE_REG_PREFIX(7), addr) #define RECV_ADDR() REG_READ(LP_STORE_REG_PREFIX(7)) -#define SEND_SIZE(size) REG_WRITE(LP_STORE_REG_PREFIX(8), size) -#define RECV_SIZE() REG_READ(LP_STORE_REG_PREFIX(8)) +#define SEND_DATA(data) REG_WRITE(LP_STORE_REG_PREFIX(8), data) +#define RECV_DATA() REG_READ(LP_STORE_REG_PREFIX(8)) #define SEND_EXCP(val) REG_WRITE(LP_STORE_REG_PREFIX(9), val) #define RECV_EXCP() REG_READ(LP_STORE_REG_PREFIX(9)) @@ -57,35 +58,12 @@ #endif #if SOC_APM_CTRL_FILTER_SUPPORTED -typedef struct { - apm_master_id_t master_id; - apm_ctrl_module_t ctrl_mod; - const uint32_t *test_addr; - uint32_t test_addr_num; - uint32_t test_addr_resv_mask; -} test_sys_apm_periph_cfg_t; - -typedef struct { - apm_master_id_t master_id; - apm_ctrl_module_t ctrl_mod; - apm_ctrl_access_path_t path; - uint32_t mem_start_addr; - uint32_t mem_end_addr; - uint32_t regn_count; - uint32_t regn_sz; -} test_sys_apm_mem_cfg_t; - -typedef struct { - apm_master_id_t master_id; - apm_tee_ctrl_module_t ctrl_mod; - const uint32_t *test_reg; - uint32_t test_reg_num; - uint64_t test_reg_resv_mask; -} test_peri_apm_periph_cfg_t; - void apm_hal_enable_region_filter_all(apm_ctrl_module_t ctrl_mod, bool enable); void test_apm_ctrl_reset_all(void); void test_apm_ctrl_enable_intr(apm_ctrl_module_t ctrl_mod, apm_ctrl_access_path_t path); +#else +void test_pms_ctrl_reset_all(void); +void test_pms_enable_intr(apm_ctrl_module_t ctrl_mod); #endif /* Utility functions */ @@ -97,7 +75,9 @@ void test_u2m_switch(void); void test_boot_lp_cpu(void); void test_stop_lp_cpu(void); void test_reset_lp_cpu(void); +#if SOC_LP_AON_SUPPORTED void test_switch_lp_mem_speed(bool high_speed); +#endif void test_gdma_init(void); void test_gdma_deinit(void); diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_apm_utils.c b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_apm_utils.c index 5ea7373eb0e..404be071c1f 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_apm_utils.c +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_apm_utils.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,11 @@ #include "soc/soc.h" #include "soc/soc_caps.h" #include "soc/interrupts.h" +#if SOC_CPU_CORES_NUM > 1 +#include "soc/interrupt_core0_reg.h" +#else +#include "soc/interrupt_matrix_reg.h" +#endif #include "soc/apm_defs.h" #include "hal/apm_hal.h" @@ -22,6 +27,7 @@ #include "unity.h" +#if SOC_APM_CTRL_FILTER_SUPPORTED /***************************** Utility - APM interrupts *****************************/ #define MAX_APM_CTRL_NUM (4) @@ -213,7 +219,7 @@ static const char *const excp_mid_strs[] = { #if SOC_PARLIO_SUPPORTED [APM_MASTER_GDMA_PARLIO] = "GDMA_PARLIO", #endif /* SOC_PARLIO_SUPPORTED */ - [26] = "GDMA_DUMMYX", + [27] = "GDMA_DUMMYX", }; static const char *apm_excp_mid_to_str(uint8_t mid) @@ -368,3 +374,232 @@ static void test_apm_ctrl_free_all_intr(void) } } } +#elif SOC_APM_SUPPORTED +/***************************** Utility - PMS interrupts *****************************/ + +#include "soc/icm_sys_reg.h" +#include "hal/lp_sys_ll.h" +#include "test_pms_params.h" + +static intr_handle_t s_pms_hp_intr_hdl = NULL; +static intr_handle_t s_pms_lp_intr_hdl = NULL; + +volatile bool pms_lp_excp_flag = false; +volatile uint32_t pms_lp_excp_addr = 0; +volatile bool pms_dma_excp_flag = false; + +/***************************** PMS exception check *****************************/ + +static const char *apm_excp_type_to_str(bool is_secure) +{ + char *excp_type = "Unknown"; + + if (is_secure) { + excp_type = "Space exception"; + } else { + excp_type = "Authority exception"; + } + + return excp_type; +} + +static const char *apm_excp_src_to_str(apm_ctrl_exception_type type) +{ + char *excp_src = "Unknown"; + + switch (type) { + case APM_EXCP_HP_AXI: + excp_src = "HP_AXI"; + break; + case APM_EXCP_HP_AHB: + excp_src = "HP_AHB"; + break; + case APM_EXCP_LP_AHB: + excp_src = "LP_AHB"; + break; + case APM_EXCP_LP_IDBUS: + excp_src = "LP_IDBUS"; + break; + default: + break; + } + + return excp_src; +} + +IRAM_ATTR static void pms_log_violation(apm_ctrl_exception_type type, apm_ctrl_exception_info_t *info) +{ + apm_hal_get_exception_info(type, info); + esp_rom_printf("PMS violation: %s\n\r", apm_excp_type_to_str(info->is_secure)); + esp_rom_printf("Access addr: 0x%08x | Type: %s\n\r", info->addr, info->is_wr ? "Write" : "Read"); + esp_rom_printf("Master: %d | Source: %s\n\r", info->id, apm_excp_src_to_str(type)); +} + +IRAM_ATTR static void pms_hp_intr_cb(void *arg) +{ + apm_ctrl_exception_info_t info; + uint32_t status = apm_hal_get_intr_status(); + + if (status & APM_EXCP_HP_AXI) { + pms_log_violation(APM_EXCP_HP_AXI, &info); + } + if (status & APM_EXCP_HP_AHB) { + pms_log_violation(APM_EXCP_HP_AHB, &info); + pms_dma_excp_flag = true; + } + + apm_hal_clear_intr(APM_CTRL_DMA_PMS); + apm_hal_clear_intr(APM_CTRL_HP_PERI_PMS); + apm_hal_clear_intr(APM_CTRL_LP2HP_PERI_PMS); +} + +IRAM_ATTR static void pms_lp_intr_cb(void *arg) +{ + apm_ctrl_exception_info_t info; + uint32_t status = apm_hal_get_intr_status(); + + if (status & APM_EXCP_LP_AHB) { + pms_log_violation(APM_EXCP_LP_AHB, &info); + pms_lp_excp_addr = info.addr; + pms_lp_excp_flag = true; + } + if (status & APM_EXCP_LP_IDBUS) { + pms_log_violation(APM_EXCP_LP_IDBUS, &info); + pms_lp_excp_addr = info.addr; + pms_lp_excp_flag = true; + } + + apm_hal_clear_intr(APM_CTRL_HP2LP_PERI_PMS); + apm_hal_clear_intr(APM_CTRL_LP_PERI_PMS); +} + +void test_pms_enable_intr(apm_ctrl_module_t ctrl_mod) +{ + /* TODO: Investigate why this is required */ + REG_CLR_BIT(ICM_INT_ENA_REG, ICM_REG_DLOCK_INT_ENA); + + int intr_src = apm_hal_get_intr_src_num(ctrl_mod); + TEST_ASSERT(intr_src >= 0); + + uint32_t flags = ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LEVEL3; + + switch (ctrl_mod) { + case APM_CTRL_DMA_PMS: + case APM_CTRL_HP_PERI_PMS: + case APM_CTRL_LP2HP_PERI_PMS: + if (!s_pms_hp_intr_hdl) { + TEST_ESP_OK(esp_intr_alloc(intr_src, flags, &pms_hp_intr_cb, NULL, &s_pms_hp_intr_hdl)); + } + break; + case APM_CTRL_LP_PERI_PMS: + case APM_CTRL_HP2LP_PERI_PMS: + if (!s_pms_lp_intr_hdl) { + TEST_ESP_OK(esp_intr_alloc(intr_src, flags, &pms_lp_intr_cb, NULL, &s_pms_lp_intr_hdl)); + } + break; + default: + TEST_ASSERT_MESSAGE(false, "Invalid PMS module"); + return; + } + + apm_hal_enable_intr(ctrl_mod, true); +} + +static void test_pms_free_all_intr(void) +{ + if (s_pms_hp_intr_hdl) { + esp_intr_free(s_pms_hp_intr_hdl); + s_pms_hp_intr_hdl = NULL; + } + if (s_pms_lp_intr_hdl) { + esp_intr_free(s_pms_lp_intr_hdl); + s_pms_lp_intr_hdl = NULL; + } +} + +/********************************** PMS Reset *************************************/ + +static void test_dma_pms_reset(void) +{ + for (uint32_t regn = 0; regn < APM_DMA_PMS_REGION_NUM; regn++) { + apm_hal_dma_pms_set_region_bounds(regn, 0x00U, UINT32_MAX); + } + + for (uint32_t mid = 0; mid < APM_MASTER_DMA_MAX; mid++) { + apm_hal_dma_pms_set_master_region_attr((apm_master_dma_id_t)mid, UINT32_MAX, UINT32_MAX); + } + + apm_hal_enable_intr(APM_CTRL_DMA_PMS, false); + apm_hal_clear_intr(APM_CTRL_DMA_PMS); +} + +static void test_hp_peri_pms_reset(void) +{ + const apm_hal_pms_hp_peri_cfg_t cfg = { + .cpu_peri = UINT32_MAX, + .hp_peri0 = UINT32_MAX, + .hp_peri1 = UINT64_MAX, + }; + for (int core = 0; core < SOC_CPU_CORES_NUM; core++) { + apm_hal_hp_peri_pms_set_hpcpu_access(core, APM_SEC_MODE_TEE, &cfg); + apm_hal_hp_peri_pms_set_hpcpu_access(core, APM_SEC_MODE_REE, &cfg); + } + + apm_hal_enable_intr(APM_CTRL_HP_PERI_PMS, false); + apm_hal_clear_intr(APM_CTRL_HP_PERI_PMS); +} + +static void test_hp2lp_peri_pms_reset(void) +{ + uint32_t cfg_mask = UINT32_MAX; + for (int core = 0; core < SOC_CPU_CORES_NUM; core++) { + apm_hal_hp2lp_peri_pms_set_hpcpu_access(core, APM_SEC_MODE_TEE, cfg_mask); + apm_hal_hp2lp_peri_pms_set_hpcpu_access(core, APM_SEC_MODE_REE, cfg_mask); + } + + apm_hal_enable_intr(APM_CTRL_HP2LP_PERI_PMS, false); + apm_hal_clear_intr(APM_CTRL_HP2LP_PERI_PMS); +} + +static void test_lp_peri_pms_reset(void) +{ + uint32_t cfg_mask = UINT32_MAX; + apm_hal_lp_peri_pms_set_lpcpu_access(cfg_mask); + + for (uint32_t regn = 0; regn < APM_LP_PERI_PMS_REGION_NUM; regn++) { + apm_hal_lp_peri_pms_set_region_bounds(regn, 0x00U, UINT32_MAX); + } + + for (uint32_t mid = 0; mid < APM_MASTER_DMA; mid++) { + apm_hal_lp_peri_pms_set_master_region_attr(mid, APM_SEC_MODE_TEE, UINT32_MAX); + apm_hal_lp_peri_pms_set_master_region_attr(mid, APM_SEC_MODE_REE, UINT32_MAX); + } + + apm_hal_enable_intr(APM_CTRL_LP_PERI_PMS, false); + apm_hal_clear_intr(APM_CTRL_LP_PERI_PMS); +} + +static void test_lp2hp_peri_pms_reset(void) +{ + const apm_hal_pms_hp_peri_cfg_t cfg = { + .cpu_peri = UINT32_MAX, + .hp_peri0 = UINT32_MAX, + .hp_peri1 = UINT64_MAX, + }; + apm_hal_lp2hp_peri_pms_set_lpcpu_access(&cfg); + + apm_hal_enable_intr(APM_CTRL_LP2HP_PERI_PMS, false); + apm_hal_clear_intr(APM_CTRL_LP2HP_PERI_PMS); + lp_sys_ll_enable_lp_core_err_resp(true); +} + +void test_pms_ctrl_reset_all(void) +{ + test_dma_pms_reset(); + test_hp_peri_pms_reset(); + test_hp2lp_peri_pms_reset(); + test_lp_peri_pms_reset(); + test_lp2hp_peri_pms_reset(); + test_pms_free_all_intr(); +} +#endif diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_panic_handler.c b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_panic_handler.c index 7709e4a7e33..f93ac02d9fe 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_panic_handler.c +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_panic_handler.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -61,11 +61,18 @@ void test_panicHandler(RvExcFrame *frame, int exccause) } return; } + /* PERI_APM access fault */ -#if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL +#if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL || !SOC_APM_CTRL_FILTER_SUPPORTED +#if CONFIG_IDF_TARGET_ESP32P4 + if ((regs->mtval >= CPU_PERIPH_LOW && regs->mtval < CPU_PERIPH_HIGH) || + (regs->mtval >= SOC_PERIPHERAL_LOW && regs->mtval < SOC_PERIPHERAL_HIGH) || + (regs->mtval >= SOC_LP_PERIPH_LOW && regs->mtval < SOC_LP_PERIPH_HIGH)) { +#else if (regs->mtval >= SOC_PERIPHERAL_LOW && regs->mtval < SOC_PERIPHERAL_HIGH) { +#endif if (mcause == MCAUSE_LOAD_ACCESS_FAULT || mcause == MCAUSE_STORE_ACCESS_FAULT) { - panic_print("[PERI_APM] %s at 0x%08x\n\r", rsn, regs->mtval); + panic_print("[PERI_ACC] %s at 0x%08x (%s)\n\r", rsn, regs->mtval, (regs->mstatus & MSTATUS_MPP) ? "M-mode" : "U-mode"); frame->mepc += 0x04U; RV_WRITE_CSR(uscratch, regs->mtval); return; diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_setup_utils.c b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_setup_utils.c index 84567627489..18e687b5099 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_setup_utils.c +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/common/test_setup_utils.c @@ -13,18 +13,27 @@ #include "hal/gdma_ll.h" #include "hal/gdma_types.h" #if SOC_AHB_GDMA_VERSION == 2 +#include "hal/ahb_dma_ll.h" #include "soc/ahb_dma_struct.h" #elif SOC_AHB_GDMA_VERSION == 1 #include "soc/gdma_struct.h" #endif +#include "esp_private/periph_ctrl.h" #if CONFIG_ULP_COPROC_ENABLED -#include "soc/lp_aon_reg.h" #include "soc/lpperi_reg.h" +#if SOC_LP_AON_SUPPORTED +#include "soc/lp_aon_reg.h" +#define LP_CPU_RST_EN (LPPERI_LP_CPU_RESET_EN) +#else +#include "soc/lp_system_reg.h" +#define LP_CPU_RST_EN (LPPERI_RST_EN_LP_CORE) +#endif #include "ulp_lp_core.h" #endif #include "esp_attr.h" +#include "esp_cache.h" #include "esp_rom_lldesc.h" #include "esp_rom_sys.h" @@ -61,9 +70,11 @@ void test_stop_lp_cpu(void) void test_reset_lp_cpu(void) { - REG_SET_BIT(LPPERI_RESET_EN_REG, LPPERI_LP_CPU_RESET_EN); + REG_SET_BIT(LPPERI_RESET_EN_REG, LP_CPU_RST_EN); + REG_CLR_BIT(LPPERI_RESET_EN_REG, LP_CPU_RST_EN); } +#if SOC_LP_AON_SUPPORTED void test_switch_lp_mem_speed(bool high_speed) { if (high_speed) { @@ -74,6 +85,7 @@ void test_switch_lp_mem_speed(bool high_speed) REG_SET_BIT(LP_AON_LPBUS_REG, LP_AON_FAST_MEM_MUX_SEL_UPDATE); } #endif +#endif /***************************** Utility - GDMA *****************************/ @@ -87,15 +99,21 @@ void test_switch_lp_mem_speed(bool high_speed) #define DMA_MEM_TRANS_EN_FIELD mem_trans_en #endif +#if SOC_RCC_IS_INDEPENDENT +#define GDMA_RCC_ATOMIC() +#else /* !SOC_RCC_IS_INDEPENDENT */ +#define GDMA_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#endif /* SOC_RCC_IS_INDEPENDENT */ + #define dma_ll_force_enable_reg_clock DMA_LL_FUNC(force_enable_reg_clock) #define dma_ll_tx_enable_data_burst DMA_LL_FUNC(tx_enable_data_burst) #define dma_ll_tx_enable_descriptor_burst DMA_LL_FUNC(tx_enable_descriptor_burst) #define dma_ll_rx_enable_data_burst DMA_LL_FUNC(rx_enable_data_burst) #define dma_ll_rx_enable_descriptor_burst DMA_LL_FUNC(rx_enable_descriptor_burst) #define dma_ll_tx_reset_channel DMA_LL_FUNC(tx_reset_channel) -#define dma_ll_tx_connect_to_periph DMA_LL_FUNC(tx_connect_to_periph) +#define dma_ll_tx_connect_to_mem DMA_LL_FUNC(tx_connect_to_mem) #define dma_ll_rx_reset_channel DMA_LL_FUNC(rx_reset_channel) -#define dma_ll_rx_connect_to_periph DMA_LL_FUNC(rx_connect_to_periph) +#define dma_ll_rx_connect_to_mem DMA_LL_FUNC(rx_connect_to_mem) #define dma_ll_tx_disconnect_all DMA_LL_FUNC(tx_disconnect_all) #define dma_ll_rx_disconnect_all DMA_LL_FUNC(rx_disconnect_all) #define dma_ll_tx_set_desc_addr DMA_LL_FUNC(tx_set_desc_addr) @@ -113,10 +131,13 @@ void test_switch_lp_mem_speed(bool high_speed) #define dma_ll_tx_get_interrupt_status DMA_LL_FUNC(tx_get_interrupt_status) #define dma_ll_rx_get_interrupt_status DMA_LL_FUNC(rx_get_interrupt_status) -#define TEST_DMA_CHN_NUM 0 +#define TEST_DMA_GRP_NUM 0 +#define TEST_DMA_CHN_NUM 1 #define TEST_DMA_BLK_LEN 1024 #define TEST_DMA_MAX_BLK_NUM 32 +#define SOC_GDMA_TRIG_PERIPH_DUMMY (11) + DRAM_ATTR static lldesc_t tx_link[TEST_DMA_MAX_BLK_NUM]; DRAM_ATTR static lldesc_t rx_link[TEST_DMA_MAX_BLK_NUM]; @@ -146,6 +167,11 @@ static void setup_gdma_link(lldesc_t *link, uint8_t *buf, size_t size, bool is_t link[x - 1].empty = 0; } +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + size_t num_desc = (size + TEST_DMA_BLK_LEN - 1) / TEST_DMA_BLK_LEN; + esp_cache_msync(&link[0], num_desc * sizeof(lldesc_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); +#endif + if (is_tx) { dma_ll_tx_set_desc_addr(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, (uint32_t)&link[0]); } else { @@ -155,8 +181,10 @@ static void setup_gdma_link(lldesc_t *link, uint8_t *buf, size_t size, bool is_t void test_gdma_init(void) { - gdma_ll_enable_bus_clock(TEST_DMA_CHN_NUM, true); - gdma_ll_reset_register(TEST_DMA_CHN_NUM); + GDMA_RCC_ATOMIC() { + gdma_ll_enable_bus_clock(TEST_DMA_GRP_NUM, true); + gdma_ll_reset_register(TEST_DMA_GRP_NUM); + } dma_ll_force_enable_reg_clock(&TEST_DMA_DEV, true); #if SOC_AHB_GDMA_VERSION == 2 @@ -181,9 +209,8 @@ void test_gdma_init(void) dma_ll_tx_set_priority(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, 1); dma_ll_rx_set_priority(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, 1); - dma_ll_tx_connect_to_periph(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, SOC_GDMA_TRIG_PERIPH_SPI2); - dma_ll_rx_connect_to_periph(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, SOC_GDMA_TRIG_PERIPH_SPI2); - TEST_DMA_DEV.channel[TEST_DMA_CHN_NUM].in.in_conf0.DMA_MEM_TRANS_EN_FIELD = 1; + dma_ll_tx_connect_to_mem(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, SOC_GDMA_TRIG_PERIPH_DUMMY); + dma_ll_rx_connect_to_mem(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, SOC_GDMA_TRIG_PERIPH_DUMMY); dma_ll_tx_enable_interrupt(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, GDMA_LL_EVENT_TX_EOF, true); dma_ll_rx_enable_interrupt(&TEST_DMA_DEV, TEST_DMA_CHN_NUM, GDMA_LL_EVENT_RX_SUC_EOF, true); @@ -200,8 +227,10 @@ void test_gdma_deinit(void) dma_ll_tx_reset_channel(&TEST_DMA_DEV, TEST_DMA_CHN_NUM); dma_ll_rx_reset_channel(&TEST_DMA_DEV, TEST_DMA_CHN_NUM); - gdma_ll_reset_register(TEST_DMA_CHN_NUM); - gdma_ll_enable_bus_clock(TEST_DMA_CHN_NUM, false); + GDMA_RCC_ATOMIC() { + gdma_ll_reset_register(TEST_DMA_GRP_NUM); + gdma_ll_enable_bus_clock(TEST_DMA_GRP_NUM, false); + } } void test_gdma_m2m_transfer(uint8_t *src, uint8_t *dest, size_t size) diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_peri_apm.c b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_peri_apm.c index 4768ec17000..bee5f6e4afc 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_peri_apm.c +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_peri_apm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,6 +27,14 @@ /***************************** PERI_APM *****************************/ +typedef struct { + apm_master_id_t master_id; + apm_tee_ctrl_module_t ctrl_mod; + const uint32_t *test_reg; + uint32_t test_reg_num; + uint64_t test_reg_resv_mask; +} test_peri_apm_periph_cfg_t; + static const uint32_t test_peri_apm_hp_peri_reg[] = { [APM_TEE_HP_PERIPH_UART1] = UART_DATE_REG(1), [APM_TEE_HP_PERIPH_I2C_EXT0] = I2C_DATE_REG(0), @@ -130,30 +138,35 @@ IRAM_ATTR static void hp_cpu_peri_addr_rw(uint32_t peri_addr, uint32_t attr) IRAM_ATTR static void lp_cpu_peri_addr_rw(uint32_t peri_addr, uint32_t attr) { - test_reset_lp_cpu(); + SEND_MSG(MSG_SLAVE_CLEAR); + test_delay_ms(5); SEND_EXCP(0); - SEND_MSG(MSG_SLAVE_WRITE); SEND_ADDR(peri_addr); + SEND_DATA(TEST_VAL); + SEND_MSG(MSG_SLAVE_WRITE); test_delay_ms(10); bool can_write = (attr & APM_PERM_W); if (!can_write) { TEST_ASSERT(RECV_EXCP() == MCAUSE_STORE_ACCESS_FAULT); TEST_ASSERT_EQUAL_HEX32(peri_addr, RECV_ADDR()); - esp_rom_printf("[PERI_APM] Store access fault at 0x%08x\n", peri_addr); + esp_rom_printf("[PERI_ACC] Store access fault at 0x%08x\n", peri_addr); } + SEND_MSG(MSG_SLAVE_CLEAR); + test_delay_ms(5); + SEND_EXCP(0); - SEND_MSG(MSG_SLAVE_READ); SEND_ADDR(peri_addr); + SEND_MSG(MSG_SLAVE_READ); test_delay_ms(10); bool can_read = (attr & APM_PERM_R); if (!can_read) { TEST_ASSERT(RECV_EXCP() == MCAUSE_LOAD_ACCESS_FAULT); TEST_ASSERT_EQUAL_HEX32(peri_addr, RECV_ADDR()); - esp_rom_printf("[PERI_APM] Load access fault at 0x%08x\n", peri_addr); + esp_rom_printf("[PERI_ACC] Load access fault at 0x%08x\n", peri_addr); } SEND_EXCP(0); diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_pms.c b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_pms.c new file mode 100644 index 00000000000..411ac2d0ba8 --- /dev/null +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_pms.c @@ -0,0 +1,740 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "soc/soc.h" +#include "soc/soc_caps.h" +#include "soc/apm_defs.h" + +#include "hal/apm_hal.h" +#include "hal/apm_ll.h" +#include "hal/apm_types.h" + +#include "esp_attr.h" +#include "esp_cpu.h" +#include "esp_rom_sys.h" + +#include "riscv/csr.h" +#include "riscv/rv_utils.h" + +#include "test_pms_priv.h" +#include "test_pms_params.h" + +#include "esp_cache.h" +#include "esp_heap_caps.h" +#include "esp_memory_utils.h" + +#include "unity.h" + +#define TEST_VAL 0x0FACADE0 + +extern volatile bool pms_lp_excp_flag; +extern volatile uint32_t pms_lp_excp_addr; +extern volatile bool pms_dma_excp_flag; + +/***************************** HP/HP2LP PERI_PMS & LP/LP2HP PERI_PMS *****************************/ + +typedef enum { + HP_PERI0, + HP_PERI1, + CPU_PERI, + LP_PERI +} test_pms_peri_grp_t; + +typedef struct { + apm_master_id_t master_id; + apm_ctrl_module_t ctrl_mod; + const uint32_t *test_reg; + uint32_t test_reg_num; + test_pms_peri_grp_t test_peri_grp; +} test_pms_periph_cfg_t; + +static const uint32_t test_cpu_peri_reg[] = { + [APM_SLAVE_TRACE0] = TRACE_DATE_REG(0), + [APM_SLAVE_TRACE1] = TRACE_DATE_REG(1), + [APM_SLAVE_CACHE] = CACHE_DATE_REG, +}; + +static const uint32_t test_hp_peri0_reg[] = { + [APM_SLAVE_HP_CRYPTO] = SHA_DATE_REG, + [APM_SLAVE_HP_RMT] = RMT_DATE_REG, + [APM_SLAVE_HP_BITSCRAMBLER] = BITSCRAMBLER_VERSION_REG, +}; + +static const uint32_t test_hp_peri1_reg[] = { + [APM_SLAVE_HP_TG0] = TIMG_NTIMERS_DATE_REG(0), + [APM_SLAVE_HP_I2C0] = I2C_DATE_REG(0), + [APM_SLAVE_HP_I2S0] = I2S_DATE_REG(0), + [APM_SLAVE_HP_PCNT] = PCNT_DATE_REG, + [APM_SLAVE_HP_UART2] = UART_DATE_REG(2), + [APM_SLAVE_HP_PARLIO] = PARL_IO_VERSION_REG, + [APM_SLAVE_HP_GPSPI2] = SPI_DATE_REG(2), + [APM_SLAVE_HP_LEDC] = LEDC_DATE_REG, + [APM_SLAVE_HP_ADC] = ADC_CTRL_DATE_REG, + [APM_SLAVE_HP_GPIO] = GPIO_DATE_REG, + [APM_SLAVE_HP_IOMUX] = IO_MUX_DATE_REG, + [APM_SLAVE_HP_SYS_REG] = HP_SYSTEM_VER_DATE_REG, +}; + +static const uint32_t test_lp_peri_reg[] = { + [APM_SLAVE_LP_TIMER] = LP_TIMER_DATE_REG, + [APM_SLAVE_LP_ANAPERI] = LP_ANALOG_PERI_DATE_REG, + [APM_SLAVE_LP_WDT] = LP_WDT_DATE_REG, + [APM_SLAVE_LP_UART] = LP_UART_ID_REG, + [APM_SLAVE_LP_I2C] = LP_I2C_DATE_REG, + [APM_SLAVE_LP_I2CMST] = LP_I2C_ANA_MST_DATE_REG, + [APM_SLAVE_LP_IOMUX] = LP_IOMUX_VER_DATE_REG, + [APM_SLAVE_LP_HUK] = HUK_DATE_REG, + [APM_SLAVE_LP_TRNG] = RNG_DATE_REG, +}; + +FORCE_INLINE_ATTR uint32_t reg_read(uint32_t addr) +{ + uint32_t value; + __asm__ volatile( + "lw %0, 0(%1)\n" + "fence\n" + "nop\nnop\nnop\nnop\n" + : "=r"(value) + : "r"(addr) + : "memory" + ); + return value; +} + +FORCE_INLINE_ATTR void reg_write(uint32_t addr, uint32_t value) +{ + __asm__ volatile( + "sw %1, 0(%0)\n" + "fence\n" + "nop\nnop\nnop\nnop\n" + : + : "r"(addr), "r"(value) + : "memory" + ); +} + +IRAM_ATTR static void hp_cpu_peri_addr_rw(uint32_t peri_addr, bool should_panic) +{ + RV_WRITE_CSR(uscratch, 0x00); + + reg_write(peri_addr, TEST_VAL); + test_delay_ms(10); + + if (should_panic) { + TEST_ASSERT_EQUAL_HEX32(peri_addr, RV_READ_CSR(uscratch)); + } else { + TEST_ASSERT_EQUAL_HEX32(0x00, RV_READ_CSR(uscratch)); + } + + RV_WRITE_CSR(uscratch, 0x00); + + volatile uint32_t val = reg_read(peri_addr); + (void)val; + test_delay_ms(10); + + if (should_panic) { + TEST_ASSERT_EQUAL_HEX32(peri_addr, RV_READ_CSR(uscratch)); + } else { + TEST_ASSERT_EQUAL_HEX32(0x00, RV_READ_CSR(uscratch)); + } + + RV_WRITE_CSR(uscratch, 0x00); +} + +#if CONFIG_ULP_COPROC_ENABLED +IRAM_ATTR static void lp_cpu_peri_addr_rw(uint32_t peri_addr, bool should_panic) +{ + bool is_lp_peri = (peri_addr >= SOC_LP_PERIPH_LOW && peri_addr < SOC_LP_PERIPH_HIGH); + + SEND_MSG(MSG_SLAVE_CLEAR); + test_delay_ms(5); + + if (is_lp_peri) { + pms_lp_excp_flag = false; + pms_lp_excp_addr = UINT32_MAX; + } else { + SEND_EXCP(0); + } + SEND_ADDR(peri_addr); + SEND_DATA(TEST_VAL); + SEND_MSG(MSG_SLAVE_WRITE); + test_delay_ms(10); + + if (should_panic) { + if (is_lp_peri) { + TEST_ASSERT_TRUE(pms_lp_excp_flag); + TEST_ASSERT_EQUAL_HEX32(peri_addr, pms_lp_excp_addr); + } else { + TEST_ASSERT(RECV_EXCP() == MCAUSE_STORE_ACCESS_FAULT); + TEST_ASSERT_EQUAL_HEX32(peri_addr, RECV_ADDR()); + esp_rom_printf("[PERI_ACC] Store access fault at 0x%08x\n", peri_addr); + } + } else { + if (is_lp_peri) { + TEST_ASSERT_FALSE(pms_lp_excp_flag); + } else { + TEST_ASSERT(RECV_EXCP() == 0); + } + } + + SEND_MSG(MSG_SLAVE_CLEAR); + test_delay_ms(5); + + if (is_lp_peri) { + pms_lp_excp_flag = false; + pms_lp_excp_addr = UINT32_MAX; + } else { + SEND_EXCP(0); + } + SEND_ADDR(peri_addr); + SEND_MSG(MSG_SLAVE_READ); + test_delay_ms(10); + + if (should_panic) { + if (is_lp_peri) { + TEST_ASSERT_TRUE(pms_lp_excp_flag); + TEST_ASSERT_EQUAL_HEX32(peri_addr, pms_lp_excp_addr); + } else { + TEST_ASSERT(RECV_EXCP() == MCAUSE_LOAD_ACCESS_FAULT); + TEST_ASSERT_EQUAL_HEX32(peri_addr, RECV_ADDR()); + esp_rom_printf("[PERI_ACC] Load access fault at 0x%08x\n", peri_addr); + } + } else { + if (is_lp_peri) { + TEST_ASSERT_FALSE(pms_lp_excp_flag); + } else { + TEST_ASSERT(RECV_EXCP() == 0); + } + } +} +#endif + +IRAM_ATTR static void switch_priv_mode(void) +{ + int mode = esp_cpu_get_curr_privilege_level(); + if (mode == PRV_M) { + rv_utils_intr_global_disable(); + test_m2u_switch(); + } else { + test_u2m_switch(); + rv_utils_intr_global_enable(); + } +} + +static const apm_hal_pms_regn_cfg_t test_hp_peri_regn_cfg[] = { + /* cpu_peri */ + APM_HAL_PMS_REGION_ENTRY(0, REG_TRACE_BASE(0), REG_TRACE_BASE(1)), + APM_HAL_PMS_REGION_ENTRY(1, DR_REG_CACHE_BASE, ALIGN_TO_NEXT_4KB(DR_REG_CACHE_BASE)), + /* hp_peri */ + APM_HAL_PMS_REGION_ENTRY(2, DR_REG_SHA_BASE, DR_REG_RSA_BASE), + APM_HAL_PMS_REGION_ENTRY(3, DR_REG_RMT_BASE, DR_REG_BITSCRAMBLER_BASE), + APM_HAL_PMS_REGION_ENTRY(4, DR_REG_PCNT_BASE, DR_REG_UART0_BASE), + APM_HAL_PMS_REGION_ENTRY(5, DR_REG_PARIO_BASE, DR_REG_SPI2_BASE), + APM_HAL_PMS_REGION_ENTRY(6, DR_REG_GPIO_BASE, DR_REG_IO_MUX_BASE), + APM_HAL_PMS_REGION_ENTRY(7, DR_REG_IO_MUX_BASE, DR_REG_SYSTIMER_BASE), +}; + +static const uint32_t test_hp_peri_regn_addr[] = { + TRACE_DATE_REG(0), CACHE_DATE_REG, SHA_DATE_REG, RMT_DATE_REG, + PCNT_DATE_REG, PARL_IO_VERSION_REG, GPIO_DATE_REG, IO_MUX_DATE_REG, +}; + +static const apm_hal_pms_regn_cfg_t test_lp_peri_regn_cfg[] = { + /* lp_peri */ + APM_HAL_PMS_REGION_ENTRY(0, DR_REG_LP_TIMER_BASE, DR_REG_LP_ANALOG_PERI_BASE), + APM_HAL_PMS_REGION_ENTRY(1, DR_REG_LP_ANALOG_PERI_BASE, DR_REG_LP_HUK_BASE), + APM_HAL_PMS_REGION_ENTRY(2, DR_REG_LP_HUK_BASE, DR_REG_PMU_BASE), + APM_HAL_PMS_REGION_ENTRY(3, DR_REG_LP_WDT_BASE, DR_REG_LP_MB_BASE), + APM_HAL_PMS_REGION_ENTRY(4, DR_REG_LP_UART_BASE, DR_REG_LP_I2C_BASE), + APM_HAL_PMS_REGION_ENTRY(5, DR_REG_LP_I2C_BASE, DR_REG_LP_SPI_BASE), + APM_HAL_PMS_REGION_ENTRY(6, DR_REG_LP_I2C_ANA_MST_BASE, DR_REG_LP_I2S_BASE), + APM_HAL_PMS_REGION_ENTRY(7, DR_REG_LP_TRNG_BASE, DR_REG_LP_ADC_BASE), +}; + +static const uint32_t test_lp_peri_regn_addr[] = { + LP_TIMER_DATE_REG, LP_ANALOG_PERI_DATE_REG, HUK_DATE_REG, LP_WDT_DATE_REG, + LP_UART_ID_REG, LP_I2C_DATE_REG, LP_I2C_ANA_MST_DATE_REG, RNG_DATE_REG, +}; + +static void test_hp_cpu_to_peri_access(const test_pms_periph_cfg_t *cfg) +{ + apm_hal_pms_hp_peri_cfg_t hp_peri_cfg = { + .cpu_peri = UINT32_MAX, + .hp_peri0 = UINT32_MAX, + .hp_peri1 = UINT64_MAX, + }; + const uint32_t lp_peri_cfg = UINT32_MAX; + + for (uint32_t mode = APM_SEC_MODE_TEE; mode <= APM_SEC_MODE_REE; mode++) { + apm_hal_hp_peri_pms_set_hpcpu_access(0, (apm_security_mode_t)mode, &hp_peri_cfg); + apm_hal_hp2lp_peri_pms_set_hpcpu_access(0, (apm_security_mode_t)mode, lp_peri_cfg); + + for (uint32_t sid = 0; sid < cfg->test_reg_num; sid++) { + uint32_t peri_addr = cfg->test_reg[sid]; + if (peri_addr == 0) { + continue; + } + bool is_switch_req = (mode == APM_SEC_MODE_REE); + + if (is_switch_req) { + switch_priv_mode(); + } + hp_cpu_peri_addr_rw(peri_addr, false); + if (is_switch_req) { + switch_priv_mode(); + } + + switch (cfg->ctrl_mod) { + case APM_CTRL_HP_PERI_PMS: + switch (cfg->test_peri_grp) { + case HP_PERI0: + hp_peri_cfg.hp_peri0 &= ~BIT(sid); + break; + case HP_PERI1: + hp_peri_cfg.hp_peri1 &= ~BIT64(sid); + break; + case CPU_PERI: + hp_peri_cfg.cpu_peri &= ~BIT(sid); + break; + default: + TEST_ASSERT_MESSAGE(false, "Invalid group"); + return; + } + apm_hal_hp_peri_pms_set_hpcpu_access(0, (apm_security_mode_t)mode, &hp_peri_cfg); + break; + case APM_CTRL_HP2LP_PERI_PMS: + apm_hal_hp2lp_peri_pms_set_hpcpu_access(0, (apm_security_mode_t)mode, lp_peri_cfg & ~BIT(sid)); + break; + default: + break; + } + memset(&hp_peri_cfg, 0xFF, sizeof(hp_peri_cfg)); + + if (is_switch_req) { + switch_priv_mode(); + } + hp_cpu_peri_addr_rw(peri_addr, true); + if (is_switch_req) { + switch_priv_mode(); + } + } + } +} + +static void test_hp_cpu_to_peri_access_regn(const test_pms_periph_cfg_t *cfg) +{ + const apm_hal_pms_regn_cfg_t *regn_cfg; + if (cfg->test_peri_grp == LP_PERI) { + regn_cfg = test_lp_peri_regn_cfg; + } else { + regn_cfg = test_hp_peri_regn_cfg; + } + + apm_hal_lp_peri_pms_set_region_cfg(cfg->test_reg_num, regn_cfg); + + for (uint32_t mode = APM_SEC_MODE_TEE; mode <= APM_SEC_MODE_REE; mode++) { + bool is_switch_req = (mode == APM_SEC_MODE_REE); + for (uint32_t rid = 0; rid < cfg->test_reg_num; rid++) { + uint32_t peri_addr = cfg->test_reg[rid]; + + apm_hal_lp_peri_pms_set_master_region_attr(cfg->master_id, (apm_security_mode_t)mode, UINT32_MAX); + + if (is_switch_req) { + switch_priv_mode(); + } + hp_cpu_peri_addr_rw(peri_addr, false); + if (is_switch_req) { + switch_priv_mode(); + } + + apm_hal_lp_peri_pms_set_master_region_attr(cfg->master_id, (apm_security_mode_t)mode, UINT32_MAX & ~BIT(rid)); + + if (is_switch_req) { + switch_priv_mode(); + } + hp_cpu_peri_addr_rw(peri_addr, true); + if (is_switch_req) { + switch_priv_mode(); + } + } + } +} + +#if CONFIG_ULP_COPROC_ENABLED +static void test_lp_cpu_to_peri_access(const test_pms_periph_cfg_t *cfg) +{ + apm_hal_pms_hp_peri_cfg_t hp_peri_cfg = { + .cpu_peri = UINT32_MAX, + .hp_peri0 = UINT32_MAX, + .hp_peri1 = UINT64_MAX, + }; + const uint32_t lp_peri_cfg = UINT32_MAX; + + for (uint32_t sid = 0; sid < cfg->test_reg_num; sid++) { + uint32_t peri_addr = cfg->test_reg[sid]; + if (peri_addr == 0) { + continue; + } + + apm_hal_lp_peri_pms_set_lpcpu_access(lp_peri_cfg); + apm_hal_lp2hp_peri_pms_set_lpcpu_access(&hp_peri_cfg); + lp_cpu_peri_addr_rw(peri_addr, false); + + switch (cfg->ctrl_mod) { + case APM_CTRL_LP_PERI_PMS: + apm_hal_lp_peri_pms_set_lpcpu_access(lp_peri_cfg & ~BIT(sid)); + break; + case APM_CTRL_LP2HP_PERI_PMS: + switch (cfg->test_peri_grp) { + case HP_PERI0: + hp_peri_cfg.hp_peri0 &= ~BIT(sid); + break; + case HP_PERI1: + hp_peri_cfg.hp_peri1 &= ~BIT64(sid); + break; + case CPU_PERI: + hp_peri_cfg.cpu_peri &= ~BIT(sid); + break; + default: + TEST_ASSERT_MESSAGE(false, "Invalid group"); + return; + } + apm_hal_lp2hp_peri_pms_set_lpcpu_access(&hp_peri_cfg); + break; + default: + break; + } + memset(&hp_peri_cfg, 0xFF, sizeof(hp_peri_cfg)); + + lp_cpu_peri_addr_rw(peri_addr, true); + } +} + +static void test_lp_cpu_to_peri_access_regn(const test_pms_periph_cfg_t *cfg) +{ + const apm_hal_pms_regn_cfg_t *regn_cfg; + if (cfg->test_peri_grp == LP_PERI) { + regn_cfg = test_lp_peri_regn_cfg; + } else { + regn_cfg = test_hp_peri_regn_cfg; + } + + apm_hal_lp_peri_pms_set_region_cfg(cfg->test_reg_num, regn_cfg); + + for (uint32_t rid = 0; rid < cfg->test_reg_num; rid++) { + uint32_t peri_addr = cfg->test_reg[rid]; + + apm_hal_lp_peri_pms_set_master_region_attr(cfg->master_id, APM_SEC_MODE_TEE, UINT32_MAX); + lp_cpu_peri_addr_rw(peri_addr, false); + + apm_hal_lp_peri_pms_set_master_region_attr(cfg->master_id, APM_SEC_MODE_TEE, UINT32_MAX & ~BIT(rid)); + lp_cpu_peri_addr_rw(peri_addr, true); + } +} +#endif + +void test_sys_pms_master_hp_cpu_slave_hp_peri(void) +{ + const test_pms_periph_cfg_t cfgs[] = { + { + .master_id = APM_MASTER_HPCPU0, + .ctrl_mod = APM_CTRL_HP_PERI_PMS, + .test_reg = test_hp_peri0_reg, + .test_reg_num = sizeof(test_hp_peri0_reg) / sizeof(test_hp_peri0_reg[0]), + .test_peri_grp = HP_PERI0, + }, + { + .master_id = APM_MASTER_HPCPU0, + .ctrl_mod = APM_CTRL_HP_PERI_PMS, + .test_reg = test_hp_peri1_reg, + .test_reg_num = sizeof(test_hp_peri1_reg) / sizeof(test_hp_peri1_reg[0]), + .test_peri_grp = HP_PERI1, + }, + { + .master_id = APM_MASTER_HPCPU0, + .ctrl_mod = APM_CTRL_HP_PERI_PMS, + .test_reg = test_cpu_peri_reg, + .test_reg_num = sizeof(test_cpu_peri_reg) / sizeof(test_cpu_peri_reg[0]), + .test_peri_grp = CPU_PERI, + }, + }; + + test_pms_ctrl_reset_all(); + set_test_vector_table(); + + for (int i = 0; i < sizeof(cfgs) / sizeof(cfgs[0]); i++) { + test_hp_cpu_to_peri_access(&cfgs[i]); + } + + restore_default_vector_table(); +} + +void test_sys_pms_master_hp_cpu_slave_lp_peri(void) +{ + const test_pms_periph_cfg_t cfg = { + .master_id = APM_MASTER_HPCPU0, + .ctrl_mod = APM_CTRL_HP2LP_PERI_PMS, + .test_reg = test_lp_peri_reg, + .test_reg_num = sizeof(test_lp_peri_reg) / sizeof(test_lp_peri_reg[0]), + }; + + test_pms_ctrl_reset_all(); + set_test_vector_table(); + + test_hp_cpu_to_peri_access(&cfg); + + restore_default_vector_table(); +} + +void test_sys_pms_master_hp_cpu_peri_regn_access(void) +{ + const test_pms_periph_cfg_t hp_peri_regn_cfg = { + .master_id = APM_MASTER_HPCPU0, + .test_reg = test_hp_peri_regn_addr, + .test_reg_num = sizeof(test_hp_peri_regn_addr) / sizeof(test_hp_peri_regn_addr[0]), + }; + + const test_pms_periph_cfg_t lp_peri_regn_cfg = { + .master_id = APM_MASTER_HPCPU0, + .test_reg = test_lp_peri_regn_addr, + .test_reg_num = sizeof(test_lp_peri_regn_addr) / sizeof(test_lp_peri_regn_addr[0]), + .test_peri_grp = LP_PERI, + }; + + test_pms_ctrl_reset_all(); + set_test_vector_table(); + + test_hp_cpu_to_peri_access_regn(&hp_peri_regn_cfg); + test_hp_cpu_to_peri_access_regn(&lp_peri_regn_cfg); + + restore_default_vector_table(); +} + +#if CONFIG_ULP_COPROC_ENABLED +void test_sys_pms_master_lp_cpu_slave_hp_peri(void) +{ + const test_pms_periph_cfg_t cfgs[] = { + { + .master_id = APM_MASTER_LPCPU, + .ctrl_mod = APM_CTRL_LP2HP_PERI_PMS, + .test_reg = test_hp_peri0_reg, + .test_reg_num = sizeof(test_hp_peri0_reg) / sizeof(test_hp_peri0_reg[0]), + .test_peri_grp = HP_PERI0, + }, + { + .master_id = APM_MASTER_LPCPU, + .ctrl_mod = APM_CTRL_LP2HP_PERI_PMS, + .test_reg = test_hp_peri1_reg, + .test_reg_num = sizeof(test_hp_peri1_reg) / sizeof(test_hp_peri1_reg[0]), + .test_peri_grp = HP_PERI1, + }, + { + .master_id = APM_MASTER_LPCPU, + .ctrl_mod = APM_CTRL_LP2HP_PERI_PMS, + .test_reg = test_cpu_peri_reg, + .test_reg_num = sizeof(test_cpu_peri_reg) / sizeof(test_cpu_peri_reg[0]), + .test_peri_grp = CPU_PERI, + }, + }; + + test_pms_ctrl_reset_all(); + test_boot_lp_cpu(); + set_test_vector_table(); + + for (int i = 0; i < sizeof(cfgs) / sizeof(cfgs[0]); i++) { + test_lp_cpu_to_peri_access(&cfgs[i]); + } + + restore_default_vector_table(); + test_stop_lp_cpu(); +} + +void test_sys_pms_master_lp_cpu_slave_lp_peri(void) +{ + const test_pms_periph_cfg_t cfg = { + .master_id = APM_MASTER_LPCPU, + .ctrl_mod = APM_CTRL_LP_PERI_PMS, + .test_reg = test_lp_peri_reg, + .test_reg_num = sizeof(test_lp_peri_reg) / sizeof(test_lp_peri_reg[0]), + }; + + test_pms_ctrl_reset_all(); + test_pms_enable_intr(APM_CTRL_LP_PERI_PMS); + test_boot_lp_cpu(); + + set_test_vector_table(); + test_lp_cpu_to_peri_access(&cfg); + restore_default_vector_table(); + + test_stop_lp_cpu(); +} + +void test_sys_pms_master_lp_cpu_peri_regn_access(void) +{ + const test_pms_periph_cfg_t hp_peri_regn_cfg = { + .master_id = APM_MASTER_LPCPU, + .test_reg = test_hp_peri_regn_addr, + .test_reg_num = sizeof(test_hp_peri_regn_addr) / sizeof(test_hp_peri_regn_addr[0]), + }; + + const test_pms_periph_cfg_t lp_peri_regn_cfg = { + .master_id = APM_MASTER_LPCPU, + .test_reg = test_lp_peri_regn_addr, + .test_reg_num = sizeof(test_lp_peri_regn_addr) / sizeof(test_lp_peri_regn_addr[0]), + .test_peri_grp = LP_PERI, + }; + + test_pms_ctrl_reset_all(); + test_pms_enable_intr(APM_CTRL_LP_PERI_PMS); + test_boot_lp_cpu(); + + set_test_vector_table(); + test_lp_cpu_to_peri_access_regn(&hp_peri_regn_cfg); + test_lp_cpu_to_peri_access_regn(&lp_peri_regn_cfg); + restore_default_vector_table(); + + test_stop_lp_cpu(); +} +#endif + +/***************************** DMA_PMS *****************************/ + +typedef struct { + apm_master_dma_id_t master_id; + uint32_t mem_start_addr; + uint32_t mem_end_addr; + uint32_t regn_count; + uint32_t regn_sz; + bool is_ext_mem; +} test_dma_pms_mem_cfg_t; + +#define GDMA_TEST_REGN_RESV_NUM(is_ext_mem) \ + ((is_ext_mem) ? GDMA_EXTMEM_TEST_REGN_RESV_NUM : GDMA_HPMEM_TEST_REGN_RESV_NUM) + +static void test_dma_pms_mem_setup(const test_dma_pms_mem_cfg_t *cfg, uint32_t test_start, uint32_t test_end) +{ + apm_hal_pms_regn_cfg_t regn_cfgs[GDMA_HPMEM_TEST_REGN_NUM] = {0}; + + regn_cfgs[0] = (apm_hal_pms_regn_cfg_t)APM_HAL_PMS_REGION_ENTRY(0, cfg->mem_start_addr, test_start); + regn_cfgs[1] = (apm_hal_pms_regn_cfg_t)APM_HAL_PMS_REGION_ENTRY(1, test_end, cfg->mem_end_addr); + + const uint32_t test_regn_start = GDMA_TEST_REGN_RESV_NUM(cfg->is_ext_mem); + if (cfg->is_ext_mem) { + regn_cfgs[2] = (apm_hal_pms_regn_cfg_t)APM_HAL_PMS_REGION_ENTRY(2, SOC_IRAM_LOW, SOC_DRAM_HIGH); + } + + for (uint32_t idx = test_regn_start; idx < cfg->regn_count; idx++) { + uint32_t regn_start = test_start + (idx - test_regn_start) * cfg->regn_sz; + regn_cfgs[idx] = (apm_hal_pms_regn_cfg_t)APM_HAL_PMS_REGION_ENTRY(idx, regn_start, regn_start + cfg->regn_sz); + } + + apm_hal_dma_pms_set_region_cfg(GDMA_HPMEM_TEST_REGN_NUM, regn_cfgs); +} + +static void gdma_hpmem_addr_rw(uint8_t *src, uint8_t *dest, size_t size, bool should_panic) +{ + pms_dma_excp_flag = false; + memset(src, 0xA5, size); + esp_cache_msync(src, size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); + + test_gdma_init(); + test_gdma_m2m_transfer(src, dest, size); + + test_delay_ms(10); + if (should_panic) { + TEST_ASSERT(pms_dma_excp_flag); + } else { + test_gdma_wait_done(); + esp_cache_msync(dest, size, ESP_CACHE_MSYNC_FLAG_DIR_M2C); + TEST_ASSERT_FALSE(pms_dma_excp_flag); + TEST_ASSERT_EQUAL_HEX8_ARRAY(src, dest, size); + } + + test_gdma_deinit(); + pms_dma_excp_flag = false; +} + +static void test_gdma_to_xmem_access(const test_dma_pms_mem_cfg_t *cfg, uint32_t test_start_addr) +{ + uint8_t *test_dma_buf = heap_caps_aligned_alloc(cfg->regn_sz, cfg->regn_sz, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + TEST_ASSERT_NOT_NULL(test_dma_buf); + memset(test_dma_buf, 0x5A, cfg->regn_sz); + + const uint32_t test_regn_start = GDMA_TEST_REGN_RESV_NUM(cfg->is_ext_mem); + const uint32_t resv_regn = BIT(test_regn_start) - 1; + + for (uint32_t regn_idx = test_regn_start; regn_idx < cfg->regn_count; regn_idx++) { + uint8_t *regn_start = (uint8_t *)(test_start_addr + (regn_idx - test_regn_start) * cfg->regn_sz); + + apm_hal_dma_pms_set_master_region_attr(cfg->master_id, resv_regn, resv_regn | BIT(regn_idx)); + gdma_hpmem_addr_rw(regn_start, test_dma_buf, cfg->regn_sz, true); + gdma_hpmem_addr_rw(test_dma_buf, regn_start, cfg->regn_sz, false); + + apm_hal_dma_pms_set_master_region_attr(cfg->master_id, resv_regn | BIT(regn_idx), resv_regn); + gdma_hpmem_addr_rw(regn_start, test_dma_buf, cfg->regn_sz, false); + gdma_hpmem_addr_rw(test_dma_buf, regn_start, cfg->regn_sz, true); + + apm_hal_dma_pms_set_master_region_attr(cfg->master_id, UINT32_MAX, UINT32_MAX); + } + + free(test_dma_buf); +} + +void test_sys_pms_master_gdma_slave_hp_mem(void) +{ + test_pms_ctrl_reset_all(); + test_pms_enable_intr(APM_CTRL_DMA_PMS); + + const uint32_t total_sz = (GDMA_HPMEM_TEST_REGN_NUM - GDMA_HPMEM_TEST_REGN_RESV_NUM) * GDMA_HPMEM_TEST_REGN_SIZE; + test_dma_pms_mem_cfg_t cfg = { + .master_id = APM_MASTER_DMA_AHB_PDMA_DUMMY, + .mem_start_addr = SOC_IRAM_LOW, + .mem_end_addr = SOC_DRAM_HIGH, + .regn_count = GDMA_HPMEM_TEST_REGN_NUM, + .regn_sz = GDMA_HPMEM_TEST_REGN_SIZE, + }; + + uint8_t *test_hpmem_buf = heap_caps_aligned_alloc(cfg.regn_sz, total_sz, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + TEST_ASSERT_NOT_NULL(test_hpmem_buf); + + uint32_t test_start_addr = (uint32_t)test_hpmem_buf; + uint32_t test_end_addr = test_start_addr + total_sz; + test_dma_pms_mem_setup(&cfg, test_start_addr, test_end_addr); + + test_gdma_to_xmem_access(&cfg, test_start_addr); + free(test_hpmem_buf); +} + +#if CONFIG_SPIRAM +void test_sys_pms_master_gdma_slave_ext_mem(void) +{ + test_pms_ctrl_reset_all(); + test_pms_enable_intr(APM_CTRL_DMA_PMS); + + const uint32_t total_sz = (GDMA_HPMEM_TEST_REGN_NUM - GDMA_EXTMEM_TEST_REGN_RESV_NUM) * GDMA_HPMEM_TEST_REGN_SIZE; + test_dma_pms_mem_cfg_t cfg = { + .master_id = APM_MASTER_DMA_AHB_PDMA_DUMMY, + .mem_start_addr = SOC_EXTRAM_LOW, + .mem_end_addr = SOC_EXTRAM_HIGH, + .regn_count = GDMA_HPMEM_TEST_REGN_NUM, + .regn_sz = GDMA_HPMEM_TEST_REGN_SIZE, + .is_ext_mem = true, + }; + + uint8_t *test_extmem_buf = heap_caps_aligned_alloc(cfg.regn_sz, total_sz, MALLOC_CAP_SPIRAM); + TEST_ASSERT_NOT_NULL(test_extmem_buf); + + uint32_t test_start_addr = (uint32_t)test_extmem_buf; + uint32_t test_end_addr = test_start_addr + total_sz; + test_dma_pms_mem_setup(&cfg, test_start_addr, test_end_addr); + + test_gdma_to_xmem_access(&cfg, test_start_addr); + free(test_extmem_buf); +} +#endif diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_sys_apm.c b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_sys_apm.c index 6f8de78a6b4..23c3ef3d4d2 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_sys_apm.c +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/pms/test_tee_sys_apm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,9 +14,8 @@ #include "hal/apm_hal.h" #include "hal/apm_types.h" -#include "rom/cache.h" +#include "esp_cache.h" #include "esp_rom_sys.h" -#include "esp_memory_utils.h" #include "esp_heap_caps.h" #include "test_pms_priv.h" @@ -34,7 +33,25 @@ APM_HAL_REGION_ENTRY(path, id, start, end, perm) #endif -extern bool apm_master_excp_flag[APM_MASTER_MAX]; +typedef struct { + apm_master_id_t master_id; + apm_ctrl_module_t ctrl_mod; + apm_ctrl_access_path_t path; + uint32_t mem_start_addr; + uint32_t mem_end_addr; + uint32_t regn_count; + uint32_t regn_sz; +} test_sys_apm_mem_cfg_t; + +typedef struct { + apm_master_id_t master_id; + apm_ctrl_module_t ctrl_mod; + const uint32_t *test_addr; + uint32_t test_addr_num; + uint32_t test_addr_resv_mask; +} test_sys_apm_periph_cfg_t; + +extern volatile bool apm_master_excp_flag[APM_MASTER_MAX]; /***************************** APM setup for memory *****************************/ @@ -65,31 +82,21 @@ static void test_mem_apm_setup(test_sys_apm_mem_cfg_t *cfg, uint32_t test_start_ /***************************** GDMA: Utility *****************************/ -static void gdma_xmem_addr_rw(uint8_t *src, uint8_t *dest, size_t size, uint32_t test_attr) +static void gdma_xmem_addr_rw(uint8_t *src, uint8_t *dest, size_t size, bool should_panic) { apm_master_excp_flag[TEST_GDMA_APM_MASTER_ID] = false; - memset(src, TEST_VAL, size); + memset(src, 0xA5, size); + esp_cache_msync(src, size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); test_gdma_init(); -#if CONFIG_SPIRAM - if (esp_ptr_external_ram(src)) { - Cache_WriteBack_Addr((uint32_t)src, size); - } -#endif test_gdma_m2m_transfer(src, dest, size); -#if CONFIG_SPIRAM - if (esp_ptr_external_ram(dest)) { - Cache_Invalidate_Addr((uint32_t)dest, size); - } -#endif - if (!test_attr) { - test_delay_ms(10); + test_delay_ms(10); + if (should_panic) { TEST_ASSERT(apm_master_excp_flag[TEST_GDMA_APM_MASTER_ID]); - test_gdma_wait_done(); } else { test_gdma_wait_done(); - test_delay_ms(10); + esp_cache_msync(dest, size, ESP_CACHE_MSYNC_FLAG_DIR_M2C); TEST_ASSERT_FALSE(apm_master_excp_flag[TEST_GDMA_APM_MASTER_ID]); TEST_ASSERT_EQUAL_HEX8_ARRAY(src, dest, size); } @@ -109,26 +116,22 @@ static void test_gdma_to_xmem_access(const test_sys_apm_mem_cfg_t *cfg, uint32_t for (uint32_t regn_idx = 2; regn_idx < cfg->regn_count; regn_idx++) { uint8_t *regn_start = (uint8_t *)(test_start_addr + (regn_idx - 2) * cfg->regn_sz); - uint32_t pms_attr = APM_PERM_NONE; if (mode == APM_SEC_MODE_TEE) { - pms_attr = APM_PERM_R | APM_PERM_W; - gdma_xmem_addr_rw(regn_start, test_dma_buf, cfg->regn_sz, pms_attr & APM_PERM_R); - gdma_xmem_addr_rw(test_dma_buf, regn_start, cfg->regn_sz, pms_attr & APM_PERM_W); + gdma_xmem_addr_rw(regn_start, test_dma_buf, cfg->regn_sz, false); + gdma_xmem_addr_rw(test_dma_buf, regn_start, cfg->regn_sz, false); continue; } - pms_attr = APM_PERM_W; apm_hal_set_sec_mode_region_attr(cfg->ctrl_mod, regn_idx, mode, APM_PERM_NONE); - apm_hal_set_sec_mode_region_attr(cfg->ctrl_mod, regn_idx, mode, pms_attr); - gdma_xmem_addr_rw(regn_start, test_dma_buf, cfg->regn_sz, pms_attr & APM_PERM_R); - gdma_xmem_addr_rw(test_dma_buf, regn_start, cfg->regn_sz, pms_attr & APM_PERM_W); + apm_hal_set_sec_mode_region_attr(cfg->ctrl_mod, regn_idx, mode, APM_PERM_W); + gdma_xmem_addr_rw(regn_start, test_dma_buf, cfg->regn_sz, true); + gdma_xmem_addr_rw(test_dma_buf, regn_start, cfg->regn_sz, false); - pms_attr = APM_PERM_R; apm_hal_set_sec_mode_region_attr(cfg->ctrl_mod, regn_idx, mode, APM_PERM_NONE); - apm_hal_set_sec_mode_region_attr(cfg->ctrl_mod, regn_idx, mode, pms_attr); - gdma_xmem_addr_rw(regn_start, test_dma_buf, cfg->regn_sz, pms_attr & APM_PERM_R); - gdma_xmem_addr_rw(test_dma_buf, regn_start, cfg->regn_sz, pms_attr & APM_PERM_W); + apm_hal_set_sec_mode_region_attr(cfg->ctrl_mod, regn_idx, mode, APM_PERM_R); + gdma_xmem_addr_rw(regn_start, test_dma_buf, cfg->regn_sz, false); + gdma_xmem_addr_rw(test_dma_buf, regn_start, cfg->regn_sz, true); apm_hal_set_sec_mode_region_attr(cfg->ctrl_mod, regn_idx, mode, APM_PERM_ALL); } @@ -545,7 +548,7 @@ static void lp_cpu_xmem_addr_rw(uint32_t mem_addr, size_t size, uint32_t attr) SEND_MSG(MSG_SLAVE_WRITE); SEND_ADDR(mem_addr); - SEND_SIZE(sizeof(uint32_t)); + SEND_DATA(sizeof(uint32_t)); test_delay_ms(10); bool can_write = (attr & APM_PERM_W); @@ -868,13 +871,13 @@ void test_tee_mode_default_access(void) test_tee_mode_apm_setup(&cfg, (uint32_t)test_hpmem_buf, (uint32_t)test_hpmem_buf + total_sz); apm_ll_hp_tee_set_master_sec_mode(TEST_GDMA_APM_MASTER_ID, APM_SEC_MODE_TEE); - uint32_t pms_attr = APM_PERM_R | APM_PERM_W; + bool should_panic = false; #if SOC_APM_CTRL_TEE_MODE_ACCESS_BUG - pms_attr = APM_PERM_NONE; + should_panic = true; #endif - gdma_xmem_addr_rw(test_hpmem_buf, test_dma_buf, total_sz, pms_attr & APM_PERM_R); - gdma_xmem_addr_rw(test_dma_buf, test_hpmem_buf, total_sz, pms_attr & APM_PERM_W); + gdma_xmem_addr_rw(test_hpmem_buf, test_dma_buf, total_sz, should_panic); + gdma_xmem_addr_rw(test_dma_buf, test_hpmem_buf, total_sz, should_panic); free(test_dma_buf); free(test_hpmem_buf); diff --git a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/ulp/ulp_lp_core_main.c b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/ulp/ulp_lp_core_main.c index 44feb46850a..4e282fed2d7 100644 --- a/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/ulp/ulp_lp_core_main.c +++ b/components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/ulp/ulp_lp_core_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,7 @@ #include #include "soc/soc.h" +#include "esp_attr.h" #include "riscv/csr.h" #include "riscv/rv_utils.h" @@ -53,6 +54,32 @@ void test_panicHandler(void *frame, int exccause) return; } +NOINLINE_ATTR static uint32_t reg_read(uint32_t addr) +{ + uint32_t value; + __asm__ volatile( + "lw %0, 0(%1)\n" + "fence\n" + "nop\nnop\nnop\nnop\n" + : "=r"(value) + : "r"(addr) + : "memory" + ); + return value; +} + +NOINLINE_ATTR static void reg_write(uint32_t addr, uint32_t value) +{ + __asm__ volatile( + "sw %1, 0(%0)\n" + "fence\n" + "nop\nnop\nnop\nnop\n" + : + : "r"(addr), "r"(value) + : "memory" + ); +} + /** * @brief Test LP CPU access to memory/peripherals * @@ -84,14 +111,14 @@ int main(void) } uint32_t test_addr = RECV_ADDR(); - uint32_t test_size = RECV_SIZE(); + uint32_t test_data = RECV_DATA(); switch (test_msg) { case MSG_SLAVE_READ: - (void)REG_READ(test_addr); + (void)reg_read(test_addr); break; case MSG_SLAVE_WRITE: - REG_WRITE(test_addr, test_size); + reg_write(test_addr, test_data); break; case MSG_SLAVE_EXEC: { void (*func_ptr)(void) = (void (*)(void))(test_addr); diff --git a/components/esp_hal_security/test_apps/tee/main/test_pms.c b/components/esp_hal_security/test_apps/tee/main/test_pms.c index 297e582a5ad..631be942763 100644 --- a/components/esp_hal_security/test_apps/tee/main/test_pms.c +++ b/components/esp_hal_security/test_apps/tee/main/test_pms.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -245,4 +245,116 @@ TEST_CASE("Test LP_CPU -> LP_PERI access", "[PERI_APM]") } #endif /* CONFIG_ULP_COPROC_ENABLED */ #endif +#else +/** + * Test HP-CPU access to HP_PERI + * + * PMS uses per-peripheral based access control with per-master read/write permissions. + * For each peripheral, tests HP-CPU read/write access with varying permissions: + * all access (both read and write pass) and no access (both read and write fail). + * Verifies enforcement of PMS access control by asserting expected load/store access faults. + */ +TEST_CASE("Test HP_CPU -> HP_PERI access", "[SYS_APM]") +{ + test_sys_pms_master_hp_cpu_slave_hp_peri(); +} + +/** + * Test HP-CPU access to LP_PERI + * + * PMS uses per-peripheral based access control with per-master read/write permissions. + * For each peripheral, tests HP-CPU read/write access with varying permissions: + * all access (both read and write pass) and no access (both read and write fail). + * Verifies enforcement of PMS access control by asserting expected load/store access faults. + */ +TEST_CASE("Test HP_CPU -> LP_PERI access", "[SYS_APM]") +{ + test_sys_pms_master_hp_cpu_slave_lp_peri(); +} + +/** + * Test HP-CPU access to HP_PERI and LP_PERI (configurable regions) + * + * PMS also provides region-based access control with start/end address boundaries and per-master + * read/write permissions. Configures PMS regions covering HP_PERI and LP_PERI address + * ranges. For each region, tests HP-CPU read/write access with varying permissions in + * both TEE and REE modes: all access (both read and write pass) and no access (both read + * and write fail). Verifies enforcement of PMS access control by asserting expected PMS violations. + */ +TEST_CASE("Test HP_CPU -> PERI access (configurable regions)", "[SYS_APM]") +{ + test_sys_pms_master_hp_cpu_peri_regn_access(); +} + +#if CONFIG_ULP_COPROC_ENABLED +/** + * Test LP-CPU access to HP_PERI + * + * PMS uses per-peripheral based access control with per-master read/write permissions. + * For each peripheral, tests LP-CPU read/write access with varying permissions: + * all access (both read and write pass) and no access (both read and write fail). + * Verifies enforcement of PMS access control by asserting expected load/store access faults. + */ +TEST_CASE("Test LP_CPU -> HP_PERI access", "[SYS_APM]") +{ + test_sys_pms_master_lp_cpu_slave_hp_peri(); +} + +/** + * Test LP-CPU access to LP_PERI + * + * PMS uses per-peripheral based access control with per-master read/write permissions. + * For each peripheral, tests LP-CPU read/write access with varying permissions: + * all access (both read and write pass) and no access (both read and write fail). + * Verifies enforcement of PMS access control by asserting expected PMS violations. + */ +TEST_CASE("Test LP_CPU -> LP_PERI access", "[SYS_APM]") +{ + test_sys_pms_master_lp_cpu_slave_lp_peri(); +} + +/** + * Test LP-CPU access to HP_PERI and LP_PERI (configurable regions) + * + * PMS uses region-based access control with start/end address boundaries and per-master + * read/write permissions. Configures PMS regions covering HP_PERI and LP_PERI address + * ranges. For each region, tests LP-CPU read/write access with varying permissions: + * all access (both read and write pass) and no access (both read and write fail). + * Verifies enforcement of PMS access control by asserting expected PMS violations. + */ +TEST_CASE("Test LP_CPU -> PERI access (configurable regions)", "[SYS_APM]") +{ + test_sys_pms_master_lp_cpu_peri_regn_access(); +} +#endif /* CONFIG_ULP_COPROC_ENABLED */ + +/** + * Test GDMA access to HP_MEM + * + * PMS uses region-based access control with start/end address boundaries and per-master + * read/write permissions. Divides a contiguous HP_MEM block into multiple PMS regions and + * configures their boundaries. For each region, tests GDMA read/write access with varying + * permissions: R-only (read passes, write fails) and W-only (write passes, read fails). + * Verifies enforcement of PMS access control by asserting expected PMS violations. + */ +TEST_CASE("Test GDMA -> HP_MEM access", "[SYS_APM]") +{ + test_sys_pms_master_gdma_slave_hp_mem(); +} + +#if CONFIG_SPIRAM +/** + * Test GDMA access to EXT_MEM (SPIRAM) + * + * PMS uses region-based access control with start/end address boundaries and per-master + * read/write permissions. Divides a contiguous EXT_MEM block into multiple PMS regions and + * configures their boundaries. For each region, tests GDMA read/write access with varying + * permissions: R-only (read passes, write fails) and W-only (write passes, read fails). + * Verifies enforcement of PMS access control by asserting expected PMS violations. + */ +TEST_CASE("Test GDMA -> EXT_MEM access", "[SYS_APM]") +{ + test_sys_pms_master_gdma_slave_ext_mem(); +} +#endif /* CONFIG_SPIRAM */ #endif /* SOC_APM_CTRL_FILTER_SUPPORTED */ diff --git a/components/esp_hal_security/test_apps/tee/pytest_pms_and_cpu_intr.py b/components/esp_hal_security/test_apps/tee/pytest_pms_and_cpu_intr.py index 729db08e3ac..348a2b7b47f 100644 --- a/components/esp_hal_security/test_apps/tee/pytest_pms_and_cpu_intr.py +++ b/components/esp_hal_security/test_apps/tee/pytest_pms_and_cpu_intr.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 import pytest from pytest_embedded_idf import IdfDut @@ -6,7 +6,7 @@ from pytest_embedded_idf.utils import idf_parametrize # ---------------- Pytest build parameters ---------------- -SOC_SUPPORT_SYS_APM_TEST = ['esp32c6', 'esp32h2', 'esp32c5', 'esp32c61'] +SOC_SUPPORT_SYS_APM_TEST = ['esp32c6', 'esp32h2', 'esp32c5', 'esp32c61', 'esp32p4'] SOC_SUPPORT_PERI_APM_TEST = ['esp32c5'] SOC_SUPPORT_INTR_TEST = ['esp32c5', 'esp32c61', 'esp32p4'] diff --git a/components/esp_hal_security/test_apps/tee/sdkconfig.defaults.esp32p4 b/components/esp_hal_security/test_apps/tee/sdkconfig.defaults.esp32p4 index 153bd95bfc9..7b7e4c56a9e 100644 --- a/components/esp_hal_security/test_apps/tee/sdkconfig.defaults.esp32p4 +++ b/components/esp_hal_security/test_apps/tee/sdkconfig.defaults.esp32p4 @@ -2,3 +2,11 @@ # U-mode for multicore SoCs. Thus, TEE interrupt tests will # run only in unicore mode till then. CONFIG_FREERTOS_UNICORE=y + +# Enable LP core +CONFIG_ULP_COPROC_ENABLED=y +CONFIG_ULP_COPROC_RESERVE_MEM=8192 +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=n + +# Enable SPIRAM +CONFIG_SPIRAM=y