Merge branch 'bugfix/uart_related_backports_v6.0' into 'release/v6.0'

fix(uart): some related uart backports (v6.0)

See merge request espressif/esp-idf!43612

components/bootloader_support/src/bootloader_console.c

@@ -30,6 +30,7 @@ static void __attribute__((unused)) release_default_console_io(void)
 {
     // Default console is UART0 with TX and RX on their IOMUX pins
     gpio_ll_output_disable(&GPIO, U0TXD_GPIO_NUM);
+    gpio_ll_func_sel(&GPIO, U0TXD_GPIO_NUM, PIN_FUNC_GPIO); // Set TX pin to GPIO function to truly disable output
     esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(UART_NUM_0, SOC_UART_PERIPH_SIGNAL_RX), 0);
 }
 

components/esp_driver_gpio/src/gpio.c

@@ -207,7 +207,8 @@ esp_err_t gpio_output_disable(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
     gpio_hal_output_disable(gpio_context.gpio_hal, gpio_num);
-    gpio_hal_set_output_enable_ctrl(gpio_context.gpio_hal, gpio_num, false, false); // so that output disable could take effect
+    gpio_hal_set_output_enable_ctrl(gpio_context.gpio_hal, gpio_num, false, false); // so that output disable could always take effect when func sel is GPIO
+    gpio_hal_func_sel(gpio_context.gpio_hal, gpio_num, PIN_FUNC_GPIO); // otherwise the oe can only be controlled by peripheral
     return ESP_OK;
 }
 
@@ -216,6 +217,7 @@ esp_err_t gpio_output_enable(gpio_num_t gpio_num)
     GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
     gpio_hal_matrix_out_default(gpio_context.gpio_hal, gpio_num); // No peripheral output signal routed to the pin, just as a simple GPIO output
     gpio_hal_output_enable(gpio_context.gpio_hal, gpio_num);
+    gpio_hal_func_sel(gpio_context.gpio_hal, gpio_num, PIN_FUNC_GPIO); // otherwise the oe can only be controlled by peripheral
     return ESP_OK;
 }
 
@@ -1085,9 +1087,10 @@ esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask)
         gpio_get_io_config(gpio_num, &io_config);
 
         // When the IO is used as a simple GPIO output, oe signal can only be controlled by the oe register
-        // When the IO is not used as a simple GPIO output, oe signal could be controlled by the peripheral
+        // When the IO connects to a peripheral signal through GPIO Matrix, oe signal can be controlled by the peripheral or the oe register (switch by oe_ctrl_by_periph)
+        // When the IO connects to a peripheral signal through IOMUX, oe signal can only be controlled by the peripheral
         const char *oe_str = io_config.oe ? "1" : "0";
-        if (io_config.sig_out != SIG_GPIO_OUT_IDX && io_config.oe_ctrl_by_periph) {
+        if (io_config.fun_sel != PIN_FUNC_GPIO || io_config.oe_ctrl_by_periph) {
             oe_str = "[periph_sig_ctrl]";
         }
 

components/esp_driver_uart/src/uart.c

@@ -85,8 +85,8 @@ static const char *UART_TAG = "uart";
                             | (UART_INTR_RXFIFO_TOUT) \
                             | (UART_INTR_RXFIFO_OVF) \
                             | (UART_INTR_BRK_DET) \
-                            | (UART_INTR_PARITY_ERR)) \
+                            | (UART_INTR_PARITY_ERR) \
-                            | (UART_INTR_WAKEUP)
+                            | (UART_INTR_WAKEUP))
 #else
 #define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \
                             | (UART_INTR_RXFIFO_TOUT) \
@@ -223,6 +223,10 @@ static bool uart_module_enable(uart_port_t uart_num)
                 uart_ll_enable_bus_clock(uart_num, true);
             }
             if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
+                // Workaround: Set RX signal to high to avoid false RX BRK_DET interrupt raised after register reset
+                if (uart_context[uart_num].rx_io_num == -1) {
+                    esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX), false);
+                }
                 HP_UART_BUS_CLK_ATOMIC() {
                     uart_ll_reset_register(uart_num);
                 }
@@ -253,6 +257,16 @@ static bool uart_module_enable(uart_port_t uart_num)
         }
 #if (SOC_UART_LP_NUM >= 1)
         else {
+            // Workaround: Set RX signal to high to avoid false RX BRK_DET interrupt raised after register reset
+            if (uart_context[uart_num].rx_io_num == -1) { // if RX pin is already configured, then workaround not needed, skip
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+                lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX), false);
+#else
+                // the signal is directly connected to its LP IO pin, the only way is to enable its pullup
+                uint32_t io_num = uart_periph_signal[uart_num].pins[SOC_UART_PERIPH_SIGNAL_RX].default_gpio;
+                gpio_pullup_en(io_num);
+#endif
+            }
             LP_UART_BUS_CLK_ATOMIC() {
                 lp_uart_ll_enable_bus_clock(TO_LP_UART_NUM(uart_num), true);
                 lp_uart_ll_reset_register(TO_LP_UART_NUM(uart_num));
@@ -718,6 +732,12 @@ static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t id
         }
         rtc_gpio_init(io_num);
         rtc_gpio_iomux_func_sel(io_num, upin->iomux_func);
+        // undo the workaround done in uart_module_enable for RX pin
+#if !SOC_LP_GPIO_MATRIX_SUPPORTED
+        if (upin->input) {
+            gpio_pullup_dis(io_num);
+        }
+#endif
     }
 #endif
 
@@ -1056,8 +1076,8 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
     uint32_t sclk_freq;
     ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "invalid src_clk");
 
-    // Enable the newly selected clock source.
+    // Enable the newly selected clock source
-    ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_sclk_sel, true), UART_TAG, "clock source enable failed");
+    esp_clk_tree_enable_src(uart_sclk_sel, true);
 #if SOC_UART_SUPPORT_RTC_CLK
     if (uart_sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) {
         periph_rtc_dig_clk8m_enable();
@@ -1066,8 +1086,6 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
 
     bool success = false;
     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
-    soc_module_clk_t uart_old_sclk_sel = uart_context[uart_num].sclk_sel;
-    uart_context[uart_num].sclk_sel = uart_sclk_sel;
     uart_hal_init(&(uart_context[uart_num].hal), uart_num);
     if (uart_num < SOC_UART_HP_NUM) {
         HP_UART_SRC_CLK_ATOMIC() {
@@ -1083,7 +1101,6 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
         success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq);
     }
 #endif
-    // Disable the previously selected clock source
     uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity);
     uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits);
     uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits);
@@ -1092,8 +1109,18 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
     uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
     uart_hal_txfifo_rst(&(uart_context[uart_num].hal));
-    ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_old_sclk_sel, false), UART_TAG, "clock source disable failed");
+    // Disable the previously selected clock source, and update the new source in context
-    ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable");
+    soc_module_clk_t uart_old_sclk_sel = uart_context[uart_num].sclk_sel;
+    esp_clk_tree_enable_src(uart_old_sclk_sel, false);
+    if (success) {
+        uart_context[uart_num].sclk_sel = uart_sclk_sel;
+    } else {
+        uart_context[uart_num].sclk_sel = -1;
+        esp_clk_tree_enable_src(uart_sclk_sel, false);
+        ESP_LOGE(UART_TAG, "baud rate unachievable");
+        return ESP_FAIL;
+    }
+
 #if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
     // Create sleep retention link if desired
     if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
@@ -1620,10 +1647,12 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool
         while (size > 0) {
             size_t free_size = xRingbufferGetCurFreeSize(p_uart_obj[uart_num]->tx_ring_buf);
             size_t send_size = MIN(size, free_size);
-            xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *)(src + offset), send_size, portMAX_DELAY);
+            if (send_size > 0) {
-            size -= send_size;
+                xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *)(src + offset), send_size, portMAX_DELAY);
-            offset += send_size;
+                size -= send_size;
-            uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT));
+                offset += send_size;
+                uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT));
+            }
         }
     } else {
         while (size) {
@@ -2017,12 +2046,6 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
         return ESP_FAIL;
     }
 
-    uart_intr_config_t uart_intr = {
-        .intr_enable_mask = UART_INTR_CONFIG_FLAG,
-        .rxfifo_full_thresh = UART_THRESHOLD_NUM(uart_num, UART_FULL_THRESH_DEFAULT),
-        .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT,
-        .txfifo_empty_intr_thresh = UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT),
-    };
     uart_module_enable(uart_num);
     uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
@@ -2038,6 +2061,42 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
           );
     ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not allocate an interrupt for UART");
 
+    // Make sure uart sclk at least exist first (following code touchs hardware, and requires sclk to be enabled)
+    if (uart_context[uart_num].sclk_sel == -1 && uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
+        // set to a default clock source
+        soc_module_clk_t default_sclk = -1;
+        if (uart_num < SOC_UART_HP_NUM) {
+            default_sclk = UART_SCLK_DEFAULT;
+        }
+#if (SOC_UART_LP_NUM >= 1)
+        else {
+            default_sclk = LP_UART_SCLK_DEFAULT;
+        }
+#endif
+        esp_clk_tree_enable_src(default_sclk, true);
+        UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
+        if (uart_num < SOC_UART_HP_NUM) {
+            HP_UART_SRC_CLK_ATOMIC() {
+                uart_hal_set_sclk(&(uart_context[uart_num].hal), default_sclk);
+            }
+        }
+#if (SOC_UART_LP_NUM >= 1)
+        else {
+            LP_UART_SRC_CLK_ATOMIC() {
+                lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)default_sclk);
+            }
+        }
+#endif
+        uart_context[uart_num].sclk_sel = default_sclk;
+        UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
+    }
+
+    uart_intr_config_t uart_intr = {
+        .intr_enable_mask = UART_INTR_CONFIG_FLAG,
+        .rxfifo_full_thresh = UART_THRESHOLD_NUM(uart_num, UART_FULL_THRESH_DEFAULT),
+        .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT,
+        .txfifo_empty_intr_thresh = UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT),
+    };
     ret = uart_intr_config(uart_num, &uart_intr);
     ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not configure the interrupt for UART");
 
@@ -2066,14 +2125,15 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
     uart_free_driver_obj(p_uart_obj[uart_num]);
     p_uart_obj[uart_num] = NULL;
 
-    ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false), UART_TAG, "clock source disable failed");
+    if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
+        esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false);
 #if SOC_UART_SUPPORT_RTC_CLK
-    soc_module_clk_t sclk = 0;
+        if (uart_context[uart_num].sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) {
-    uart_hal_get_sclk(&(uart_context[uart_num].hal), &sclk);
+            periph_rtc_dig_clk8m_disable();
-    if (sclk == (soc_module_clk_t)UART_SCLK_RTC) {
+        }
-        periph_rtc_dig_clk8m_disable();
-    }
 #endif
+        uart_context[uart_num].sclk_sel = -1;
+    }
 
 #if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
     // Free sleep retention link for HP UART
@@ -2275,7 +2335,7 @@ esp_err_t uart_detect_bitrate_start(uart_port_t uart_num, const uart_bitrate_det
         uart_sclk_sel = (soc_module_clk_t)((config->source_clk) ? config->source_clk : UART_SCLK_DEFAULT); // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock
         uint32_t sclk_freq = 0;
         ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), err, UART_TAG, "invalid source_clk");
-        ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(uart_sclk_sel, true), err, UART_TAG, "clock source enable failed");
+        esp_clk_tree_enable_src(uart_sclk_sel, true);
 #if SOC_UART_SUPPORT_RTC_CLK
         if (uart_sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) {
             periph_rtc_dig_clk8m_enable();
@@ -2285,6 +2345,7 @@ esp_err_t uart_detect_bitrate_start(uart_port_t uart_num, const uart_bitrate_det
             uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
             uart_hal_set_baudrate(&(uart_context[uart_num].hal), 57600, sclk_freq); // set to any baudrate
         }
+        uart_context[uart_num].sclk_sel = uart_sclk_sel;
         _uart_set_pin6(uart_num, UART_PIN_NO_CHANGE, config->rx_io_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
     } else if (config != NULL) {
         ESP_LOGW(UART_TAG, "unable to re-configure for an acquired port, ignoring the new config");
@@ -2337,12 +2398,15 @@ esp_err_t uart_detect_bitrate_stop(uart_port_t uart_num, bool deinit, uart_bitra
 
     if (deinit) { // release the port
         uart_release_pin(uart_num, true, true, true, true, true, true);
-        ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false), UART_TAG, "clock source disable failed");
+        if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
+            esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false);
 #if SOC_UART_SUPPORT_RTC_CLK
-        if (src_clk == (soc_module_clk_t)UART_SCLK_RTC) {
+            if (src_clk == (soc_module_clk_t)UART_SCLK_RTC) {
-            periph_rtc_dig_clk8m_disable();
+                periph_rtc_dig_clk8m_disable();
-        }
+            }
 #endif
+            uart_context[uart_num].sclk_sel = -1;
+        }
         uart_module_disable(uart_num);
     }
     return ret;

components/esp_driver_uart/test_apps/rs485/main/test_app_main.c

@@ -10,7 +10,7 @@
 #include "esp_heap_caps.h"
 #include "esp_newlib.h"
 
-#define TEST_MEMORY_LEAK_THRESHOLD (200)
+#define TEST_MEMORY_LEAK_THRESHOLD (250)
 
 void setUp(void)
 {

components/esp_driver_uart/test_apps/uart/main/test_uart.c

@@ -440,7 +440,7 @@ TEST_CASE("uart tx ring buffer free space test", "[uart]")
         uart_port_t uart_num = port_param.port_num;
         uint8_t *rd_data = (uint8_t *)malloc(1024);
         TEST_ASSERT_NOT_NULL(rd_data);
-        uint8_t *wr_data = (uint8_t *)malloc(256);
+        uint8_t *wr_data = (uint8_t *)malloc(2048);
         TEST_ASSERT_NOT_NULL(wr_data);
         uart_config_t uart_config = {
             .baud_rate = 2000000,
@@ -475,7 +475,7 @@ TEST_CASE("uart tx ring buffer free space test", "[uart]")
         TEST_ASSERT_EQUAL_INT(0, tx_buffer_free_space); // tx buffer is full
 
         // Let CTS be low, so that transmission is unblocked
-        esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, uart_periph_signal[uart_num].pins[SOC_UART_PERIPH_SIGNAL_CTS].signal, true);
+        esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, uart_periph_signal[uart_num].pins[SOC_UART_PERIPH_SIGNAL_CTS].signal, false);
         uart_wait_tx_done(uart_num, portMAX_DELAY);
         uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space);
         TEST_ASSERT_EQUAL_INT(2020, tx_buffer_free_space); // tx buffer is back to full capacity

components/esp_system/port/soc/esp32c5/system_internal.c

@@ -36,8 +36,11 @@
 void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
-    esp_rom_output_tx_wait_idle(0);
+    for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
-    esp_rom_output_tx_wait_idle(1);
+        if (uart_ll_is_enabled(i)) {
+            esp_rom_output_tx_wait_idle(i);
+        }
+    }
 
     // TODO: IDF-8845
 #if SOC_MODEM_CLOCK_SUPPORTED

components/hal/esp32/include/hal/gpio_ll.h

@@ -710,7 +710,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32c2/include/hal/gpio_ll.h

@@ -512,7 +512,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32c3/include/hal/gpio_ll.h

@@ -510,7 +510,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32c5/include/hal/gpio_ll.h

@@ -508,7 +508,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32c6/include/hal/gpio_ll.h

@@ -471,7 +471,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32c61/include/hal/gpio_ll.h

@@ -508,7 +508,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32h2/include/hal/gpio_ll.h

@@ -517,7 +517,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32h21/include/hal/gpio_ll.h

@@ -498,7 +498,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32h4/include/hal/gpio_ll.h

@@ -518,7 +518,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Set peripheral output to an GPIO pad through the IOMUX.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32p4/include/hal/gpio_ll.h

@@ -635,7 +635,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32s2/include/hal/gpio_ll.h

@@ -524,7 +524,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/esp32s3/include/hal/gpio_ll.h

@@ -525,7 +525,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 }
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.

components/hal/gpio_hal.c

@@ -42,8 +42,8 @@ void gpio_hal_iomux_in(gpio_hal_context_t *hal, uint32_t gpio_num, int func, uin
 
 void gpio_hal_iomux_out(gpio_hal_context_t *hal, uint32_t gpio_num, int func)
 {
-    gpio_ll_set_output_enable_ctrl(hal->dev, gpio_num, true, false);
     gpio_ll_func_sel(hal->dev, gpio_num, func);
+    // as long as the func sel is not GPIO, the oe can only be controlled by the peripheral
 }
 
 void gpio_hal_matrix_in(gpio_hal_context_t *hal, uint32_t gpio_num, uint32_t signal_idx, bool in_inv)

components/hal/include/hal/gpio_hal.h

@@ -161,7 +161,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
 #define gpio_hal_output_enable(hal, gpio_num) gpio_ll_output_enable((hal)->dev, gpio_num)
 
 /**
-  * @brief Configure the source of output enable signal for the GPIO pin.
+  * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO).
   *
   * @param hal Context of the HAL layer
   * @param gpio_num GPIO number