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fix(parlio): fix max valid delay value

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Chen Jichang
2026-06-08 17:52:17 +08:00
parent 407dfb44a7
commit 0cb56b975b
3 changed files with 4 additions and 5 deletions
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components/hal/esp32h2/include/hal/parlio_ll.h
-1
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@@ -36,7 +36,6 @@
#define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 7 // TXD[7] can be used a valid signal
#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal
#ifdef __cplusplus
extern "C" {
#endif