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Merge branch 'fix/spi_buslock_multi_dev_acq_release_issue_v5.5' into 'release/v5.5'

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fix(esp_hw_support): fixed spi buslock multi dev acq/release logic issue (v5.5)

See merge request espressif/esp-idf!49171
This commit is contained in:
morris
2026-06-10 10:13:03 +08:00
parent 74eedf49c1 61e0dca2a0
commit 0b816722db
8 changed files with 191 additions and 27 deletions
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components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h
+1 -1
View File
@@ -29,7 +29,7 @@ extern "C" {
#if BUS_LOCK_DEBUG
#define BUS_LOCK_DEBUG_EXECUTE_CHECK(x) assert(x)
#else
#define BUS_LOCK_DEBUG_EXECUTE_CHECK(x)
#define BUS_LOCK_DEBUG_EXECUTE_CHECK(x) (void)(x)
#endif
#define CHECK_IOMUX_PIN(HOST, PIN_NAME) if (GPIO.func_in_sel_cfg[spi_periph_signal[(HOST)].PIN_NAME##_in].sig_in_sel) return false
components/esp_hw_support/spi_bus_lock.c
+54 -20
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -87,12 +87,14 @@
* -> STATE_ACQ: by `acquire_core`
*
* - STATE_BG:
* * No acquiring device, the ISR is the acquiring processor, there is BG bits active, but no LOCK
* bits
* * No acquiring device, the ISR is the acquiring processor, and there are BG bits active. There
* may also be LOCK bits pending for another device, but the lock owner must wait until BG is
* fully finished.
* * The BG operation should be enabled while turning into this state.
*
* -> STATE_IDLE: by `bg_exit_core` after `clear_pend_core` for all BG bits
* -> STATE_BG_ACQ: by `schedule_core`, when there is new LOCK bit set (by `acquire_core`)
* -> STATE_BG_ACQ: by `schedule_core`, when there is a new LOCK bit set (by `acquire_core`) and
* BG is active for the same device
*
* - STATE_BG_ACQ:
* * There is acquiring device, the ISR is the acquiring processor, there may be BG bits active for
@@ -115,9 +117,11 @@
*
* -> STATE_BG_ACQ: by `req_core`
* -> STATE_BG_ACQ (other device): by `acquire_end_core`, when there is LOCK bit for another
* device, and the new acquiring device has active BG bits.
* -> STATE_ACQ (other device): by `acquire_end_core`, when there is LOCK bit for another devices,
* but the new acquiring device has no active BG bits.
* device, and BG is active for the new acquiring device.
* -> STATE_ACQ (other device): by `acquire_end_core`, when there is LOCK bit for another device,
* and no BG bits are active.
* -> STATE_BG: by `acquire_end_core`, when there is LOCK bit for another device, but BG is still
* active for a different device.
* -> STATE_BG: by `acquire_end_core` when there is no LOCK bit active, but there are active BG
* bits.
* -> STATE_IDLE: by `acquire_end_core` when there is no LOCK bit, nor BG bit active.
@@ -388,19 +392,22 @@ SPI_BUS_LOCK_ISR_ATTR static inline bool acquire_core(spi_bus_lock_dev_t *dev_ha
/**
* Find the next acquiring processor according to the status. Will directly change
* the acquiring device if new one found.
* the acquiring device if the BG can yield to the lock owner, or if BG is active for the
* lock owner.
*
* Cases:
* - BG should still be the acquiring processor (Return false):
* 1. Acquiring device has active BG bits: out_desired_dev = new acquiring device
* 2. No acquiring device, but BG active: out_desired_dev = randomly pick one device with active BG bits
* 2. A new acquiring device exists, but BG is still active for another device:
* out_desired_dev = that BG-active device
* 3. No acquiring device, but BG active: out_desired_dev = randomly pick one device with active BG bits
* - BG should yield to the task (Return true):
* 3. Acquiring device has no active BG bits: out_desired_dev = new acquiring device
* 4. No acquiring device while no active BG bits: out_desired_dev=NULL
* 4. Acquiring device has no active BG bits: out_desired_dev = new acquiring device
* 5. No acquiring device while no active BG bits: out_desired_dev=NULL
*
* Acquiring device task need to be resumed only when case 3.
* Acquiring device task needs to be resumed only when case 4.
*
* This scheduling can happen in either task or ISR, so `in_isr` or `bg_active` not touched.
* This scheduling can happen in either task or ISR, so `in_isr` is not touched.
*
* @param lock
* @param status Current status
@@ -419,12 +426,26 @@ schedule_core(spi_bus_lock_t *lock, uint32_t status, spi_bus_lock_dev_t **out_de
bool bg_yield;
if (lock_bits) {
int dev_id = mask_get_id(lock_bits);
desired_dev = (spi_bus_lock_dev_t *)atomic_load(&lock->dev[dev_id]);
BUS_LOCK_DEBUG_EXECUTE_CHECK(desired_dev);
spi_bus_lock_dev_t *lock_dev = (spi_bus_lock_dev_t *)atomic_load(&lock->dev[dev_id]);
BUS_LOCK_DEBUG_EXECUTE_CHECK(lock_dev);
lock->acquiring_dev = desired_dev;
bg_yield = ((bg_bits & desired_dev->mask) == 0);
lock->acq_dev_bg_active = !bg_yield;
if (bg_bits && ((bg_bits & lock_dev->mask) == 0)) {
int bg_dev_id = mask_get_id(bg_bits);
desired_dev = (spi_bus_lock_dev_t *)atomic_load(&lock->dev[bg_dev_id]);
BUS_LOCK_DEBUG_EXECUTE_CHECK(desired_dev);
// Keep ISR/BG owning the bus until the previous device's in-flight
// interrupt transactions are fully finished. The new lock owner will
// be resumed by a later schedule once BG bits are cleared.
lock->acquiring_dev = NULL;
lock->acq_dev_bg_active = false;
bg_yield = false;
} else {
desired_dev = lock_dev;
lock->acquiring_dev = desired_dev;
bg_yield = ((bg_bits & desired_dev->mask) == 0);
lock->acq_dev_bg_active = !bg_yield;
}
} else {
lock->acq_dev_bg_active = false;
if (bg_bits) {
@@ -532,7 +553,7 @@ SPI_BUS_LOCK_ISR_ATTR static inline bool bg_entry_core(spi_bus_lock_t *lock)
// Handle the conditions of status and interrupt, avoiding the ISR being disabled when there is any new coming BG requests.
// When called with `wip=true`, means the ISR is performing some operations. Will enable the interrupt again and exit unconditionally.
// When called with `wip=false`, will only return `true` when there is no coming BG request. If return value is `false`, the ISR should try again.
// Will not change acquiring device.
// May change acquiring device when BG has finished and there is a pending LOCK bit.
SPI_BUS_LOCK_ISR_ATTR static inline bool bg_exit_core(spi_bus_lock_t *lock, bool wip, BaseType_t *do_yield)
{
//See comments in `bg_entry_core`, re-enable interrupt disabled in entry if we do need the interrupt
@@ -556,7 +577,20 @@ SPI_BUS_LOCK_ISR_ATTR static inline bool bg_exit_core(spi_bus_lock_t *lock, bool
}
} else {
BUS_LOCK_DEBUG_EXECUTE_CHECK(!lock->acq_dev_bg_active);
ret = !(status & BG_MASK);
if (status & BG_MASK) {
ret = false;
} else if (status & LOCK_MASK) {
spi_bus_lock_dev_t *desired_dev = NULL;
bool bg_yield = schedule_core(lock, status, &desired_dev);
// A waiting lock owner must be selected once BG is fully finished.
BUS_LOCK_DEBUG_EXECUTE_CHECK(bg_yield);
BUS_LOCK_DEBUG_EXECUTE_CHECK(desired_dev);
BUS_LOCK_DEBUG_EXECUTE_CHECK(lock->acquiring_dev == desired_dev);
resume_dev_in_isr(lock->acquiring_dev, do_yield);
ret = true;
} else {
ret = true;
}
}
if (ret) {
//when successfully exit, but no transaction done, mark BG as inactive