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fix(driver): fix drivers clock management

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This commit is contained in:
wuzhenghui
2026-09-02 19:20:14 +08:00
parent f9428ecc1e
commit 0b7f047e9e
7 changed files with 82 additions and 3 deletions
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components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
+16
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@@ -66,6 +66,7 @@ typedef struct dvp_platform {
static dvp_platform_t s_platform;
static const char *TAG = "dvp_cam";
static soc_module_clk_t s_dvp_clk_src[CAP_DVP_PERIPH_NUM];
/**
* @brief Claim DVP controller
@@ -346,6 +347,11 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e
esp_rom_gpio_connect_out_signal(pin->xclk_io, cam_periph_signals.buses[ctlr_id].clk_sig, false, false);
}
#if CONFIG_IDF_TARGET_ESP32S31
// PLL 120M was selected in esp_perip_clk_init on esp32s31.
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, true));
#endif
PERIPH_RCC_ACQUIRE_ATOMIC(cam_periph_signals.buses[ctlr_id].module, ref_count) {
if (ref_count == 0) {
cam_ll_enable_bus_clock(ctlr_id, true);
@@ -354,6 +360,7 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e
}
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true));
s_dvp_clk_src[ctlr_id] = (soc_module_clk_t)clk_src;
PERIPH_RCC_ATOMIC() {
cam_ll_enable_clk(ctlr_id, true);
cam_ll_select_clk_src(ctlr_id, clk_src);
@@ -458,6 +465,15 @@ esp_err_t esp_cam_ctlr_dvp_deinit(int ctlr_id)
}
}
if (s_dvp_clk_src[ctlr_id]) {
esp_clk_tree_enable_src(s_dvp_clk_src[ctlr_id], false);
s_dvp_clk_src[ctlr_id] = 0;
}
#if CONFIG_IDF_TARGET_ESP32S31
esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, false);
#endif
return ESP_OK;
}