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feat(soc): support esp32s31 lp_aon & rtc_wdt & rtc_timer
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "hal/lp_sys_ll.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define lp_aon_hal_inform_wakeup_type(dslp) lp_sys_ll_inform_wakeup_type(dslp)
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,66 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-S31 LP_SYS register operations
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#pragma once
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#include <stdlib.h>
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#include "esp_attr.h"
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#include "soc/soc.h"
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#include "soc/lp_system_struct.h"
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#include "hal/misc.h"
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#include "esp32s31/rom/rtc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ROM obtains the wake-up type through LP_SYS_STORE9_REG[0].
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* Set the flag to inform
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* @param true: deepsleep false: lightsleep
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*/
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FORCE_INLINE_ATTR void lp_sys_ll_inform_wakeup_type(bool dslp)
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{
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if (dslp) {
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REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
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} else {
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REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
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}
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}
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FORCE_INLINE_ATTR void lp_sys_ll_set_pau_aon_bypass(bool bypass)
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{
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LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0;
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}
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FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout)
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{
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LP_SYS.backup_dma_cfg1.link_wait_tout_thres_aon = tout;
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LP_SYS.backup_dma_cfg1.link_work_tout_thres_aon = tout;
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}
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FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_backup_tout_thres(uint32_t tout)
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{
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LP_SYS.backup_dma_cfg0.link_backup_tout_thres_aon = tout;
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}
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FORCE_INLINE_ATTR void lp_sys_ll_set_pau_reg_read_interval(uint32_t val)
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{
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LP_SYS.backup_dma_cfg0.read_interval_aon = val;
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}
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FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_addr(uint32_t addr)
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{
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LP_SYS.backup_dma_cfg2.link_addr_aon = addr;
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}
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#ifdef __cplusplus
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}
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#endif
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