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fix(driver_spi): fixed master dma unaligned trans error
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@@ -891,6 +891,37 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
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TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK);
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}
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#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE // targets who need cache sync don't support unaligned trans
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TEST_CASE("SPI Master DMA manually unaligned RX test", "[spi]")
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{
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spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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buscfg.miso_io_num = buscfg.mosi_io_num;
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
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spi_device_handle_t dev0;
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spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &dev0));
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WORD_ALIGNED_ATTR uint8_t tx_data[8] = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88};
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WORD_ALIGNED_ATTR uint8_t rx_data[8] = {0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA};
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spi_transaction_t trans_cfg = {
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.tx_buffer = tx_data,
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.rx_buffer = rx_data,
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.length = 5 * 8,
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.flags = SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL,
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};
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printf("Sending %d bytes\n", trans_cfg.length / 8);
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TEST_ESP_OK(spi_device_transmit(dev0, &trans_cfg));
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ESP_LOG_BUFFER_HEX("rx", rx_data, 8);
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#if !SOC_IS(ESP32)
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TEST_ASSERT_EQUAL(rx_data[6], 0xAA);
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#endif
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TEST_ESP_OK(spi_bus_remove_device(dev0));
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TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
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}
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#endif
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#if (TEST_SPI_PERIPH_NUM >= 2)
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//These will only be enabled on chips with 2 or more SPI peripherals
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