feat(panic): panic immediatly if trying to write to flash through cache on ESP32-S3

Updated S3 to use PMS protection for writing to flash through cache. This means we get a panic quicker for this illegal behavior than we did before, making the source of the error easier to track down.
2026-10-02 11:10:54 +03:00 · 2024-12-27 17:58:33 +08:00
parent f8ddcee8cd
commit 096cb409d9
12 changed files with 244 additions and 57 deletions
@@ -752,6 +752,23 @@ static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_
    return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask);
 }

+/**
+ * @brief Read vaddr that caused acs dbus reject error
+ *
+ * @param cache_id cache id to get vaddr from
+ *
+ * @return vaddr that cause the acs dbus reject error
+ */
+__attribute__((always_inline))
+static inline uint32_t cache_ll_get_acs_dbus_reject_vaddr(uint32_t cache_id)
+{
+    if (cache_id == 0) {
+        return REG_READ(EXTMEM_CORE0_DBUS_REJECT_VADDR_REG);
+    } else {
+        return REG_READ(EXTMEM_CORE1_DBUS_REJECT_VADDR_REG);
+    }
+}
+
 #ifdef __cplusplus
 }
 #endif
@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/syscon_struct.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  flash access control config struct
+ */
+typedef union {
+    uint32_t val;
+    struct {
+        uint32_t sec_x: 1;  // Secure world cache execute access
+        uint32_t sec_r: 1;  // Secure world cache read access
+        uint32_t sec_w: 1;  // Secure world cache write access
+        uint32_t nsec_x: 1; // Non-secure world cache execute access
+        uint32_t nsec_r: 1; // Non-secure world cache execute read
+        uint32_t nsec_w: 1; // Non-secure world cache execute write
+        uint32_t spi1_r: 1; // SPI1 read access
+        uint32_t spi1_w: 1; // SPI1 write access
+    };
+} mspi_ll_flash_ace_ctrl_t;
+
+/**
+ * @brief Set PMS flash protection start address
+ *
+ * @param region  PMS region id (0~3)
+ * @param address Starting address
+ *
+ */
+__attribute__((always_inline))
+static inline void mspi_ll_set_flash_protection_addr(uint32_t region, uint32_t address)
+{
+    switch(region){
+        case 0:
+            SYSCON.flash_ace0_addr = address;
+            break;
+        case 1:
+            SYSCON.flash_ace1_addr = address;
+            break;
+        case 2:
+            SYSCON.flash_ace2_addr = address;
+            break;
+        case 3:
+            SYSCON.flash_ace3_addr = address;
+            break;
+        default:
+            HAL_ASSERT(false);
+    }
+}
+
+/**
+ * @brief Set PMS flash protection size
+ *
+ * @param region  PMS region id (0~3)
+ * @param size    Size, in number of 64kB pages
+ *
+ */
+__attribute__((always_inline))
+static inline void mspi_ll_set_flash_protection_size(uint32_t region, uint32_t size)
+{
+    switch(region){
+        case 0:
+            SYSCON.flash_ace0_size.flash_ace0_size = size;
+            break;
+        case 1:
+            SYSCON.flash_ace1_size.flash_ace1_size = size;
+            break;
+        case 2:
+            SYSCON.flash_ace2_size.flash_ace2_size = size;
+            break;
+        case 3:
+            SYSCON.flash_ace3_size.flash_ace3_size = size;
+            break;
+        default:
+            HAL_ASSERT(false);
+    }
+}
+
+/**
+ * @brief Set PMS flash protection access ctrl bits
+ *
+ * @param region  PMS region id (0~3)
+ * @param address ctrl bits, RWX per mode
+ *
+ */
+__attribute__((always_inline))
+static inline void mspi_ll_set_flash_protection_access(uint32_t region, mspi_ll_flash_ace_ctrl_t ctrl)
+{
+    switch(region){
+        case 0:
+            SYSCON.flash_ace0_attr.flash_ace0_attr = ctrl.val;
+            break;
+        case 1:
+            SYSCON.flash_ace1_attr.flash_ace1_attr = ctrl.val;
+            break;
+        case 2:
+            SYSCON.flash_ace2_attr.flash_ace2_attr = ctrl.val;
+            break;
+        case 3:
+            SYSCON.flash_ace3_attr.flash_ace3_attr = ctrl.val;
+            break;
+        default:
+            HAL_ASSERT(false);
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif