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Merge branch 'fix/core_system_fixes_for_p4_eco5_v6_0' into 'release/v6.0'

Browse Source 
Core System fixes for p4 eco5 (v6.0)

See merge request espressif/esp-idf!43629
This commit is contained in:
Roland Dobai
2025-11-27 10:15:03 +01:00
parent 88c6d19ad2 84dec0fe39
commit 093c5f0b01
45 changed files with 77 additions and 225 deletions
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components/cxx/test_apps/.build-test-rules.yml
-4
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@@ -5,7 +5,3 @@ components/cxx/test_apps:
- if: IDF_TARGET in ["esp32", "esp32c3", "esp32c61", "esp32p4"]
temporary: true
reason: the other targets are not tested yet
disable:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: p4 rev3 migration # TODO: IDF-14402
components/cxx/test_apps/exception/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 |
| ----------------- | ----- | -------- | --------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | ESP32-P4 |
| ----------------- | ----- | -------- | --------- | -------- |
components/cxx/test_apps/exception_no_except/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 |
| ----------------- | ----- | -------- | --------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | ESP32-P4 |
| ----------------- | ----- | -------- | --------- | -------- |
components/cxx/test_apps/general/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 |
| ----------------- | ----- | -------- | --------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | ESP32-P4 |
| ----------------- | ----- | -------- | --------- | -------- |
components/cxx/test_apps/rtti/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 |
| ----------------- | ----- | -------- | --------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | ESP32-P4 |
| ----------------- | ----- | -------- | --------- | -------- |
components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
+4 -4
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@@ -308,17 +308,17 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
#endif
#if SOC_EFUSE_ECDSA_KEY_P192
#if SOC_EFUSE_ECDSA_KEY_P192 || EFUSE_LL_HAS_ECDSA_KEY_P192
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
#endif
#if SOC_EFUSE_ECDSA_KEY_P384
#if SOC_EFUSE_ECDSA_KEY_P384 || EFUSE_LL_HAS_ECDSA_KEY_P384
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
#endif
#if SOC_PSRAM_ENCRYPTION_XTS_AES_128
#if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
#endif
#if SOC_PSRAM_ENCRYPTION_XTS_AES_256
#if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
#endif
components/efuse/test_apps/.build-test-rules.yml
-4
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@@ -3,10 +3,6 @@
components/efuse/test_apps:
enable:
- if: (INCLUDE_DEFAULT == 1 and SOC_EFUSE_SUPPORTED == 1) or IDF_TARGET == "linux")
disable:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: p4 rev3 migration # TODO: IDF-14403
disable_test:
- if: IDF_TARGET in ["esp32s2", "esp32s3"]
reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3.
components/efuse/test_apps/README.md
+2 -2
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@@ -1,3 +1,3 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | Linux |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | ----- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | ----- |
components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
+6 -5
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@@ -14,6 +14,7 @@
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "esp_efuse_utility.h"
#include "hal/efuse_ll.h"
#include "sdkconfig.h"
ESP_LOG_ATTR_TAG(TAG, "efuse_key_test");
@@ -93,17 +94,17 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
#endif
#if SOC_EFUSE_ECDSA_KEY_P192
#if SOC_EFUSE_ECDSA_KEY_P192 || EFUSE_LL_HAS_ECDSA_KEY_P192
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
#endif
#if SOC_EFUSE_ECDSA_KEY_P384
#if SOC_EFUSE_ECDSA_KEY_P384 || EFUSE_LL_HAS_ECDSA_KEY_P384
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
#endif
#if SOC_PSRAM_ENCRYPTION_XTS_AES_128
#if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
#endif
#if SOC_PSRAM_ENCRYPTION_XTS_AES_256
#if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
#endif
@@ -126,7 +127,7 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
TEST_ASSERT_EQUAL(purpose, esp_efuse_get_key_purpose(num_key));
esp_efuse_purpose_t purpose2 = 0;
const esp_efuse_desc_t** key_purpose = esp_efuse_get_purpose_field(num_key);
TEST_ESP_OK(esp_efuse_read_field_blob(key_purpose, &purpose2, key_purpose[0]->bit_count));
TEST_ESP_OK(esp_efuse_read_field_blob(key_purpose, &purpose2, esp_efuse_get_field_size(key_purpose)));
TEST_ASSERT_EQUAL(purpose, purpose2);
TEST_ASSERT_TRUE(esp_efuse_get_keypurpose_dis_write(num_key));
return ESP_OK;
components/esp_libc/test_apps/.build-test-rules.yml
-7
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@@ -1,7 +0,0 @@
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
components/esp_libc/test_apps/newlib:
disable_test:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: p4 rev3 migration # TODO: IDF-14415
components/esp_libc/test_apps/newlib/pytest_newlib.py
-1
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@@ -20,6 +20,5 @@ from pytest_embedded_idf.utils import idf_parametrize
],
indirect=['config', 'target'],
)
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14415')
def test_newlib(dut: Dut) -> None:
dut.run_all_single_board_cases()
components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.systimer.ld
+4 -2
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@@ -9,8 +9,10 @@
***************************************/
/* Functions */
systimer_hal_init = 0x4000039c;
systimer_hal_deinit = 0x400003a0;
/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
/* systimer_hal_init = 0x4000039c; */
/* systimer_hal_deinit = 0x400003a0; */
systimer_hal_set_tick_rate_ops = 0x400003a4;
systimer_hal_get_counter_value = 0x400003a8;
systimer_hal_get_time = 0x400003ac;
components/esp_rom/esp32h4/ld/esp32h4.rom.systimer.ld
+4 -2
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@@ -18,8 +18,10 @@
***************************************/
/* Functions */
systimer_hal_init = 0x4000036c;
systimer_hal_deinit = 0x40000370;
/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
/* systimer_hal_init = 0x4000036c; */
/* systimer_hal_deinit = 0x40000370; */
systimer_hal_set_tick_rate_ops = 0x40000374;
systimer_hal_get_counter_value = 0x40000378;
systimer_hal_get_time = 0x4000037c;
components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.ld
-22
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@@ -170,28 +170,6 @@ rom_spiflash_legacy_data = 0x4ffbffe8;
g_flash_guard_ops = 0x4ffbfff0;
/***************************************
Group hal_systimer
***************************************/
/* Functions */
systimer_hal_init = 0x4fc00228;
systimer_hal_deinit = 0x4fc0022c;
systimer_hal_set_tick_rate_ops = 0x4fc00230;
systimer_hal_get_counter_value = 0x4fc00234;
systimer_hal_get_time = 0x4fc00238;
systimer_hal_set_alarm_target = 0x4fc0023c;
systimer_hal_set_alarm_period = 0x4fc00240;
systimer_hal_get_alarm_value = 0x4fc00244;
systimer_hal_enable_alarm_int = 0x4fc00248;
systimer_hal_on_apb_freq_update = 0x4fc0024c;
systimer_hal_counter_value_advance = 0x4fc00250;
systimer_hal_enable_counter = 0x4fc00254;
systimer_hal_select_alarm_mode = 0x4fc00258;
systimer_hal_connect_alarm_counter = 0x4fc0025c;
systimer_hal_counter_can_stall_by_cpu = 0x4fc00260;
/***************************************
Group cache
***************************************/
components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.newlib.ld
+3 -61
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@@ -10,7 +10,9 @@
*
* Compatible with ROM where ECO version equal or greater to 5.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
* THIS FILE WAS AUTOMATICALLY GENERATED. !!! BUT EDITED !!!
* The file was originally generated for use with newlib, but it was split into
* multiple files to make it compatible with picolibc.
*/
/***************************************
@@ -18,69 +20,12 @@
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x4fc00264;
memset = 0x4fc00268;
memcpy = 0x4fc0026c;
memmove = 0x4fc00270;
memcmp = 0x4fc00274;
strcpy = 0x4fc00278;
strncpy = 0x4fc0027c;
strcmp = 0x4fc00280;
strncmp = 0x4fc00284;
strlen = 0x4fc00288;
strstr = 0x4fc0028c;
bzero = 0x4fc00290;
_isatty_r = 0x4fc00294;
sbrk = 0x4fc00298;
isalnum = 0x4fc0029c;
isalpha = 0x4fc002a0;
isascii = 0x4fc002a4;
isblank = 0x4fc002a8;
iscntrl = 0x4fc002ac;
isdigit = 0x4fc002b0;
islower = 0x4fc002b4;
isgraph = 0x4fc002b8;
isprint = 0x4fc002bc;
ispunct = 0x4fc002c0;
isspace = 0x4fc002c4;
isupper = 0x4fc002c8;
toupper = 0x4fc002cc;
tolower = 0x4fc002d0;
toascii = 0x4fc002d4;
memccpy = 0x4fc002d8;
memchr = 0x4fc002dc;
memrchr = 0x4fc002e0;
strcasecmp = 0x4fc002e4;
strcasestr = 0x4fc002e8;
strcat = 0x4fc002ec;
strdup = 0x4fc002f0;
strchr = 0x4fc002f4;
strcspn = 0x4fc002f8;
strcoll = 0x4fc002fc;
strlcat = 0x4fc00300;
strlcpy = 0x4fc00304;
strlwr = 0x4fc00308;
strncasecmp = 0x4fc0030c;
strncat = 0x4fc00310;
strndup = 0x4fc00314;
strnlen = 0x4fc00318;
strrchr = 0x4fc0031c;
strsep = 0x4fc00320;
strspn = 0x4fc00324;
strtok_r = 0x4fc00328;
strupr = 0x4fc0032c;
longjmp = 0x4fc00330;
setjmp = 0x4fc00334;
abs = 0x4fc00338;
div = 0x4fc0033c;
labs = 0x4fc00340;
ldiv = 0x4fc00344;
qsort = 0x4fc00348;
rand_r = 0x4fc0034c;
rand = 0x4fc00350;
srand = 0x4fc00354;
utoa = 0x4fc00358;
itoa = 0x4fc0035c;
atoi = 0x4fc00360;
atol = 0x4fc00364;
strtol = 0x4fc00368;
@@ -94,6 +39,3 @@ __swhatbuf_r = 0x4fc00384;
__swbuf_r = 0x4fc00388;
__swbuf = 0x4fc0038c;
__swsetup_r = 0x4fc00390;
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x4ffbffe4;
_global_impure_ptr = 0x4ffbffe0;
components/esp_rom/test_apps/.build-test-rules.yml
-4
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@@ -10,10 +10,6 @@ components/esp_rom/test_apps/rom_impl_components:
- if: CONFIG_NAME == "rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1))
- if: CONFIG_NAME == "no_rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1))
- if: SOC_WDT_SUPPORTED != 1
disable_test:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: p4 rev3 migration # TODO: IDF-14417
components/esp_rom/test_apps/rom_tests:
disable_test:
components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py
-1
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@@ -15,6 +15,5 @@ from pytest_embedded_idf.utils import idf_parametrize
indirect=True,
)
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14417')
def test_esp_rom_impl_components(dut: Dut) -> None:
dut.run_all_single_board_cases()
components/esp_system/ld/esp32p4/memory.ld.in
-6
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@@ -32,12 +32,6 @@
#define SRAM_HIGH_END SRAM_HIGH_START + SRAM_HIGH_SIZE
#endif
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
#define MSPI_WORKAROUND_SIZE CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE
#else
#define MSPI_WORKAROUND_SIZE 0x0
#endif
#define IDROM_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 10)
#define LP_ROM_DRAM_START 0x5010fa80 // Value taken from ROM elf, includes LP ROM stack
components/esp_system/ld/esp32p4/sections.rev3.ld.in
+4 -12
View File
@@ -403,20 +403,12 @@ SECTIONS
* C++ constructor tables.
*
* Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt.
*
* RISC-V gcc is configured with --enable-initfini-array so it emits
* .init_array section instead. But the init_priority sections will be
* sorted for iteration in ascending order during startup.
* The rest of the init_array sections is sorted for iteration in descending
* order during startup, however. Hence a different section is generated for
* the init_priority functions which is iterated in ascending order during
* startup. The corresponding code can be found in startup.c.
*/
ALIGNED_SYMBOL(4, __init_priority_array_start)
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
__init_priority_array_end = ABSOLUTE(.);
ALIGNED_SYMBOL(4, __preinit_array_start)
KEEP (*(.preinit_array))
__preinit_array_end = ABSOLUTE(.);
ALIGNED_SYMBOL(4, __init_array_start)
KEEP (*(SORT_BY_INIT_PRIORITY(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)))
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
__init_array_end = ABSOLUTE(.);
components/esp_system/ld/ld.common
+6
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@@ -74,6 +74,12 @@
#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
#endif
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
#define MSPI_WORKAROUND_SIZE CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE
#else
#define MSPI_WORKAROUND_SIZE 0x0
#endif
#endif // SOC_RTC_MEM_SUPPORTED
#define QUOTED_STRING(STRING) #STRING
components/esp_timer/test_apps/.build-test-rules.yml
-4
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@@ -4,7 +4,3 @@ components/esp_timer/test_apps:
disable:
- if: CONFIG_NAME == "dfs" and SOC_CLK_XTAL32K_SUPPORTED != 1
reason: The test requires the XTAL32K clock to measure the esp_timer timing accuracy
disable_test:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: p4 rev3 migration # TODO: IDF-14420
components/esp_timer/test_apps/pytest_esp_timer_ut.py
-2
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@@ -22,7 +22,6 @@ from pytest_embedded_idf.utils import idf_parametrize
],
indirect=['config', 'target'],
)
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420')
def test_esp_timer(dut: Dut) -> None:
dut.run_all_single_board_cases(timeout=120)
@@ -37,7 +36,6 @@ def test_esp_timer(dut: Dut) -> None:
indirect=True,
)
@idf_parametrize('target', ['esp32'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420')
def test_esp_timer_psram(dut: Dut) -> None:
dut.run_all_single_board_cases(timeout=120)
components/hal/esp32p4/include/hal/cpu_utility_ll.h
+4 -2
View File
@@ -33,11 +33,13 @@ FORCE_INLINE_ATTR void cpu_utility_ll_stall_cpu(uint32_t cpu_no)
{
if (cpu_no == 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore0_stall_code, 0x86);
while(!REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore1_stall_code, 0x86);
while(!REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST));
}
// We do not check stalled status here because
// it will not be set if the stalled core was in WFI when the stall happens, thus any check
// is unreliable.
// TODO: when ECO6 fixes this we can add back a check here
}
FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
components/hal/esp32p4/include/hal/efuse_ll.h
+20 -1
View File
@@ -11,6 +11,7 @@
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -25,6 +26,25 @@ typedef enum {
EFUSE_CONTROLLER_STATE_READ_RS_BLK = 5, ///< efuse_controllerid is on reading RS block state.
} efuse_controller_state_t;
/* Revision-aware eFuse feature macros
*
* These macros indicate whether an eFuse feature is available given the
* configured minimum supported chip revision (HAL_CONFIG(CHIP_SUPPORT_MIN_REV)).
* Use them when a feature's presence depends on the chosen minimum revision.
*
* Note: SOC_* capability macros describe silicon capabilities; these
* EFUSE_LL_HAS_* macros reflect availability relative to the configured min revision.
* If a feature is present in silicon and does not depend on the chip revision,
* then add SOC_* macro in soc_caps.h instead.
*/
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
// Rev 3.00+: key_purpose fields expanded from 4 to 5 bits, enabling additional key types.
#define EFUSE_LL_HAS_ECDSA_KEY_P192 (1)
#define EFUSE_LL_HAS_ECDSA_KEY_P384 (1)
#define EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128 (1)
#define EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256 (1)
#endif
// Always inline these functions even no gcc optimization is applied.
/******************* eFuse fields *************************/
@@ -91,7 +111,6 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(
return EFUSE.rd_mac_sys_2.pkg_version;
}
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -595,6 +595,10 @@ config SOC_CPU_HAS_ZC_EXTENSIONS
bool
default y
config SOC_CPU_ZCMP_WORKAROUND
bool
default y
config SOC_CPU_ZCMP_PUSH_REVERSED
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+2
View File
@@ -211,6 +211,7 @@
#define SOC_CPU_HAS_ZC_EXTENSIONS 1
#define SOC_CPU_ZCMP_WORKAROUND 1
#define SOC_CPU_ZCMP_PUSH_REVERSED 1
#define SOC_CPU_ZCMP_POPRET_ISSUE 1
@@ -665,6 +666,7 @@
#define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 /* SOC_EFUSE_XTS_AES_KEY_128 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 (1) */
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 /* SOC_EFUSE_XTS_AES_KEY_256 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 (1) */
/*-------------------------- MEMPROT CAPS ------------------------------------*/
/*-------------------------- UART CAPS ---------------------------------------*/
components/ulp/ld/lp_core_riscv.ld
+3 -1
View File
@@ -9,11 +9,13 @@
#if CONFIG_ESP_ROM_HAS_LP_ROM
/* With LP-ROM memory layout is different due to LP ROM stack/data */
#define ULP_MEM_START_ADDRESS SOC_RTC_DRAM_LOW + RESERVE_RTC_MEM
/* For P4 ECO5 we also reserve some RTC MEM at the first for MSPI workaround */
#define ULP_MEM_START_ADDRESS SOC_RTC_DRAM_LOW + RESERVE_RTC_MEM + MSPI_WORKAROUND_SIZE
#else
#define ULP_MEM_START_ADDRESS (SOC_RTC_DRAM_LOW)
#endif
#define ALIGN_DOWN(SIZE, AL) (SIZE & ~(AL - 1))
/* Ensure the end where the shared memory starts is aligned to 8 bytes
if updating this also update the same in ulp_lp_core_memory_shared.c
components/ulp/test_apps/.build-test-rules.yml
-7
View File
@@ -5,17 +5,10 @@ components/ulp/test_apps/lp_core/lp_core_basic_tests:
- if: SOC_LP_CORE_SUPPORTED != 1
- if: CONFIG_NAME == "xtal" and SOC_CLK_LP_FAST_SUPPORT_XTAL != 1
- if: CONFIG_NAME == "lp_vad" and SOC_LP_VAD_SUPPORTED != 1
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: p4 rev3 migration # TODO: IDF-14368
components/ulp/test_apps/lp_core/lp_core_hp_uart:
disable:
- if: SOC_LP_CORE_SUPPORTED != 1
disable_test:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: p4 rev3 migration # TODO: IDF-14422
components/ulp/test_apps/ulp_fsm:
enable:
components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md
+2 -2
View File
@@ -1,3 +1,3 @@
| Supported Targets | ESP32-C5 | ESP32-C6 |
| ----------------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- |
components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py
-4
View File
@@ -8,7 +8,6 @@ from pytest_embedded_idf.utils import soc_filtered_targets
@pytest.mark.generic
@idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422')
def test_lp_core_hp_uart_print(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('"lp-print can output to hp-uart"')
@@ -19,7 +18,6 @@ def test_lp_core_hp_uart_print(dut: Dut) -> None:
@pytest.mark.generic
@idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422')
def test_lp_core_panic(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('"LP-Core panic"')
@@ -31,7 +29,6 @@ def test_lp_core_panic(dut: Dut) -> None:
@pytest.mark.generic
@idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422')
def test_lp_core_shared_mem(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('"LP-Core Shared-mem"')
@@ -50,7 +47,6 @@ def test_lp_core_shared_mem(dut: Dut) -> None:
@pytest.mark.generic
@idf_parametrize('target', ['esp32p4'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422')
def test_lp_core_lp_rom(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('"LP-Core LP-ROM"')