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Merge branch 'fix/fix_s31_modem_clock_link_bad_retention' into 'master'

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fix(esp_hw_support): wait pll ready before modem clock retention on s31

See merge request espressif/esp-idf!52015
This commit is contained in:
Jiang Jiang Jian
2026-09-16 12:06:29 +08:00
parent 3fd0b94ea2 69b860b6b8
commit 0925b1c79a
9 changed files with 217 additions and 160 deletions
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components/soc/esp32s31/include/soc/retention_periph_defs.h
+56 -54
View File
@@ -15,76 +15,78 @@ extern "C" {
typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_MIN = 0,
SLEEP_RETENTION_MODULE_NULL = 1, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */
/* PLL source (I2C master clock + SYSPLL self-calibration) */
SLEEP_RETENTION_MODULE_PLL_SOURCE = 2,
/* clock module, which includes system and modem */
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 2,
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 3,
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
* TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
SLEEP_RETENTION_MODULE_SYS_PERIPH = 3,
SLEEP_RETENTION_MODULE_SYS_PERIPH = 4,
/* Timer Group by target*/
SLEEP_RETENTION_MODULE_TG0_WDT = 4,
SLEEP_RETENTION_MODULE_TG1_WDT = 5,
SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6,
SLEEP_RETENTION_MODULE_TG0_TIMER1 = 7,
SLEEP_RETENTION_MODULE_TG1_TIMER0 = 8,
SLEEP_RETENTION_MODULE_TG1_TIMER1 = 9,
SLEEP_RETENTION_MODULE_TG0_WDT = 5,
SLEEP_RETENTION_MODULE_TG1_WDT = 6,
SLEEP_RETENTION_MODULE_TG0_TIMER0 = 7,
SLEEP_RETENTION_MODULE_TG0_TIMER1 = 8,
SLEEP_RETENTION_MODULE_TG1_TIMER0 = 9,
SLEEP_RETENTION_MODULE_TG1_TIMER1 = 10,
/* AHB_DMA by channel */
SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 10,
SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 11,
SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 12,
SLEEP_RETENTION_MODULE_AHB_DMA_CH3 = 13,
SLEEP_RETENTION_MODULE_AHB_DMA_CH4 = 14,
SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 11,
SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 12,
SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 13,
SLEEP_RETENTION_MODULE_AHB_DMA_CH3 = 14,
SLEEP_RETENTION_MODULE_AHB_DMA_CH4 = 15,
/* AXI_DMA by channel */
SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 15,
SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 16,
SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 17,
SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 16,
SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 17,
SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 18,
/* LP_AHB_DMA by channel */
SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0 = 18,
SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1 = 19,
SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0 = 19,
SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1 = 20,
/* MISC Peripherals */
SLEEP_RETENTION_MODULE_UART0 = 20,
SLEEP_RETENTION_MODULE_UART1 = 21,
SLEEP_RETENTION_MODULE_UART2 = 22,
SLEEP_RETENTION_MODULE_UART3 = 23,
SLEEP_RETENTION_MODULE_RMT0 = 24,
SLEEP_RETENTION_MODULE_I2S0 = 25,
SLEEP_RETENTION_MODULE_I2S1 = 26,
SLEEP_RETENTION_MODULE_I2C0 = 27,
SLEEP_RETENTION_MODULE_I2C1 = 28,
SLEEP_RETENTION_MODULE_ETM0 = 29,
SLEEP_RETENTION_MODULE_TWAI0 = 30,
SLEEP_RETENTION_MODULE_TWAI1 = 31,
SLEEP_RETENTION_MODULE_PARLIO0 = 32,
SLEEP_RETENTION_MODULE_GPSPI2 = 33,
SLEEP_RETENTION_MODULE_GPSPI3 = 34,
SLEEP_RETENTION_MODULE_LEDC0 = 35,
SLEEP_RETENTION_MODULE_LEDC1 = 36,
SLEEP_RETENTION_MODULE_MCPWM0 = 37,
SLEEP_RETENTION_MODULE_MCPWM1 = 38,
SLEEP_RETENTION_MODULE_MCPWM2 = 39,
SLEEP_RETENTION_MODULE_MCPWM3 = 40,
SLEEP_RETENTION_MODULE_SDM0 = 41,
SLEEP_RETENTION_MODULE_LCDCAM = 42,
SLEEP_RETENTION_MODULE_JPEG = 43,
SLEEP_RETENTION_MODULE_DMA2D = 44,
SLEEP_RETENTION_MODULE_PPA = 45,
SLEEP_RETENTION_MODULE_UART0 = 21,
SLEEP_RETENTION_MODULE_UART1 = 22,
SLEEP_RETENTION_MODULE_UART2 = 23,
SLEEP_RETENTION_MODULE_UART3 = 24,
SLEEP_RETENTION_MODULE_RMT0 = 25,
SLEEP_RETENTION_MODULE_I2S0 = 26,
SLEEP_RETENTION_MODULE_I2S1 = 27,
SLEEP_RETENTION_MODULE_I2C0 = 28,
SLEEP_RETENTION_MODULE_I2C1 = 29,
SLEEP_RETENTION_MODULE_ETM0 = 30,
SLEEP_RETENTION_MODULE_TWAI0 = 31,
SLEEP_RETENTION_MODULE_TWAI1 = 32,
SLEEP_RETENTION_MODULE_PARLIO0 = 33,
SLEEP_RETENTION_MODULE_GPSPI2 = 34,
SLEEP_RETENTION_MODULE_GPSPI3 = 35,
SLEEP_RETENTION_MODULE_LEDC0 = 36,
SLEEP_RETENTION_MODULE_LEDC1 = 37,
SLEEP_RETENTION_MODULE_MCPWM0 = 38,
SLEEP_RETENTION_MODULE_MCPWM1 = 39,
SLEEP_RETENTION_MODULE_MCPWM2 = 40,
SLEEP_RETENTION_MODULE_MCPWM3 = 41,
SLEEP_RETENTION_MODULE_SDM0 = 42,
SLEEP_RETENTION_MODULE_LCDCAM = 43,
SLEEP_RETENTION_MODULE_JPEG = 44,
SLEEP_RETENTION_MODULE_DMA2D = 45,
SLEEP_RETENTION_MODULE_PPA = 46,
/* Modem module, which includes WiFi, BLE and 802.15.4 */
SLEEP_RETENTION_MODULE_WIFI_MAC = 46,
SLEEP_RETENTION_MODULE_WIFI_BB = 47,
SLEEP_RETENTION_MODULE_BLE_MAC = 48,
SLEEP_RETENTION_MODULE_BT_BB = 49,
SLEEP_RETENTION_MODULE_802154_MAC = 50,
SLEEP_RETENTION_MODULE_CLOCK_MODEM = 51,
SLEEP_RETENTION_MODULE_MODEM_PHY = 52,
SLEEP_RETENTION_MODULE_PHY_FE = 53,
SLEEP_RETENTION_MODULE_WIFI_MAC = 47,
SLEEP_RETENTION_MODULE_WIFI_BB = 48,
SLEEP_RETENTION_MODULE_BLE_MAC = 49,
SLEEP_RETENTION_MODULE_BT_BB = 50,
SLEEP_RETENTION_MODULE_802154_MAC = 51,
SLEEP_RETENTION_MODULE_CLOCK_MODEM = 52,
SLEEP_RETENTION_MODULE_MODEM_PHY = 53,
SLEEP_RETENTION_MODULE_PHY_FE = 54,
SLEEP_RETENTION_MODULE_ASRC = 53,
SLEEP_RETENTION_MODULE_ASRC = 55,
SLEEP_RETENTION_MODULE_MAX,
} periph_retention_module_t;
#define is_top_domain_module(m) ((m >= SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) && ((m <= SLEEP_RETENTION_MODULE_PPA)))
#define is_top_domain_module(m) ((m >= SLEEP_RETENTION_MODULE_PLL_SOURCE) && ((m <= SLEEP_RETENTION_MODULE_PPA)))
#ifdef __cplusplus
}
components/soc/include/soc/regdma.h
+5 -3
View File
@@ -37,6 +37,7 @@ extern "C" {
#define REGDMA_MODEMLPCON_LINK(_pri) ((0x03 << 8) | _pri)
#define REGDMA_PAU_LINK(_pri) ((0x04 << 8) | _pri)
#define REGDMA_PVT_LINK(_pri) ((0x05 << 8) | _pri)
#define REGDMA_PLL_LINK(_pri) ((0x06 << 8) | _pri)
#define REGDMA_CACHE_LINK(_pri) ((0x0c << 8) | _pri)
#define REGDMA_INTMTX_LINK(_pri) ((0x0d << 8) | _pri)
@@ -79,9 +80,10 @@ extern "C" {
#define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri)
#define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_0
#define REGDMA_LINK_PRI_MODEM_CLK REGDMA_LINK_PRI_1
#define REGDMA_LINK_PRI_CLOCK_ICG REGDMA_LINK_PRI_1
#define REGDMA_LINK_PRI_PLL_SOURCE REGDMA_LINK_PRI_0
#define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_1
#define REGDMA_LINK_PRI_MODEM_CLK REGDMA_LINK_PRI_2
#define REGDMA_LINK_PRI_CLOCK_ICG REGDMA_LINK_PRI_2
#define REGDMA_LINK_PRI_CRITICAL_TEE_APM REGDMA_LINK_PRI_2
#define REGDMA_LINK_PRI_WIFI_MAC_BB REGDMA_LINK_PRI_3
#define REGDMA_LINK_PRI_NON_CRITICAL_TEE_APM REGDMA_LINK_PRI_4