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fix(iwdt): increased default timeout if using PSRAM

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Default timeout for interrupt WDT was increased by default
on ESP32, due to some heap integrity check APIs taking a long
time on large PSRAMs and causing timeouts.

But this adjustment was only done for ESP32, not later chips,
even though they may experience the same issue.

Adjusted to have the same behavior on all chips with PSRAM
enabled, making it consistant with the docs.

Closes https://github.com/espressif/esp-idf/issues/18360
This commit is contained in:
Marius Vikhammer
2026-06-29 10:31:38 +08:00
parent f83bc1cdb2
commit 08c4e54ec5
3 changed files with 10 additions and 6 deletions
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docs/en/api-reference/system/wdts.rst
+4 -2
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@@ -68,8 +68,10 @@ Configuration
- The IWDT is enabled by default via the :ref:`CONFIG_ESP_INT_WDT` option.
- The IWDT's timeout is configured by setting the :ref:`CONFIG_ESP_INT_WDT_TIMEOUT_MS` option.
- Note that the default timeout is higher if PSRAM support is enabled, as a critical section or interrupt routine that accesses a large amount of PSRAM takes longer to complete in some circumstances.
- The timeout should always at least twice longer than the period between FreeRTOS ticks (see :ref:`CONFIG_FREERTOS_HZ`).
.. list::
:SOC_SPIRAM_SUPPORTED: - Note that the default timeout is higher if PSRAM support is enabled, as a critical section or interrupt routine that accesses a large amount of PSRAM takes longer to complete in some circumstances.
- The configured timeout duration for IWDT should always be at least twice longer than the period between two FreeRTOS ticks, e.g., if two FreeRTOS ticks occur 10 ms apart, then IWDT timeout duration should at least be more than 20 ms (see :ref:`CONFIG_FREERTOS_HZ`).
Tuning
^^^^^^