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Merge branch 'fix/esp32c5_usj_console_stuck_v6.0' into 'release/v6.0'

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fix(esp32c5): Do not disable UART0 sclk when USB Serial/JTAG is primary console (v6.0)

See merge request espressif/esp-idf!48874
This commit is contained in:
Jiang Jiang Jian
2026-06-29 15:32:15 +08:00
parent b84f9a72b5 f49e195afc
commit 0855c331d7
4 changed files with 26 additions and 8 deletions
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components/esp_system/port/soc/esp32c5/clk.c
+10
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@@ -251,5 +251,15 @@ __attribute__((weak)) void esp_perip_clk_init(void)
clk_gate_config.disable_pvt_clk = true;
#endif
#if defined(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG) && CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
/* ESP32-C5 rev <= 1.0: Do not disable UART0 sclk when USB Serial/JTAG is primary console.
* Disabling it would cause the chip to end in infinite loop on reset (workaround for rom code issue).
* See: IDFGH-17050
*/
if (efuse_hal_chip_revision() <= 100) {
clk_gate_config.disable_uart0_clk = false;
}
#endif
periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config);
}