test(drivers): run flash encryption apps on real hardware

Replace the virtual efuse flash-encryption flow in parlio, rmt, and lcd test apps with real-device flash_enc configs so CI can validate the same path used on encryption runners.
2026-09-22 13:01:16 +03:00 · 2026-07-08 19:04:04 +08:00
parent e1b1969b8a
commit 08346e011a
45 changed files with 252 additions and 545 deletions
--- a/components/esp_driver_dma/src/gdma.c
+++ b/components/esp_driver_dma/src/gdma.c
@@ -484,6 +484,16 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
        ext_mem_alignment = BIT(31);
    }

+#if CONFIG_IDF_TARGET_ESP32S31 && SOC_HAS(LP_AHB_GDMA)
+    // ESP32-S31 LP AHB GDMA can't burst-access encrypted external memory.
+    // Keep configuration/installation permissive for callers that only intend to
+    // use internal buffers, but poison the external-memory alignment so any
+    // later PSRAM use fails the caller-side validation.
+    if (config->access_ext_mem && group->bus_id == SOC_GDMA_BUS_LP && esp_efuse_is_flash_encryption_enabled()) {
+        ext_mem_alignment = BIT(31);
+    }
+#endif
+
    dma_chan->int_mem_alignment = int_mem_alignment;
    dma_chan->ext_mem_alignment = ext_mem_alignment;
    return ESP_OK;
--- a/components/esp_driver_dma/src/gdma_priv.h
+++ b/components/esp_driver_dma/src/gdma_priv.h
@@ -41,7 +41,7 @@
 #if CI_TEST_SW_RETENTION
 #define GDMA_RETENTION_ENTRY    REGDMA_SW_TRIGGER_ENTRY
 #else
-#if SOC_PHY_SUPPORTED
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
 #define GDMA_RETENTION_ENTRY    (ENTRY(0) | ENTRY(2))
 #else
 #define GDMA_RETENTION_ENTRY    (ENTRY(0))
--- a/components/esp_driver_dma/test_apps/dma/main/gdma_test_utils.h
+++ b/components/esp_driver_dma/test_apps/dma/main/gdma_test_utils.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -7,8 +7,18 @@
 #pragma once

 #include <stdbool.h>
+#include "sdkconfig.h"
 #include "esp_private/gdma.h"

+#if CONFIG_IDF_TARGET_ESP32S31
+// ESP32-S31 LP AHB GDMA can't burst-access external PSRAM. Skip the
+// flash-encrypted PSRAM test paths because encrypted PSRAM requires burst
+// accesses aligned to the encryption block size.
+#define GDMA_TEST_LP_AHB_BURST_PSRAM_SUPPORTED 0
+#else
+#define GDMA_TEST_LP_AHB_BURST_PSRAM_SUPPORTED 1
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
--- a/components/esp_driver_dma/test_apps/dma/main/test_async_memcpy.c
+++ b/components/esp_driver_dma/test_apps/dma/main/test_async_memcpy.c
@@ -17,6 +17,7 @@
 #include "esp_async_memcpy.h"
 #include "hal/efuse_hal.h"
 #include "esp_efuse.h"
+#include "gdma_test_utils.h"

 #if SOC_GDMA_SUPPORTED
 #include "hal/gdma_ll.h"
@@ -409,10 +410,14 @@ TEST_CASE("memory copy performance 40KB: PSRAM->PSRAM", "[async mcp]")

 #if SOC_HAS(LP_AHB_GDMA)
 #if GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE)
-    printf("Testing memcpy by LP AHB GDMA\r\n");
-    TEST_ESP_OK(esp_async_memcpy_install_gdma_lp_ahb(&driver_config, &driver));
-    test_memcpy_performance(driver, 40 * 1024, true, true);
-    TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
+    if (esp_efuse_is_flash_encryption_enabled() && !GDMA_TEST_LP_AHB_BURST_PSRAM_SUPPORTED) {
+        TEST_IGNORE_MESSAGE("Skipping LP AHB GDMA PSRAM->PSRAM under flash encryption");
+    } else {
+        printf("Testing memcpy by LP AHB GDMA\r\n");
+        TEST_ESP_OK(esp_async_memcpy_install_gdma_lp_ahb(&driver_config, &driver));
+        test_memcpy_performance(driver, 40 * 1024, true, true);
+        TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
+    }
 #endif // GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE)
 #endif // SOC_HAS(LP_AHB_GDMA)
 }
--- a/components/esp_driver_dma/test_apps/dma/main/test_gdma.c
+++ b/components/esp_driver_dma/test_apps/dma/main/test_gdma.c
@@ -399,6 +399,7 @@ static void test_gdma_m2m_mode(bool trig_retention_backup)
    gdma_channel_alloc_config_t chan_alloc_config = {};

 #if SOC_HAS(AHB_GDMA)
+    printf("Testing GDMA M2M Mode by AHB GDMA%s\n", trig_retention_backup ? " with retention backup" : "");
    TEST_ESP_OK(gdma_new_ahb_channel(&chan_alloc_config, &tx_chan, &rx_chan));

    test_gdma_m2m_transaction(tx_chan, rx_chan, false, trig_retention_backup);
@@ -408,6 +409,7 @@ static void test_gdma_m2m_mode(bool trig_retention_backup)
 #endif // SOC_HAS(AHB_GDMA)

 #if SOC_HAS(AXI_GDMA)
+    printf("Testing GDMA M2M Mode by AXI GDMA%s\n", trig_retention_backup ? " with retention backup" : "");
    TEST_ESP_OK(gdma_new_axi_channel(&chan_alloc_config, &tx_chan, &rx_chan));

    bool lli_in_ext_mem = false;
@@ -422,12 +424,17 @@ static void test_gdma_m2m_mode(bool trig_retention_backup)
 #endif // SOC_HAS(AXI_GDMA)

 #if SOC_HAS(LP_AHB_GDMA)
-    TEST_ESP_OK(gdma_new_lp_ahb_channel(&chan_alloc_config, &tx_chan, &rx_chan));
+    if (esp_efuse_is_flash_encryption_enabled() && !GDMA_TEST_LP_AHB_BURST_PSRAM_SUPPORTED) {
+        TEST_IGNORE_MESSAGE("Skip LP-AHB-GDMA GDMA M2M Mode under flash encryption");
+    } else {
+        printf("Testing GDMA M2M Mode by LP-AHB GDMA%s\n", trig_retention_backup ? " with retention backup" : "");
+        TEST_ESP_OK(gdma_new_lp_ahb_channel(&chan_alloc_config, &tx_chan, &rx_chan));

-    test_gdma_m2m_transaction(tx_chan, rx_chan, false, trig_retention_backup);
+        test_gdma_m2m_transaction(tx_chan, rx_chan, false, trig_retention_backup);

-    TEST_ESP_OK(gdma_del_channel(tx_chan));
-    TEST_ESP_OK(gdma_del_channel(rx_chan));
+        TEST_ESP_OK(gdma_del_channel(tx_chan));
+        TEST_ESP_OK(gdma_del_channel(rx_chan));
+    }
 #endif // SOC_HAS(LP_AHB_GDMA)
 }

@@ -837,13 +844,19 @@ TEST_CASE("GDMA memory copy SRAM->PSRAM->SRAM", "[GDMA][M2M]")
 #endif // SOC_HAS(AXI_GDMA)

 #if SOC_HAS(LP_AHB_GDMA)
-    printf("Testing LP-AHB-GDMA memory copy SRAM->PSRAM->SRAM\n");
-    TEST_ESP_OK(gdma_new_lp_ahb_channel(&chan_alloc_config, &tx_chan, &rx_chan));
+#if GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE)
+    if (esp_efuse_is_flash_encryption_enabled() && !GDMA_TEST_LP_AHB_BURST_PSRAM_SUPPORTED) {
+        TEST_IGNORE_MESSAGE("Skipping LP-AHB-GDMA SRAM->PSRAM->SRAM under flash encryption");
+    } else {
+        printf("Testing LP-AHB-GDMA memory copy SRAM->PSRAM->SRAM\n");
+        TEST_ESP_OK(gdma_new_lp_ahb_channel(&chan_alloc_config, &tx_chan, &rx_chan));

-    test_gdma_memcpy_from_to_psram(tx_chan, rx_chan);
+        test_gdma_memcpy_from_to_psram(tx_chan, rx_chan);

-    TEST_ESP_OK(gdma_del_channel(tx_chan));
-    TEST_ESP_OK(gdma_del_channel(rx_chan));
+        TEST_ESP_OK(gdma_del_channel(tx_chan));
+        TEST_ESP_OK(gdma_del_channel(rx_chan));
+    }
+#endif // GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE)
 #endif // SOC_HAS(LP_AHB_GDMA)
 }
 #endif // SOC_SPIRAM_SUPPORTED
--- a/components/esp_driver_dma/test_apps/dma/pytest_dma.py
+++ b/components/esp_driver_dma/test_apps/dma/pytest_dma.py
@@ -71,7 +71,17 @@ def test_dma_weighted_arbitration(dut: Dut) -> None:
    ],
    indirect=True,
 )
-@idf_parametrize('target', ['esp32p4', 'esp32c5'], indirect=['target'])
+@idf_parametrize(
+    'target',
+    soc_filtered_targets(
+        'SOC_GDMA_SUPPORTED == 1 and '
+        'SOC_PSRAM_DMA_CAPABLE == 1 and '
+        'SOC_FLASH_ENC_SUPPORTED == 1 and '
+        'IDF_TARGET not in ["esp32s3"]'
+    ),
+    indirect=['target'],
+)
+@pytest.mark.temp_skip_ci(targets=['esp32h4', 'esp32c61'], reason='no runner yet')
 def test_dma_flash_encryption(dut: Dut) -> None:
    dut.run_all_single_board_cases()

--- a/components/esp_driver_dma/test_apps/dma2d/pytest_dma2d.py
+++ b/components/esp_driver_dma/test_apps/dma2d/pytest_dma2d.py
@@ -41,7 +41,8 @@ def test_dma2d_esp32p4_rev1(dut: Dut) -> None:
    ],
    indirect=True,
 )
-@idf_parametrize('target', soc_filtered_targets('SOC_DMA2D_SUPPORTED == 1'), indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='TODO: IDFCI-10377 no runner yet')
+@idf_parametrize(
+    'target', soc_filtered_targets('SOC_DMA2D_SUPPORTED == 1 and SOC_FLASH_ENC_SUPPORTED == 1'), indirect=['target']
+)
 def test_dma2d_flash_encryption(dut: Dut) -> None:
    dut.run_all_single_board_cases()