feat(esp_hw_support): Memory region protection for ESP32-H4

components/esp_hw_support/port/esp32h4/cpu_region_protect.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,10 @@
 #include "soc/soc.h"
 #include "esp_cpu.h"
 #include "esp_fault.h"
+#include "esp32h4/rom/rom_layout.h"
+#if CONFIG_SPIRAM
+#include "esp_private/esp_psram_extram.h"
+#endif /* CONFIG_SPIRAM */
 
 #ifdef BOOTLOADER_BUILD
 // Without L bit set
@@ -16,26 +20,87 @@
 #define CONDITIONAL_RX          PMP_R | PMP_X
 #define CONDITIONAL_RW          PMP_R | PMP_W
 #define CONDITIONAL_RWX         PMP_R | PMP_W | PMP_X
+// PMA entries must not be locked in the bootloader, otherwise the application cannot
+// reconfigure them (e.g. a single-core application booted by a multi-core bootloader needs
+// to extend the valid RAM window over the reclaimed ICache1 SRAM, see SOC_HP_RAM_HIGH below).
+#define CONDITIONAL_PMA_L       0x0
 #else
 // With L bit set
 #define CONDITIONAL_NONE        NONE
 #define CONDITIONAL_RX          RX
 #define CONDITIONAL_RW          RW
 #define CONDITIONAL_RWX         RWX
+#define CONDITIONAL_PMA_L       PMA_L
 #endif
 
-//TODO: [ESP32H4] IDF-12588
+#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr)   (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1))
+#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1))
+#define ALIGN_UP(addr, align)  ((addr) & ~((align) - 1))
+
+/* In single core mode, the ICache1 SRAM block (SOC_RAM_ICACHE1_LOW..SOC_RAM_ICACHE1_HIGH) is
+ * reclaimed and handed to the heap as regular RAM (see components/heap/port/esp32h4/memory_layout.c).
+ * It is contiguous with the top of the D/IRAM region, so the region protection must extend the valid
+ * RAM window up to the top of ICache1, otherwise the first access to that heap memory triggers a
+ * load/store access fault. In multi-core mode the same block is used as actual I-Cache and must stay
+ * outside the valid RAM window.
+ */
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+#define SOC_HP_RAM_HIGH   (SOC_RAM_ICACHE1_HIGH + 1)
+_Static_assert(SOC_IRAM_HIGH == SOC_RAM_ICACHE1_LOW, "ICache1 RAM must be contiguous with D/IRAM");
+#else
+#define SOC_HP_RAM_HIGH   SOC_IRAM_HIGH
+#endif
 
 static void esp_cpu_configure_invalid_regions(void)
 {
-    abort();
+    const unsigned PMA_NONE                            = CONDITIONAL_PMA_L | PMA_EN;
+    __attribute__((unused)) const unsigned PMA_RW      = CONDITIONAL_PMA_L | PMA_EN | PMA_R | PMA_W;
+    __attribute__((unused)) const unsigned PMA_RX      = CONDITIONAL_PMA_L | PMA_EN | PMA_R | PMA_X;
+    __attribute__((unused)) const unsigned PMA_RWX     = CONDITIONAL_PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
+
+    // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF
+
+    // 0. Gap at bottom of address space
+    PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
+
+    // 1. Gap between CPU subsystem region & ROM-Cache
+    PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
+
+    // 2. ROM has configured the ROM region to be cacheable, lock the configuration
+    PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_IROM_MASK_LOW, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(4, SOC_DROM_MASK_HIGH, PMA_TOR | PMA_RX);
+
+    // 3. Gap between ROM-Cache & RAM
+    PMA_RESET_AND_ENTRY_SET_TOR(5, SOC_DROM_MASK_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
+
+    // 4. Gap between DRAM and I_Cache
+    // In single core mode SOC_HP_RAM_HIGH includes the ICache1 SRAM that is used as heap RAM,
+    // so the invalid gap starts above it.
+    PMA_RESET_AND_ENTRY_SET_TOR(7, SOC_HP_RAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
+
+    // 5. ROM has configured the MSPI region with RX permission, add W attribute for PSRAM and lock
+    // This function sets invalid regions but this is a valid memory region configuration that could have
+    // been configured using PMP as well, but due to insufficient PMP entries we are configuring this using PMA.
+    // This entry is also required to be set using PMA because the region needs to be configured as cacheable.
+    PMA_RESET_AND_ENTRY_SET_NAPOT(9, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
+
+    // 6. Gap between D_Cache & peripheral addresses
+    PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_DROM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(11, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
+
+    // 7. End of address space
+    PMA_RESET_AND_ENTRY_SET_TOR(12, SOC_PERIPHERAL_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(13, UINT32_MAX, PMA_TOR | PMA_NONE);
+
+    PMA_ENTRY_CFG_RESET(14);
+    PMA_ENTRY_CFG_RESET(15);
 }
 
 void esp_cpu_configure_region_protection(void)
 {
-    // ROM has configured the MSPI region with RX permission, we should add W attribute for psram
-    PMA_ENTRY_SET_NAPOT(0, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X);
-    return;
     /* Notes on implementation:
      *
      * 1) Note: ESP32-H4 CPU doesn't support overlapping PMP regions
@@ -58,7 +123,7 @@ void esp_cpu_configure_region_protection(void)
      *
      * 2. Application build with CONFIG_ESP_SYSTEM_MEMPROT enabled
      *    - We split the SRAM into IRAM and DRAM such that IRAM region cannot be written to
-     *      and DRAM region cannot be executed. We use _iram_end and _data_start markers to set the boundaries.
+     *      and DRAM region cannot be executed. We use _iram_text_end and _data_start markers to set the boundaries.
      *      We also lock these entries so the R/W/X permissions are enforced even for machine mode
      *
      * 3. Application build with CONFIG_ESP_SYSTEM_MEMPROT disabled
@@ -72,10 +137,10 @@ void esp_cpu_configure_region_protection(void)
      *      We also lock these entries so the R/W/X permissions are enforced even for machine mode
      */
     const unsigned NONE    = PMP_L;
-    const unsigned R       = PMP_L | PMP_R;
+    __attribute__((unused)) const unsigned R       = PMP_L | PMP_R;
-    const unsigned RW      = PMP_L | PMP_R | PMP_W;
+    __attribute__((unused)) const unsigned RW      = PMP_L | PMP_R | PMP_W;
-    const unsigned RX      = PMP_L | PMP_R | PMP_X;
+    __attribute__((unused)) const unsigned RX      = PMP_L | PMP_R | PMP_X;
-    const unsigned RWX     = PMP_L | PMP_R | PMP_W | PMP_X;
+    __attribute__((unused)) const unsigned RWX     = PMP_L | PMP_R | PMP_W | PMP_X;
 
     //
     // Configure all the invalid address regions using PMA
@@ -86,91 +151,90 @@ void esp_cpu_configure_region_protection(void)
     // Configure all the valid address regions using PMP
     //
 
-    // 1. Debug region
+    // 1. CPU Subsystem region - contains debug mode code and interrupt config registers
-    const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_DEBUG_LOW, SOC_DEBUG_HIGH);
+    const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH);
     PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX);
-    _Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region");
+    _Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
 
-    // 2.1 I-ROM
+    // 2. I/D-ROM (ROM-Cache)
-    PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
+#if CONFIG_ESP_SYSTEM_MEMPROT && CONFIG_ESP_SYSTEM_MEMPROT_PMP && !BOOTLOADER_BUILD
-    PMP_ENTRY_SET(2, SOC_IROM_MASK_HIGH, PMP_TOR | RX);
+    const uint32_t drom_start = (uint32_t) (ets_rom_layout_p->drom_start);
-    _Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I-ROM region");
+    if ((drom_start & (SOC_CPU_PMP_REGION_GRANULARITY - 1)) == 0) {
-
+        // We can skip configuring the PMP entry for the [SOC_IROM_MASK_LOW - drom_start]
-    // 2.2 D-ROM
+        // region as RX, as we already have configured a PMA entry with RX permissions for the
-    PMP_ENTRY_SET(3, SOC_DROM_MASK_LOW, NONE);
+        // [SOC_IROM_MASK_LOW - SOC_DROM_MASK_HIGH] region that helps us to also configure
-    PMP_ENTRY_SET(4, SOC_DROM_MASK_HIGH, PMP_TOR | R);
+        // the region as cacheable. Thus, we save on one PMP entry.
-    _Static_assert(SOC_DROM_MASK_LOW < SOC_DROM_MASK_HIGH, "Invalid D-ROM region");
+        PMP_ENTRY_SET(1, drom_start, NONE);
+        PMP_ENTRY_SET(2, SOC_DROM_MASK_HIGH, PMP_TOR | R);
+    } else
+#endif
+    {
+        PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
+        PMP_ENTRY_SET(2, SOC_IROM_MASK_HIGH, PMP_TOR | CONDITIONAL_RX);
+        _Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I/D-ROM region");
+    }
 
+    // 3. IRAM and DRAM
     if (esp_cpu_dbgr_is_attached()) {
         // Anti-FI check that cpu is really in ocd mode
         ESP_FAULT_ASSERT(esp_cpu_dbgr_is_attached());
 
-        // 5. IRAM and DRAM
+        PMP_ENTRY_SET(3, SOC_IRAM_LOW, NONE);
-        // const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
+        PMP_ENTRY_SET(4, SOC_HP_RAM_HIGH, PMP_TOR | RWX);
-        // PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | RWX);
-        // _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
-        PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
-        PMP_ENTRY_SET(6, SOC_IRAM_HIGH, PMP_TOR | RWX);
         _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
     } else {
 #if CONFIG_ESP_SYSTEM_MEMPROT && CONFIG_ESP_SYSTEM_MEMPROT_PMP && !BOOTLOADER_BUILD
-        extern int _iram_end;
+        extern int _iram_text_end;
-        // 5. IRAM and DRAM
+        PMP_ENTRY_CFG_RESET(3);
-        /* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
+        PMP_ENTRY_CFG_RESET(4);
-         * Bootloader might have given extra permissions and those won't be cleared
-         */
         PMP_ENTRY_CFG_RESET(5);
-        PMP_ENTRY_CFG_RESET(6);
+        PMP_ENTRY_SET(3, SOC_IRAM_LOW, NONE);
-        PMP_ENTRY_CFG_RESET(7);
+        PMP_ENTRY_SET(4, (int)&_iram_text_end, PMP_TOR | RX);
-        PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
+        PMP_ENTRY_SET(5, SOC_HP_RAM_HIGH, PMP_TOR | RW);
-        PMP_ENTRY_SET(6, (int)&_iram_end, PMP_TOR | RX);
-        PMP_ENTRY_SET(7, SOC_DRAM_HIGH, PMP_TOR | RW);
 #else
-        // 5. IRAM and DRAM
+        PMP_ENTRY_SET(3, SOC_IRAM_LOW, CONDITIONAL_NONE);
-        // const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
+        PMP_ENTRY_SET(4, SOC_HP_RAM_HIGH, PMP_TOR | CONDITIONAL_RWX);
-        // PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | CONDITIONAL_RWX);
-        // _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
-        PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
-        PMP_ENTRY_SET(6, SOC_IRAM_HIGH, PMP_TOR | RWX);
         _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
 #endif
     }
 
-    // 4. I_Cache (flash)
+    // 4. I_Cache / D_Cache (flash)
-    const uint32_t pmpaddr8 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
-    PMP_ENTRY_SET(8, pmpaddr8, PMP_NAPOT | RX);
-    _Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I_Cache region");
-
-    // 5. D_Cache (flash)
-    const uint32_t pmpaddr9 = PMPADDR_NAPOT(SOC_DROM_LOW, SOC_DROM_HIGH);
-    PMP_ENTRY_SET(9, pmpaddr9, PMP_NAPOT | R);
-    _Static_assert(SOC_DROM_LOW < SOC_DROM_HIGH, "Invalid D_Cache region");
-
-    // 6. LP memory
 #if CONFIG_ESP_SYSTEM_MEMPROT && CONFIG_ESP_SYSTEM_MEMPROT_PMP && !BOOTLOADER_BUILD
-    extern int _rtc_text_end;
+    extern int _instruction_reserved_end;
-    /* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
+    extern int _rodata_reserved_end;
-     * Bootloader might have given extra permissions and those won't be cleared
-     */
-    PMP_ENTRY_CFG_RESET(10);
-    PMP_ENTRY_CFG_RESET(11);
-    PMP_ENTRY_CFG_RESET(12);
-    PMP_ENTRY_CFG_RESET(13);
-    PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE);
 
-    // Repeat same previous entry, to ensure next entry has correct base address (TOR)
+    const uint32_t page_aligned_irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
-    PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
+    __attribute__((unused)) const uint32_t page_aligned_drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
-    PMP_ENTRY_SET(12, (int)&_rtc_text_end, PMP_TOR | RX);
+
-    PMP_ENTRY_SET(13, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
+    PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE);
+
+#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
+    PMP_ENTRY_SET(7, (uint32_t)(&_instruction_reserved_end), PMP_TOR | RX);
+    PMP_ENTRY_SET(8, page_aligned_irom_resv_end, PMP_TOR | RW);
 #else
-    const uint32_t pmpaddr10 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
+    PMP_ENTRY_SET(7, page_aligned_irom_resv_end, PMP_TOR | RX);
-    PMP_ENTRY_SET(10, pmpaddr10, PMP_NAPOT | CONDITIONAL_RWX);
+    PMP_ENTRY_SET(8, page_aligned_irom_resv_end, NONE);
-    _Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
+#endif /* CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
+
+#if CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
+    PMP_ENTRY_SET(9, (uint32_t)(&_rodata_reserved_end), PMP_TOR | R);
+#else
+    PMP_ENTRY_SET(9, page_aligned_drom_resv_end, PMP_TOR | R);
+#endif /* CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
+
+#if CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
+    size_t available_psram_heap = esp_psram_get_heap_size_to_protect();
+    PMP_ENTRY_SET(10, ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW);
+#endif /* CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
+#else
+    const uint32_t pmpaddr6 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
+    // Add the W attribute in the case of PSRAM
+    PMP_ENTRY_SET(6, pmpaddr6, PMP_NAPOT | CONDITIONAL_RWX);
+    _Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I/D_Cache region");
 #endif
 
-
+    // 5. Peripheral addresses
-    // 7. Peripheral addresses
+    const uint32_t pmpaddr15 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
-    const uint32_t pmpaddr14 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
+    PMP_ENTRY_SET(15, pmpaddr15, PMP_NAPOT | RW);
-    PMP_ENTRY_SET(14, pmpaddr14, PMP_NAPOT | RW);
     _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
 }

components/esp_rom/esp32h4/include/esp32h4/rom/rom_layout.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -85,16 +85,15 @@ typedef struct {
 #if SUPPORT_USB_DWCOTG
     void *dram_start_usb_dwcotg_rom;
     void *dram_end_usb_dwcotg_rom;
-#else
-    //Two reserved members are defined here, so the structure will not be broken,
-    //please keep in mind that there is no memory can be released between
-    //dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom.
-    void *dram_start_usb_reserved_rom;
-    void *dram_end_usb_reserved_rom;
 #endif
 
     void *dram_start_uart_rom;
     void *dram_end_uart_rom;
+
+    void *eh_frame_vaddr_rom;
+    void *eh_frame_hdr_vaddr_rom;
+
+    void *drom_start;
 } ets_rom_layout_t;
 
 extern const ets_rom_layout_t *const ets_rom_layout_p;

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -419,6 +419,10 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
     bool
     default y
 
+config SOC_CPU_PMP_REGION_GRANULARITY
+    int
+    default 128
+
 config SOC_HP_CPU_HAS_MULTIPLE_CORES
     bool
     default y

components/soc/esp32h4/include/soc/soc.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -142,9 +142,9 @@
 #define SOC_DROM_LOW    SOC_IROM_LOW
 #define SOC_DROM_HIGH   SOC_IROM_HIGH
 #define SOC_IROM_MASK_LOW  0x40000000
-#define SOC_IROM_MASK_HIGH 0x40050000
+#define SOC_IROM_MASK_HIGH 0x40020000
 #define SOC_DROM_MASK_LOW  0x40000000
-#define SOC_DROM_MASK_HIGH 0x40050000
+#define SOC_DROM_MASK_HIGH 0x40020000
 #define SOC_IRAM_LOW    0x40810000
 #define SOC_IRAM_HIGH   0x40860000
 #define SOC_DRAM_LOW    0x40810000
@@ -186,9 +186,9 @@
 #define SOC_PERIPHERAL_LOW 0x60000000
 #define SOC_PERIPHERAL_HIGH 0x60100000
 
-// Debug region, not used by software
+// CPU subsystem region (debug mode code and interrupt config)
-#define SOC_DEBUG_LOW 0x20000000
+#define SOC_CPU_SUBSYSTEM_LOW 0x20000000
-#define SOC_DEBUG_HIGH 0x28000000
+#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
 
 // Start (highest address) of ROM boot stack, only relevant during early boot
 #define SOC_ROM_STACK_START         0x4085d350

components/soc/esp32h4/include/soc/soc_caps.h

@@ -173,6 +173,7 @@
 
 #define SOC_CPU_HAS_PMA                 1
 #define SOC_CPU_IDRAM_SPLIT_USING_PMP   1
+#define SOC_CPU_PMP_REGION_GRANULARITY  128
 
 #define SOC_HP_CPU_HAS_MULTIPLE_CORES   1   // Convenience boolean macro used to determine if a target has multiple cores.
 #define SOC_CPU_HAS_LOCKUP_RESET        1

tools/test_apps/system/panic/panic_base/pytest_panic.py

@@ -635,8 +635,20 @@ CONFIGS_MEMPROT_IDRAM = list(
             'memprot_esp32p4',
             'memprot_esp32h21',
             'memprot_esp32s31',
+            'memprot_esp32h4',
+        ],
+        [
+            'esp32s2',
+            'esp32c3',
+            'esp32c2',
+            'esp32c5',
+            'esp32c61',
+            'esp32h2',
+            'esp32p4',
+            'esp32h21',
+            'esp32s31',
+            'esp32h4',
         ],
-        ['esp32s2', 'esp32c3', 'esp32c2', 'esp32c5', 'esp32c61', 'esp32h2', 'esp32p4', 'esp32h21', 'esp32s31'],
     )
 ) + [
     ('memprot_esp32p4_rev_less_than_v3', 'esp32p4', P4_REV_LESS_THAN_V3_MARKER),
@@ -676,8 +688,9 @@ CONFIGS_MEMPROT_FLASH_IDROM = list(
             'memprot_esp32p4',
             'memprot_esp32h21',
             'memprot_esp32s31',
+            'memprot_esp32h4',
         ],
-        ['esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4', 'esp32h21', 'esp32s31'],
+        ['esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4', 'esp32h21', 'esp32s31', 'esp32h4'],
     )
 ) + [
     ('memprot_esp32p4_rev_less_than_v3', 'esp32p4', P4_REV_LESS_THAN_V3_MARKER),

tools/test_apps/system/panic/panic_base/sdkconfig.ci.memprot_esp32h4

@@ -0,0 +1,8 @@
+# Restricting to ESP32H4
+CONFIG_IDF_TARGET="esp32h4"
+
+# Enabling memory protection
+CONFIG_ESP_SYSTEM_MEMPROT=y
+
+# Enable memprot test
+CONFIG_TEST_MEMPROT=y