mirror of
https://github.com/espressif/esp-idf.git
synced 2026-09-22 13:01:16 +03:00
Merge branch 'feat/feat_enable_h21_light_sleep_v5.4' into 'release/v5.4'
fix(ble): disable flash pd config (5.4) See merge request espressif/esp-idf!49214
This commit is contained in:
@@ -342,7 +342,7 @@ enc_adv_data_cent_ext_should_connect(const struct ble_gap_ext_disc_desc *disc)
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addr_offset = (uint32_t *)&test_addr[1];
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*addr_offset = atoi(CONFIG_EXAMPLE_PEER_ADDR);
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test_addr[5] = 0xC3;
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test_addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
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test_addr[0] = CONFIG_IDF_FIRMWARE_CHIP_ID;
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#endif
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if (memcmp(test_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) {
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return 0;
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@@ -31,28 +31,6 @@
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#include "host/ble_esp_gattc_cache.h"
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#endif
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#if CONFIG_EXAMPLE_USE_CI_ADDRESS
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#ifdef CONFIG_IDF_TARGET_ESP32
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#define TEST_CI_ADDRESS_CHIP_OFFSET (0)
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#elif CONFIG_IDF_TARGET_ESP32C2
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#define TEST_CI_ADDRESS_CHIP_OFFSET (1)
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#elif CONFIG_IDF_TARGET_ESP32C3
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#define TEST_CI_ADDRESS_CHIP_OFFSET (2)
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#elif CONFIG_IDF_TARGET_ESP32C6
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#define TEST_CI_ADDRESS_CHIP_OFFSET (3)
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#elif CONFIG_IDF_TARGET_ESP32C5
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#define TEST_CI_ADDRESS_CHIP_OFFSET (4)
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#elif CONFIG_IDF_TARGET_ESP32H2
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#define TEST_CI_ADDRESS_CHIP_OFFSET (5)
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#elif CONFIG_IDF_TARGET_ESP32P4
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#define TEST_CI_ADDRESS_CHIP_OFFSET (6)
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#elif CONFIG_IDF_TARGET_ESP32S3
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#define TEST_CI_ADDRESS_CHIP_OFFSET (7)
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#elif CONFIG_IDF_TARGET_ESP32C61
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#define TEST_CI_ADDRESS_CHIP_OFFSET (8)
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#endif
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#endif
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#if MYNEWT_VAL(BLE_GATTC)
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/*** The UUID of the service containing the subscribable characteristic ***/
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static const ble_uuid_t * remote_svc_uuid =
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@@ -518,7 +496,7 @@ ext_blecent_should_connect(const struct ble_gap_ext_disc_desc *disc)
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addr_offset = (uint32_t *)&test_addr[1];
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*addr_offset = atoi(CONFIG_EXAMPLE_PEER_ADDR);
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test_addr[5] = 0xC3;
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test_addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
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test_addr[0] = CONFIG_IDF_FIRMWARE_CHIP_ID;
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#endif
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if (memcmp(test_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) {
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return 0;
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@@ -583,7 +561,7 @@ blecent_should_connect(const struct ble_gap_disc_desc *disc)
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addr_offset = (uint32_t *)&test_addr[1];
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*addr_offset = atoi(CONFIG_EXAMPLE_PEER_ADDR);
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test_addr[5] = 0xC3;
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test_addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
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test_addr[0] = CONFIG_IDF_FIRMWARE_CHIP_ID;
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#endif
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if (memcmp(test_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) {
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@@ -1,90 +1,5 @@
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menu "Example Configuration"
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choice EXAMPLE_MAX_CPU_FREQ
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prompt "Maximum CPU frequency"
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default EXAMPLE_MAX_CPU_FREQ_160 if !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C5
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default EXAMPLE_MAX_CPU_FREQ_96 if IDF_TARGET_ESP32H2
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default EXAMPLE_MAX_CPU_FREQ_120 if IDF_TARGET_ESP32C2
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default EXAMPLE_MAX_CPU_FREQ_240 if IDF_TARGET_ESP32C5
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depends on PM_ENABLE
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help
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Maximum CPU frequency to use for dynamic frequency scaling.
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config EXAMPLE_MAX_CPU_FREQ_80
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bool "80 MHz"
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config EXAMPLE_MAX_CPU_FREQ_96
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bool "96 MHz"
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depends on IDF_TARGET_ESP32H2
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config EXAMPLE_MAX_CPU_FREQ_160
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bool "160 MHz"
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config EXAMPLE_MAX_CPU_FREQ_120
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bool "120 MHz"
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depends on IDF_TARGET_ESP32C2
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config EXAMPLE_MAX_CPU_FREQ_240
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bool "240 MHz"
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depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C5
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endchoice
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config EXAMPLE_MAX_CPU_FREQ_MHZ
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int
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default 80 if EXAMPLE_MAX_CPU_FREQ_80
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default 96 if EXAMPLE_MAX_CPU_FREQ_96
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default 120 if EXAMPLE_MAX_CPU_FREQ_120
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default 160 if EXAMPLE_MAX_CPU_FREQ_160
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default 240 if EXAMPLE_MAX_CPU_FREQ_240
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choice EXAMPLE_MIN_CPU_FREQ
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prompt "Minimum CPU frequency"
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default EXAMPLE_MIN_CPU_FREQ_40M if !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C5
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default EXAMPLE_MIN_CPU_FREQ_48M if IDF_TARGET_ESP32C5
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default EXAMPLE_MIN_CPU_FREQ_32M if IDF_TARGET_ESP32H2
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default EXAMPLE_MIN_CPU_FREQ_26M if IDF_TARGET_ESP32C2
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depends on PM_ENABLE
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help
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Minimum CPU frequency to use for dynamic frequency scaling.
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Should be set to XTAL frequency or XTAL frequency divided by integer.
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config EXAMPLE_MIN_CPU_FREQ_80M
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bool "80 MHz"
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depends on !(IDF_TARGET_ESP32 && EXAMPLE_MAX_CPU_FREQ_240)
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help
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ESP32 does not support switching between 240M and 80M.The root cause
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is that when switching between 240M and 80M, we need to disable
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BBPLL and then re-enable it with a different frequency.Since the
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Bluetooth baseband works from PLL frequency, it will temporarily
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lose its 80 MHz clock, while the BBPLL is disabled.
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config EXAMPLE_MIN_CPU_FREQ_48M
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bool "48 MHz (use with 48MHz XTAL)"
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depends on XTAL_FREQ_48 || XTAL_FREQ_AUTO
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config EXAMPLE_MIN_CPU_FREQ_40M
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bool "40 MHz (use with 40MHz XTAL)"
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depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
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config EXAMPLE_MIN_CPU_FREQ_32M
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bool "32 MHz (use with 32MHz XTAL)"
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depends on IDF_TARGET_ESP32H2
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depends on XTAL_FREQ_32 || XTAL_FREQ_AUTO
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config EXAMPLE_MIN_CPU_FREQ_26M
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bool "26 MHz (use with 26MHz XTAL)"
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depends on IDF_TARGET_ESP32C2
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depends on XTAL_FREQ_26 || XTAL_FREQ_AUTO
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config EXAMPLE_MIN_CPU_FREQ_20M
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bool "20 MHz (use with 40MHz XTAL)"
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depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
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config EXAMPLE_MIN_CPU_FREQ_10M
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bool "10 MHz (use with 40MHz XTAL)"
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depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
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endchoice
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config EXAMPLE_MIN_CPU_FREQ_MHZ
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int
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default 80 if EXAMPLE_MIN_CPU_FREQ_80M
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default 48 if EXAMPLE_MIN_CPU_FREQ_48M
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default 40 if EXAMPLE_MIN_CPU_FREQ_40M
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default 32 if EXAMPLE_MIN_CPU_FREQ_32M
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default 26 if EXAMPLE_MIN_CPU_FREQ_26M
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default 20 if EXAMPLE_MIN_CPU_FREQ_20M
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default 10 if EXAMPLE_MIN_CPU_FREQ_10M
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choice EXAMPLE_USE_IO_TYPE
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prompt "I/O Capability"
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default BLE_SM_IO_CAP_NO_IO
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@@ -16,28 +16,7 @@
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#include "console/console.h"
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#include "services/gap/ble_svc_gap.h"
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#include "bleprph.h"
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#if CONFIG_EXAMPLE_USE_CI_ADDRESS
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#ifdef CONFIG_IDF_TARGET_ESP32
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#define TEST_CI_ADDRESS_CHIP_OFFSET (0)
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#elif CONFIG_IDF_TARGET_ESP32C2
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#define TEST_CI_ADDRESS_CHIP_OFFSET (1)
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#elif CONFIG_IDF_TARGET_ESP32C3
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#define TEST_CI_ADDRESS_CHIP_OFFSET (2)
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#elif CONFIG_IDF_TARGET_ESP32C6
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#define TEST_CI_ADDRESS_CHIP_OFFSET (3)
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#elif CONFIG_IDF_TARGET_ESP32C5
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#define TEST_CI_ADDRESS_CHIP_OFFSET (4)
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#elif CONFIG_IDF_TARGET_ESP32H2
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#define TEST_CI_ADDRESS_CHIP_OFFSET (5)
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#elif CONFIG_IDF_TARGET_ESP32P4
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#define TEST_CI_ADDRESS_CHIP_OFFSET (6)
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#elif CONFIG_IDF_TARGET_ESP32S3
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#define TEST_CI_ADDRESS_CHIP_OFFSET (7)
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#elif CONFIG_IDF_TARGET_ESP32C61
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#define TEST_CI_ADDRESS_CHIP_OFFSET (8)
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#endif
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#endif
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#include "soc/rtc.h"
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#if CONFIG_EXAMPLE_EXTENDED_ADV
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static uint8_t ext_adv_pattern_1[] = {
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@@ -531,7 +510,7 @@ bleprph_on_sync(void)
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uint32_t *offset = (uint32_t *)&addr[1];
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*offset = atoi(CONFIG_EXAMPLE_CI_ADDRESS_OFFSET);
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addr[5] = 0xC3;
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addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
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addr[0] = CONFIG_IDF_FIRMWARE_CHIP_ID;
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rc = ble_hs_id_set_rnd(addr);
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assert(rc == 0);
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}
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@@ -595,8 +574,8 @@ app_main(void)
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// maximum and minimum frequencies are set in sdkconfig,
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// automatic light sleep is enabled if tickless idle support is enabled.
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esp_pm_config_t pm_config = {
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.max_freq_mhz = CONFIG_EXAMPLE_MAX_CPU_FREQ_MHZ,
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.min_freq_mhz = CONFIG_EXAMPLE_MIN_CPU_FREQ_MHZ,
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.max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
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.min_freq_mhz = rtc_clk_xtal_freq_get(),
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#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
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.light_sleep_enable = true
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#endif
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@@ -17,6 +17,5 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
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#
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# Sleep Config
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#
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CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
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CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
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# end of Sleep Config
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@@ -17,6 +17,5 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
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#
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# Sleep Config
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#
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CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
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CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
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# end of Sleep Config
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@@ -18,7 +18,6 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
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#
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# Sleep Config
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#
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CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
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CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
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# end of Sleep Config
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@@ -18,7 +18,6 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
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#
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# Sleep Config
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#
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CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
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CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
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# end of Sleep Config
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