Merge branch 'feat/feat_enable_h21_light_sleep_v5.4' into 'release/v5.4'

fix(ble): disable flash pd config (5.4)

See merge request espressif/esp-idf!49214
This commit is contained in:
Island
2026-06-29 17:46:59 +08:00
8 changed files with 7 additions and 139 deletions

View File

@@ -342,7 +342,7 @@ enc_adv_data_cent_ext_should_connect(const struct ble_gap_ext_disc_desc *disc)
addr_offset = (uint32_t *)&test_addr[1];
*addr_offset = atoi(CONFIG_EXAMPLE_PEER_ADDR);
test_addr[5] = 0xC3;
test_addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
test_addr[0] = CONFIG_IDF_FIRMWARE_CHIP_ID;
#endif
if (memcmp(test_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) {
return 0;

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@@ -31,28 +31,6 @@
#include "host/ble_esp_gattc_cache.h"
#endif
#if CONFIG_EXAMPLE_USE_CI_ADDRESS
#ifdef CONFIG_IDF_TARGET_ESP32
#define TEST_CI_ADDRESS_CHIP_OFFSET (0)
#elif CONFIG_IDF_TARGET_ESP32C2
#define TEST_CI_ADDRESS_CHIP_OFFSET (1)
#elif CONFIG_IDF_TARGET_ESP32C3
#define TEST_CI_ADDRESS_CHIP_OFFSET (2)
#elif CONFIG_IDF_TARGET_ESP32C6
#define TEST_CI_ADDRESS_CHIP_OFFSET (3)
#elif CONFIG_IDF_TARGET_ESP32C5
#define TEST_CI_ADDRESS_CHIP_OFFSET (4)
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_CI_ADDRESS_CHIP_OFFSET (5)
#elif CONFIG_IDF_TARGET_ESP32P4
#define TEST_CI_ADDRESS_CHIP_OFFSET (6)
#elif CONFIG_IDF_TARGET_ESP32S3
#define TEST_CI_ADDRESS_CHIP_OFFSET (7)
#elif CONFIG_IDF_TARGET_ESP32C61
#define TEST_CI_ADDRESS_CHIP_OFFSET (8)
#endif
#endif
#if MYNEWT_VAL(BLE_GATTC)
/*** The UUID of the service containing the subscribable characteristic ***/
static const ble_uuid_t * remote_svc_uuid =
@@ -518,7 +496,7 @@ ext_blecent_should_connect(const struct ble_gap_ext_disc_desc *disc)
addr_offset = (uint32_t *)&test_addr[1];
*addr_offset = atoi(CONFIG_EXAMPLE_PEER_ADDR);
test_addr[5] = 0xC3;
test_addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
test_addr[0] = CONFIG_IDF_FIRMWARE_CHIP_ID;
#endif
if (memcmp(test_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) {
return 0;
@@ -583,7 +561,7 @@ blecent_should_connect(const struct ble_gap_disc_desc *disc)
addr_offset = (uint32_t *)&test_addr[1];
*addr_offset = atoi(CONFIG_EXAMPLE_PEER_ADDR);
test_addr[5] = 0xC3;
test_addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
test_addr[0] = CONFIG_IDF_FIRMWARE_CHIP_ID;
#endif
if (memcmp(test_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) {

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@@ -1,90 +1,5 @@
menu "Example Configuration"
choice EXAMPLE_MAX_CPU_FREQ
prompt "Maximum CPU frequency"
default EXAMPLE_MAX_CPU_FREQ_160 if !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C5
default EXAMPLE_MAX_CPU_FREQ_96 if IDF_TARGET_ESP32H2
default EXAMPLE_MAX_CPU_FREQ_120 if IDF_TARGET_ESP32C2
default EXAMPLE_MAX_CPU_FREQ_240 if IDF_TARGET_ESP32C5
depends on PM_ENABLE
help
Maximum CPU frequency to use for dynamic frequency scaling.
config EXAMPLE_MAX_CPU_FREQ_80
bool "80 MHz"
config EXAMPLE_MAX_CPU_FREQ_96
bool "96 MHz"
depends on IDF_TARGET_ESP32H2
config EXAMPLE_MAX_CPU_FREQ_160
bool "160 MHz"
config EXAMPLE_MAX_CPU_FREQ_120
bool "120 MHz"
depends on IDF_TARGET_ESP32C2
config EXAMPLE_MAX_CPU_FREQ_240
bool "240 MHz"
depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C5
endchoice
config EXAMPLE_MAX_CPU_FREQ_MHZ
int
default 80 if EXAMPLE_MAX_CPU_FREQ_80
default 96 if EXAMPLE_MAX_CPU_FREQ_96
default 120 if EXAMPLE_MAX_CPU_FREQ_120
default 160 if EXAMPLE_MAX_CPU_FREQ_160
default 240 if EXAMPLE_MAX_CPU_FREQ_240
choice EXAMPLE_MIN_CPU_FREQ
prompt "Minimum CPU frequency"
default EXAMPLE_MIN_CPU_FREQ_40M if !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C5
default EXAMPLE_MIN_CPU_FREQ_48M if IDF_TARGET_ESP32C5
default EXAMPLE_MIN_CPU_FREQ_32M if IDF_TARGET_ESP32H2
default EXAMPLE_MIN_CPU_FREQ_26M if IDF_TARGET_ESP32C2
depends on PM_ENABLE
help
Minimum CPU frequency to use for dynamic frequency scaling.
Should be set to XTAL frequency or XTAL frequency divided by integer.
config EXAMPLE_MIN_CPU_FREQ_80M
bool "80 MHz"
depends on !(IDF_TARGET_ESP32 && EXAMPLE_MAX_CPU_FREQ_240)
help
ESP32 does not support switching between 240M and 80M.The root cause
is that when switching between 240M and 80M, we need to disable
BBPLL and then re-enable it with a different frequency.Since the
Bluetooth baseband works from PLL frequency, it will temporarily
lose its 80 MHz clock, while the BBPLL is disabled.
config EXAMPLE_MIN_CPU_FREQ_48M
bool "48 MHz (use with 48MHz XTAL)"
depends on XTAL_FREQ_48 || XTAL_FREQ_AUTO
config EXAMPLE_MIN_CPU_FREQ_40M
bool "40 MHz (use with 40MHz XTAL)"
depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
config EXAMPLE_MIN_CPU_FREQ_32M
bool "32 MHz (use with 32MHz XTAL)"
depends on IDF_TARGET_ESP32H2
depends on XTAL_FREQ_32 || XTAL_FREQ_AUTO
config EXAMPLE_MIN_CPU_FREQ_26M
bool "26 MHz (use with 26MHz XTAL)"
depends on IDF_TARGET_ESP32C2
depends on XTAL_FREQ_26 || XTAL_FREQ_AUTO
config EXAMPLE_MIN_CPU_FREQ_20M
bool "20 MHz (use with 40MHz XTAL)"
depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
config EXAMPLE_MIN_CPU_FREQ_10M
bool "10 MHz (use with 40MHz XTAL)"
depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
endchoice
config EXAMPLE_MIN_CPU_FREQ_MHZ
int
default 80 if EXAMPLE_MIN_CPU_FREQ_80M
default 48 if EXAMPLE_MIN_CPU_FREQ_48M
default 40 if EXAMPLE_MIN_CPU_FREQ_40M
default 32 if EXAMPLE_MIN_CPU_FREQ_32M
default 26 if EXAMPLE_MIN_CPU_FREQ_26M
default 20 if EXAMPLE_MIN_CPU_FREQ_20M
default 10 if EXAMPLE_MIN_CPU_FREQ_10M
choice EXAMPLE_USE_IO_TYPE
prompt "I/O Capability"
default BLE_SM_IO_CAP_NO_IO

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@@ -16,28 +16,7 @@
#include "console/console.h"
#include "services/gap/ble_svc_gap.h"
#include "bleprph.h"
#if CONFIG_EXAMPLE_USE_CI_ADDRESS
#ifdef CONFIG_IDF_TARGET_ESP32
#define TEST_CI_ADDRESS_CHIP_OFFSET (0)
#elif CONFIG_IDF_TARGET_ESP32C2
#define TEST_CI_ADDRESS_CHIP_OFFSET (1)
#elif CONFIG_IDF_TARGET_ESP32C3
#define TEST_CI_ADDRESS_CHIP_OFFSET (2)
#elif CONFIG_IDF_TARGET_ESP32C6
#define TEST_CI_ADDRESS_CHIP_OFFSET (3)
#elif CONFIG_IDF_TARGET_ESP32C5
#define TEST_CI_ADDRESS_CHIP_OFFSET (4)
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_CI_ADDRESS_CHIP_OFFSET (5)
#elif CONFIG_IDF_TARGET_ESP32P4
#define TEST_CI_ADDRESS_CHIP_OFFSET (6)
#elif CONFIG_IDF_TARGET_ESP32S3
#define TEST_CI_ADDRESS_CHIP_OFFSET (7)
#elif CONFIG_IDF_TARGET_ESP32C61
#define TEST_CI_ADDRESS_CHIP_OFFSET (8)
#endif
#endif
#include "soc/rtc.h"
#if CONFIG_EXAMPLE_EXTENDED_ADV
static uint8_t ext_adv_pattern_1[] = {
@@ -531,7 +510,7 @@ bleprph_on_sync(void)
uint32_t *offset = (uint32_t *)&addr[1];
*offset = atoi(CONFIG_EXAMPLE_CI_ADDRESS_OFFSET);
addr[5] = 0xC3;
addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
addr[0] = CONFIG_IDF_FIRMWARE_CHIP_ID;
rc = ble_hs_id_set_rnd(addr);
assert(rc == 0);
}
@@ -595,8 +574,8 @@ app_main(void)
// maximum and minimum frequencies are set in sdkconfig,
// automatic light sleep is enabled if tickless idle support is enabled.
esp_pm_config_t pm_config = {
.max_freq_mhz = CONFIG_EXAMPLE_MAX_CPU_FREQ_MHZ,
.min_freq_mhz = CONFIG_EXAMPLE_MIN_CPU_FREQ_MHZ,
.max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
.min_freq_mhz = rtc_clk_xtal_freq_get(),
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
.light_sleep_enable = true
#endif

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@@ -17,6 +17,5 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
#
# Sleep Config
#
CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
# end of Sleep Config

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@@ -17,6 +17,5 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
#
# Sleep Config
#
CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
# end of Sleep Config

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@@ -18,7 +18,6 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
#
# Sleep Config
#
CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
# end of Sleep Config

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@@ -18,7 +18,6 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
#
# Sleep Config
#
CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
# end of Sleep Config