From 06ba6bb4b45e3122654572c788e3b265f3ca1271 Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Tue, 23 Sep 2025 19:05:55 +0530 Subject: [PATCH] fix(esp_tee): Use HAL APIs instead of ROM APIs for SPI flash service calls Currently, REE SPI flash HAL operations are routed as service calls to TEE, but the TEE implementation incorrectly uses ROM APIs instead of HAL APIs. This leads to issues and is not the recommended approach. --- components/esp_rom/CMakeLists.txt | 1 - .../subproject/main/ld/esp32c5/esp_tee.ld.in | 9 +++++++++ .../subproject/main/ld/esp32c6/esp_tee.ld.in | 9 +++++++++ .../subproject/main/ld/esp32h2/esp_tee.ld.in | 9 +++++++++ .../test_apps/tee_cli_app/sdkconfig.ci.release | 2 -- .../test_apps/tee_cli_app/sdkconfig.ci.sb_fe | 4 ++++ .../test_apps/tee_test_fw/sdkconfig.ci.tee_ota | 4 ++++ .../test_apps/tee_test_fw/sdkconfig.defaults | 3 --- components/hal/CMakeLists.txt | 2 +- components/hal/spi_flash_hal_common.inc | 13 ++----------- 10 files changed, 38 insertions(+), 18 deletions(-) diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 2b30df87690..52f93375e9b 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -144,7 +144,6 @@ if(CONFIG_ESP_ROM_HAS_VERSION) endif() if(ESP_TEE_BUILD) - rom_linker_script("spiflash") rom_linker_script("heap") if(CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT) rom_linker_script("newlib-nano") diff --git a/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in b/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in index 73cc9a4599f..f43a8d52c56 100644 --- a/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in +++ b/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in @@ -40,6 +40,11 @@ PROVIDE ( esp_tee_app_config = SRAM_REE_SEG_START + 0x2b0 ); PROVIDE ( GDMA = 0x60080000 ); +/* SPI Flash functions required from the ROM (refer esp32c5.rom.spiflash.ld) */ +PROVIDE ( spi_flash_check_and_flush_cache = 0x40000230 ); +PROVIDE ( spi_flash_chip_generic_config_host_io_mode = 0x400002d4 ); +PROVIDE ( memspi_host_flush_cache = 0x40000318 ); + /* Default entry point: */ ENTRY(esp_tee_init); @@ -98,6 +103,8 @@ SECTIONS *libhal.a:cache_hal.c*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.c*(.literal .text .literal.* .text.*) *libhal.a:apm_hal.c*(.literal .text .literal.* .text.*) + *libhal.a:spi_flash_hal.c*(.literal .text .literal.* .text.*) + *libhal.a:spi_flash_hal_iram.c*(.literal .text .literal.* .text.*) /* IDF components */ *libbootloader_support.a:*(.literal .text .literal.* .text.*) *libesp_hw_support.a:*(.literal .text .literal.* .text.*) @@ -146,6 +153,8 @@ SECTIONS /* HAL (noflash) */ *libhal.a:mmu_hal.c*(.rodata .srodata .rodata.* .srodata.*) *libhal.a:cache_hal.c*(.rodata .srodata .rodata.* .srodata.*) + *libhal.a:spi_flash_hal.c*(.rodata .srodata .rodata.* .srodata.*) + *libhal.a:spi_flash_hal_iram.c*(.rodata .srodata .rodata.* .srodata.*) _tee_rodata_end = ABSOLUTE(.); _tee_dram_end = ABSOLUTE(.); } > sram_tee_seg diff --git a/components/esp_tee/subproject/main/ld/esp32c6/esp_tee.ld.in b/components/esp_tee/subproject/main/ld/esp32c6/esp_tee.ld.in index 121f4f4b656..4ab75b2af64 100644 --- a/components/esp_tee/subproject/main/ld/esp32c6/esp_tee.ld.in +++ b/components/esp_tee/subproject/main/ld/esp32c6/esp_tee.ld.in @@ -40,6 +40,11 @@ PROVIDE ( esp_tee_app_config = SRAM_REE_SEG_START + 0x2e0 ); PROVIDE ( GDMA = 0x60080000 ); +/* SPI Flash functions required from the ROM (refer esp32c6.rom.spiflash.ld) */ +PROVIDE ( spi_flash_check_and_flush_cache = 0x4000021c ); +PROVIDE ( spi_flash_chip_generic_config_host_io_mode = 0x400002c4 ); +PROVIDE ( memspi_host_flush_cache = 0x40000308 ); + /* Default entry point: */ ENTRY(esp_tee_init); @@ -98,6 +103,8 @@ SECTIONS *libhal.a:cache_hal.c*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.c*(.literal .text .literal.* .text.*) *libhal.a:apm_hal.c*(.literal .text .literal.* .text.*) + *libhal.a:spi_flash_hal.c*(.literal .text .literal.* .text.*) + *libhal.a:spi_flash_hal_iram.c*(.literal .text .literal.* .text.*) /* IDF components */ *libbootloader_support.a:*(.literal .text .literal.* .text.*) *libesp_hw_support.a:*(.literal .text .literal.* .text.*) @@ -146,6 +153,8 @@ SECTIONS /* HAL (noflash) */ *libhal.a:mmu_hal.c*(.rodata .srodata .rodata.* .srodata.*) *libhal.a:cache_hal.c*(.rodata .srodata .rodata.* .srodata.*) + *libhal.a:spi_flash_hal.c*(.rodata .srodata .rodata.* .srodata.*) + *libhal.a:spi_flash_hal_iram.c*(.rodata .srodata .rodata.* .srodata.*) _tee_rodata_end = ABSOLUTE(.); _tee_dram_end = ABSOLUTE(.); } > sram_tee_seg diff --git a/components/esp_tee/subproject/main/ld/esp32h2/esp_tee.ld.in b/components/esp_tee/subproject/main/ld/esp32h2/esp_tee.ld.in index 121f4f4b656..8fab6ff223f 100644 --- a/components/esp_tee/subproject/main/ld/esp32h2/esp_tee.ld.in +++ b/components/esp_tee/subproject/main/ld/esp32h2/esp_tee.ld.in @@ -40,6 +40,11 @@ PROVIDE ( esp_tee_app_config = SRAM_REE_SEG_START + 0x2e0 ); PROVIDE ( GDMA = 0x60080000 ); +/* SPI Flash functions required from the ROM (refer esp32h2.rom.spiflash.ld) */ +PROVIDE ( spi_flash_check_and_flush_cache = 0x40000214 ); +PROVIDE ( spi_flash_chip_generic_config_host_io_mode = 0x400002bc ); +PROVIDE ( memspi_host_flush_cache = 0x40000300 ); + /* Default entry point: */ ENTRY(esp_tee_init); @@ -98,6 +103,8 @@ SECTIONS *libhal.a:cache_hal.c*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.c*(.literal .text .literal.* .text.*) *libhal.a:apm_hal.c*(.literal .text .literal.* .text.*) + *libhal.a:spi_flash_hal.c*(.literal .text .literal.* .text.*) + *libhal.a:spi_flash_hal_iram.c*(.literal .text .literal.* .text.*) /* IDF components */ *libbootloader_support.a:*(.literal .text .literal.* .text.*) *libesp_hw_support.a:*(.literal .text .literal.* .text.*) @@ -146,6 +153,8 @@ SECTIONS /* HAL (noflash) */ *libhal.a:mmu_hal.c*(.rodata .srodata .rodata.* .srodata.*) *libhal.a:cache_hal.c*(.rodata .srodata .rodata.* .srodata.*) + *libhal.a:spi_flash_hal.c*(.rodata .srodata .rodata.* .srodata.*) + *libhal.a:spi_flash_hal_iram.c*(.rodata .srodata .rodata.* .srodata.*) _tee_rodata_end = ABSOLUTE(.); _tee_dram_end = ABSOLUTE(.); } > sram_tee_seg diff --git a/components/esp_tee/test_apps/tee_cli_app/sdkconfig.ci.release b/components/esp_tee/test_apps/tee_cli_app/sdkconfig.ci.release index 52e758739c9..e96f96e949c 100644 --- a/components/esp_tee/test_apps/tee_cli_app/sdkconfig.ci.release +++ b/components/esp_tee/test_apps/tee_cli_app/sdkconfig.ci.release @@ -1,8 +1,6 @@ # Reducing TEE I/DRAM sizes # 28KB CONFIG_SECURE_TEE_IRAM_SIZE=0x7000 -# 16KB -CONFIG_SECURE_TEE_DRAM_SIZE=0x4000 # TEE Secure Storage: Release mode CONFIG_SECURE_TEE_SEC_STG_MODE_RELEASE=y diff --git a/components/esp_tee/test_apps/tee_cli_app/sdkconfig.ci.sb_fe b/components/esp_tee/test_apps/tee_cli_app/sdkconfig.ci.sb_fe index b1d65ee809d..b84c8bf3986 100644 --- a/components/esp_tee/test_apps/tee_cli_app/sdkconfig.ci.sb_fe +++ b/components/esp_tee/test_apps/tee_cli_app/sdkconfig.ci.sb_fe @@ -13,3 +13,7 @@ CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y # TEE Secure Storage: Release mode CONFIG_SECURE_TEE_SEC_STG_MODE_RELEASE=y CONFIG_SECURE_TEE_SEC_STG_EFUSE_HMAC_KEY_ID=5 + +# Increasing TEE DRAM size +# 18KB +CONFIG_SECURE_TEE_DRAM_SIZE=0x4800 diff --git a/components/esp_tee/test_apps/tee_test_fw/sdkconfig.ci.tee_ota b/components/esp_tee/test_apps/tee_test_fw/sdkconfig.ci.tee_ota index 09d30653ea5..7cbca448490 100644 --- a/components/esp_tee/test_apps/tee_test_fw/sdkconfig.ci.tee_ota +++ b/components/esp_tee/test_apps/tee_test_fw/sdkconfig.ci.tee_ota @@ -15,3 +15,7 @@ CONFIG_SECURE_TEE_ATT_KEY_STR_ID="tee_att_keyN" # Enabling flash protection over SPI1 CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1=y + +# Increasing TEE DRAM size +# 19KB +CONFIG_SECURE_TEE_DRAM_SIZE=0x4c00 diff --git a/components/esp_tee/test_apps/tee_test_fw/sdkconfig.defaults b/components/esp_tee/test_apps/tee_test_fw/sdkconfig.defaults index c7570128d89..161c206fc4a 100644 --- a/components/esp_tee/test_apps/tee_test_fw/sdkconfig.defaults +++ b/components/esp_tee/test_apps/tee_test_fw/sdkconfig.defaults @@ -11,6 +11,3 @@ CONFIG_SECURE_TEE_TEST_MODE=y # Setting partition table CONFIG_PARTITION_TABLE_SINGLE_APP_TEE=y CONFIG_PARTITION_TABLE_OFFSET=0xF000 - -# TEE IRAM size -CONFIG_SECURE_TEE_IRAM_SIZE=0x8400 diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 0692b0e1d6c..d2c9946200e 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -60,7 +60,7 @@ if(esp_tee_build) "ecc_hal.c") if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1) - list(APPEND srcs "spi_flash_hal.c") + list(APPEND srcs "spi_flash_hal.c" "spi_flash_hal_iram.c") endif() elseif(NOT BOOTLOADER_BUILD) list(APPEND srcs "color_hal.c") diff --git a/components/hal/spi_flash_hal_common.inc b/components/hal/spi_flash_hal_common.inc index ff5d1659fde..803c745c652 100644 --- a/components/hal/spi_flash_hal_common.inc +++ b/components/hal/spi_flash_hal_common.inc @@ -132,15 +132,7 @@ esp_err_t spi_flash_hal_configure_host_io_mode( addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS; #endif spi_flash_ll_set_extra_address(dev, 0); - // TODO: [IDF-13582] - // Currently, REE and TEE use different sets of APIs for flash operations - - // REE uses the IDF SPI flash driver while TEE call the ROM APIs. This inconsistency - // leads to compatibility issues on ESP32-C5. - // One specific issue arises when esp_flash_read() is used in REE, which internally - // calls spi_flash_ll_wb_mode_enable(). This function enables the WB mode bit in - // the flash write operation. However, the ROM API does not support this - // feature, resulting in failures when TEE attempts to access flash after this call. -#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL && !CONFIG_SECURE_ENABLE_TEE +#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL spi_flash_ll_wb_mode_enable(dev, true); #endif } @@ -219,8 +211,7 @@ esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_tr if (trans->miso_len > 0) { spi_flash_ll_get_buffer_data(dev, trans->miso_data, trans->miso_len); } - // TODO: [IDF-13582] -#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL && !CONFIG_SECURE_ENABLE_TEE +#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL spi_flash_ll_wb_mode_enable(dev, false); #endif return ESP_OK;