diff --git a/components/esp_driver_gpio/src/dedic_gpio.c b/components/esp_driver_gpio/src/dedic_gpio.c index 3d9b99bd599..64cd1234286 100644 --- a/components/esp_driver_gpio/src/dedic_gpio.c +++ b/components/esp_driver_gpio/src/dedic_gpio.c @@ -17,6 +17,7 @@ #include "esp_cpu.h" #include "soc/soc_caps_full.h" #include "soc/io_mux_reg.h" +#include "hal/dedic_gpio_caps.h" #include "hal/dedic_gpio_cpu_ll.h" #include "esp_private/gpio.h" #include "esp_private/periph_ctrl.h" @@ -25,10 +26,10 @@ #include "driver/dedic_gpio.h" #include "hal/dedic_gpio_periph.h" -#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS +#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) #include "soc/dedic_gpio_struct.h" #endif -#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) #include "hal/dedic_gpio_ll.h" #endif @@ -50,11 +51,11 @@ struct dedic_gpio_platform_t { uint32_t in_occupied_mask; // mask of input channels that already occupied #if SOC_DEDIC_GPIO_HAS_INTERRUPT intr_handle_t intr_hdl; // interrupt handle - dedic_gpio_isr_callback_t cbs[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // array of callback function for input channel - void *cb_args[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // array of callback arguments for input channel - dedic_gpio_bundle_t *in_bundles[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // which bundle belongs to for input channel + dedic_gpio_isr_callback_t cbs[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; // array of callback function for input channel + void *cb_args[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; // array of callback arguments for input channel + dedic_gpio_bundle_t *in_bundles[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; // which bundle belongs to for input channel #endif -#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS +#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) dedic_dev_t *dev; #endif }; @@ -81,18 +82,18 @@ static esp_err_t dedic_gpio_build_platform(int core_id) // initialize platform members s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; // initial occupy_mask: 1111...100...0 - s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1); - s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1); -#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS + s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1); + s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1); +#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) s_platform[core_id]->dev = &DEDIC_GPIO; -#endif // DEDIC_GPIO_LL_ALLOW_REG_ACCESS -#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#endif // DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) +#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) // enable dedicated GPIO register clock PERIPH_RCC_ATOMIC() { dedic_gpio_ll_enable_bus_clock(true); dedic_gpio_ll_reset_register(); } -#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#endif // !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) } } _lock_release(&s_platform_mutexlock[core_id]); @@ -113,12 +114,12 @@ static void dedic_gpio_break_platform(int core_id) if (s_platform[core_id]) { free(s_platform[core_id]); s_platform[core_id] = NULL; -#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) // disable the register clock if no GPIO channel is in use PERIPH_RCC_ATOMIC() { dedic_gpio_ll_enable_bus_clock(false); } -#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#endif // !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) } _lock_release(&s_platform_mutexlock[core_id]); } @@ -222,11 +223,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ // configure outwards channels uint32_t out_offset = 0; if (config->flags.out_en) { - ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, - "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)); + ESP_GOTO_ON_FALSE(config->array_size <= DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, + "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)); // prevent install bundle concurrently portENTER_CRITICAL(&s_platform[core_id]->spinlock); - for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) - config->array_size; i++) { + for (size_t i = 0; i <= DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) - config->array_size; i++) { if ((s_platform[core_id]->out_occupied_mask & (pattern << i)) == 0) { out_mask = pattern << i; out_offset = i; @@ -235,7 +236,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ } if (out_mask) { s_platform[core_id]->out_occupied_mask |= out_mask; -#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS +#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) // always enable instruction to access output GPIO, which has better performance than register access dedic_gpio_ll_enable_instruction_access_out(s_platform[core_id]->dev, out_mask, true); #endif @@ -248,11 +249,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ // configure inwards channels uint32_t in_offset = 0; if (config->flags.in_en) { - ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, - "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)); + ESP_GOTO_ON_FALSE(config->array_size <= DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, + "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)); // prevent install bundle concurrently portENTER_CRITICAL(&s_platform[core_id]->spinlock); - for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU) - config->array_size; i++) { + for (size_t i = 0; i <= DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU) - config->array_size; i++) { if ((s_platform[core_id]->in_occupied_mask & (pattern << i)) == 0) { in_mask = pattern << i; in_offset = i; @@ -320,8 +321,8 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle) portENTER_CRITICAL(&s_platform[core_id]->spinlock); s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask); s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask); - if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1)) && - s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1))) { + if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1)) && + s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1))) { recycle_all = true; } portEXIT_CRITICAL(&s_platform[core_id]->spinlock); diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index 0f0b32cb1d8..fe078d4baed 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -32,9 +32,12 @@ static const char *GPIO_TAG = "gpio"; #define GPIO_ISR_CORE_ID_UNINIT (3) -//default value for SOC_GPIO_SUPPORT_RTC_INDEPENDENT is 0 -#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 0 +// On ESP32, those PADs which have RTC functions must set pullup/down/drv capability via RTC register. +// On other targets, digital IOs have their own registers to control pullup/down/drv capability, independent with RTC_IO (LP_IOMUX) registers. +#if CONFIG_IDF_TARGET_ESP32 +#define GPIO_RTCIO_ARE_INDEPENDENT 0 +#else // for any other target has RTC_IO (LP_IOMUX) registers +#define GPIO_RTCIO_ARE_INDEPENDENT 1 #endif typedef struct { @@ -77,7 +80,7 @@ esp_err_t gpio_pullup_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PU)", ESP_ERR_INVALID_ARG); - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_pullup_en(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -96,7 +99,7 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_pullup_dis(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -115,7 +118,7 @@ esp_err_t gpio_pulldown_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PD)", ESP_ERR_INVALID_ARG); - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_pulldown_en(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -134,7 +137,7 @@ esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_pulldown_dis(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -701,7 +704,7 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG); esp_err_t ret = ESP_OK; - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_set_drive_capability(gpio_context.gpio_hal, gpio_num, strength); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -722,7 +725,7 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG); esp_err_t ret = ESP_OK; - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_get_drive_capability(gpio_context.gpio_hal, gpio_num, strength); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -1062,7 +1065,7 @@ esp_err_t gpio_get_io_config(gpio_num_t gpio_num, gpio_io_config_t *out_io_confi ESP_RETURN_ON_FALSE(out_io_config, ESP_ERR_INVALID_ARG, GPIO_TAG, "out_io_config is a null pointer"); gpio_hal_get_io_config(gpio_context.gpio_hal, gpio_num, out_io_config); -#if !SOC_GPIO_SUPPORT_RTC_INDEPENDENT && SOC_RTCIO_PIN_COUNT > 0 +#if !GPIO_RTCIO_ARE_INDEPENDENT && SOC_RTCIO_PIN_COUNT > 0 if (rtc_gpio_is_valid_gpio(gpio_num)) { int rtcio_num = rtc_io_number_get(gpio_num); out_io_config->pu = rtcio_hal_is_pullup_enabled(rtcio_num); diff --git a/components/esp_driver_gpio/src/gpio_etm.c b/components/esp_driver_gpio/src/gpio_etm.c index d521a64e72d..ad4f117bb0b 100644 --- a/components/esp_driver_gpio/src/gpio_etm.c +++ b/components/esp_driver_gpio/src/gpio_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +15,7 @@ #include "esp_log.h" #include "esp_check.h" #include "soc/soc_caps.h" +#include "hal/gpio_caps.h" #include "hal/gpio_ll.h" #include "hal/gpio_etm_ll.h" #include "esp_private/etm_interface.h" @@ -29,10 +30,10 @@ typedef struct gpio_etm_event_t gpio_etm_event_t; typedef struct gpio_etm_group_t { portMUX_TYPE spinlock; gpio_etm_dev_t *dev; - uint8_t tasks[GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP]; // Array of the acquired action masks in each GPIO ETM task channel - uint8_t events[GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP]; // Array of the acquired event masks in each GPIO ETM event channel + uint8_t tasks[GPIO_CAPS_GET(ETM_TASK_CHANNELS_PER_GROUP)]; // Array of the acquired action masks in each GPIO ETM task channel + uint8_t events[GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP)]; // Array of the acquired event masks in each GPIO ETM event channel uint8_t actions[SOC_GPIO_PIN_COUNT]; // Array of the masks of the added actions to each GPIO - uint8_t edges[GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP]; // Array of the masks of the bound event edges in each GPIO ETM event channel + uint8_t edges[GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP)]; // Array of the masks of the bound event edges in each GPIO ETM event channel } gpio_etm_group_t; struct gpio_etm_event_t { @@ -63,7 +64,7 @@ static esp_err_t gpio_etm_acquire_event_channel(uint8_t event_mask, int *chan_id int free_chan_id = -1; // loop to search free event channel in the group portENTER_CRITICAL(&group->spinlock); - for (int j = 0; j < GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP; j++) { + for (int j = 0; j < GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP); j++) { if (!group->events[j]) { free_chan_id = j; group->events[j] = event_mask; @@ -94,7 +95,7 @@ static esp_err_t gpio_etm_acquire_task_channel(uint8_t task_mask, int *chan_id) int free_chan_id = -1; // loop to search free task channel in the group portENTER_CRITICAL(&group->spinlock); - for (int j = 0; j < GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP; j++) { + for (int j = 0; j < GPIO_CAPS_GET(ETM_TASK_CHANNELS_PER_GROUP); j++) { if (!group->tasks[j]) { free_chan_id = j; group->tasks[j] = task_mask; diff --git a/components/esp_driver_gpio/src/gpio_pin_glitch_filter.c b/components/esp_driver_gpio/src/gpio_pin_glitch_filter.c index 2e62b784433..39e3c912956 100644 --- a/components/esp_driver_gpio/src/gpio_pin_glitch_filter.c +++ b/components/esp_driver_gpio/src/gpio_pin_glitch_filter.c @@ -12,6 +12,7 @@ #include "hal/gpio_ll.h" #include "esp_clk_tree.h" #include "esp_private/io_mux.h" +#include "hal/gpio_caps.h" static const char *TAG = "gpio-filter"; @@ -93,11 +94,11 @@ esp_err_t gpio_new_pin_glitch_filter(const gpio_pin_glitch_filter_config_t *conf // create pm lock according to different clock source #if CONFIG_PM_ENABLE esp_pm_lock_type_t lock_type = ESP_PM_NO_LIGHT_SLEEP; -#if SOC_GPIO_FILTER_CLK_SUPPORT_APB +#if GPIO_CAPS_GET(FILTER_CLK_SUPPORT_APB) if (config->clk_src == GLITCH_FILTER_CLK_SRC_APB) { lock_type = ESP_PM_APB_FREQ_MAX; } -#endif // SOC_GPIO_FILTER_CLK_SUPPORT_APB +#endif // GPIO_CAPS_GET(FILTER_CLK_SUPPORT_APB) sprintf(filter->pm_lock_name, "filter_io_%d", config->gpio_num); // e.g. filter_io_0 ESP_GOTO_ON_ERROR(esp_pm_lock_create(lock_type, 0, filter->pm_lock_name, &filter->pm_lock), err, TAG, "create pm_lock failed"); diff --git a/components/esp_driver_gpio/src/rtc_io.c b/components/esp_driver_gpio/src/rtc_io.c index 362ad86c813..6e955feb7b2 100644 --- a/components/esp_driver_gpio/src/rtc_io.c +++ b/components/esp_driver_gpio/src/rtc_io.c @@ -16,6 +16,9 @@ #include "hal/rtc_io_hal.h" #include "hal/rtc_io_periph.h" #include "soc/soc_caps.h" +#if SOC_RTCIO_PIN_COUNT > 0 +#include "hal/rtc_gpio_caps.h" +#endif #if SOC_LP_GPIO_MATRIX_SUPPORTED #include "soc/lp_gpio_pins.h" #endif @@ -263,11 +266,11 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num) esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) { ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error"); -#if !SOC_RTCIO_EDGE_WAKE_SUPPORTED +#if !RTC_GPIO_CAPS_GET(EDGE_WAKEUP_SUPPORTED) if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) { return ESP_ERR_INVALID_ARG; // Dont support this mode. } -#endif //!SOC_RTCIO_EDGE_WAKE_SUPPORTED +#endif //!RTC_GPIO_CAPS_GET(EDGE_WAKEUP_SUPPORTED) RTCIO_ENTER_CRITICAL(); rtcio_hal_wakeup_enable(rtc_io_number_get(gpio_num), intr_type); RTCIO_EXIT_CRITICAL(); diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c index 097bcd08a02..a9ab9c8be35 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c @@ -12,6 +12,7 @@ #include "unity_test_utils.h" #include "esp_rom_sys.h" #include "soc/soc_caps_full.h" +#include "hal/dedic_gpio_caps.h" #include "hal/dedic_gpio_periph.h" #include "hal/dedic_gpio_cpu_ll.h" #include "driver/gpio.h" @@ -19,9 +20,9 @@ TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]") { - const int test_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2] = {0}; - const int test2_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2 + 1] = {0}; - const int test3_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) + 1] = {0}; + const int test_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2] = {0}; + const int test2_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2 + 1] = {0}; + const int test3_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) + 1] = {0}; dedic_gpio_bundle_handle_t test_bundle, test_bundle2, test_bundle3 = NULL; dedic_gpio_bundle_config_t bundle_config = { .gpio_array = test_gpios, @@ -48,7 +49,7 @@ TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]") TEST_ASSERT_EQUAL_MESSAGE(ESP_OK, dedic_gpio_new_bundle(&bundle_config, &test_bundle), "create bundle with half channels failed"); uint32_t mask = 0; TEST_ESP_OK(dedic_gpio_get_out_mask(test_bundle, &mask)); - TEST_ASSERT_EQUAL_MESSAGE((1 << (SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2)) - 1, mask, "wrong out mask"); + TEST_ASSERT_EQUAL_MESSAGE((1 << (DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2)) - 1, mask, "wrong out mask"); TEST_ESP_OK(dedic_gpio_get_in_mask(test_bundle, &mask)); TEST_ASSERT_EQUAL_MESSAGE(0, mask, "wrong in mask"); diff --git a/components/esp_driver_sdm/src/sdm.c b/components/esp_driver_sdm/src/sdm.c index 0cc91805a43..924d4cdfbef 100644 --- a/components/esp_driver_sdm/src/sdm.c +++ b/components/esp_driver_sdm/src/sdm.c @@ -23,6 +23,7 @@ #include "esp_clk_tree.h" #include "driver/gpio.h" #include "driver/sdm.h" +#include "hal/sdm_caps.h" #include "hal/sdm_periph.h" #include "hal/sdm_hal.h" #include "hal/sdm_ll.h" @@ -50,15 +51,15 @@ typedef struct sdm_channel_t sdm_channel_t; struct sdm_platform_t { _lock_t mutex; // platform level mutex lock - sdm_group_t *groups[SOC_SDM_ATTR(INST_NUM)]; // sdm group pool - int group_ref_counts[SOC_SDM_ATTR(INST_NUM)];// reference count used to protect group install/uninstall + sdm_group_t *groups[SDM_CAPS_GET(INST_NUM)]; // sdm group pool + int group_ref_counts[SDM_CAPS_GET(INST_NUM)];// reference count used to protect group install/uninstall }; struct sdm_group_t { int group_id; // Group ID, index from 0 portMUX_TYPE spinlock; // to protect per-group register level concurrent access sdm_hal_context_t hal; // hal context - sdm_channel_t *channels[SOC_SDM_ATTR(CHANS_PER_INST)]; // array of sdm channels + sdm_channel_t *channels[SDM_CAPS_GET(CHANS_PER_INST)]; // array of sdm channels sdm_clock_source_t clk_src; // Clock source #if CONFIG_PM_ENABLE esp_pm_lock_handle_t pm_lock; // PM lock, to prevent the system going into light sleep when SDM is running @@ -162,11 +163,11 @@ static sdm_group_t *sdm_acquire_group_handle(int group_id, sdm_clock_source_t cl ESP_LOGD(TAG, "new group (%d) at %p", group_id, group); #if CONFIG_PM_ENABLE esp_pm_lock_type_t pm_type = ESP_PM_NO_LIGHT_SLEEP; -#if SDM_LL_FUNC_CLOCK_SUPPORT_APB +#if SDM_CAPS_GET(FUNC_CLOCK_SUPPORT_APB) if (clk_src == SDM_CLK_SRC_APB) { pm_type = ESP_PM_APB_FREQ_MAX; } -#endif // SDM_LL_FUNC_CLOCK_SUPPORT_APB +#endif // SDM_CAPS_GET(FUNC_CLOCK_SUPPORT_APB) if (esp_pm_lock_create(pm_type, 0, soc_sdm_signals[group_id].module_name, &group->pm_lock) != ESP_OK) { ESP_LOGE(TAG, "fail to create PM lock for group %d", group_id); } @@ -216,12 +217,12 @@ static esp_err_t sdm_register_to_group(sdm_channel_t *chan, sdm_clock_source_t c { sdm_group_t *group = NULL; int chan_id = -1; - for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) { + for (int i = 0; i < SDM_CAPS_GET(INST_NUM); i++) { group = sdm_acquire_group_handle(i, clk_src); ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no mem for group (%d)", i); // loop to search free unit in the group portENTER_CRITICAL(&group->spinlock); - for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) { + for (int j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++) { if (!group->channels[j]) { chan_id = j; group->channels[j] = chan; diff --git a/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp b/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp index 4940c0c218e..ea77cfd0dd1 100644 --- a/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp +++ b/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp @@ -11,6 +11,7 @@ #include "unity.h" #include "driver/sdm.h" #include "hal/sdm_periph.h" +#include "hal/sdm_caps.h" #include "esp_attr.h" TEST_CASE("sdm_channel_install_uninstall", "[sdm]") @@ -25,17 +26,17 @@ TEST_CASE("sdm_channel_install_uninstall", "[sdm]") .allow_pd = false, }, }; - sdm_channel_handle_t chans[SOC_SDM_ATTR(INST_NUM)][SOC_SDM_ATTR(CHANS_PER_INST)] = {}; - for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) { - for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) { + sdm_channel_handle_t chans[SDM_CAPS_GET(INST_NUM)][SDM_CAPS_GET(CHANS_PER_INST)] = {}; + for (int i = 0; i < SDM_CAPS_GET(INST_NUM); i++) { + for (int j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++) { TEST_ESP_OK(sdm_new_channel(&config, &chans[i][j])); } TEST_ESP_ERR(ESP_ERR_NOT_FOUND, sdm_new_channel(&config, &chans[0][0])); } printf("delete sdm channels\r\n"); - for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) { - for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) { + for (int i = 0; i < SDM_CAPS_GET(INST_NUM); i++) { + for (int j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++) { TEST_ESP_OK(sdm_del_channel(chans[i][j])); } } diff --git a/components/esp_hal_gpio/esp32/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32/include/hal/gpio_caps.h new file mode 100644 index 00000000000..960a06d7042 --- /dev/null +++ b/components/esp_hal_gpio/esp32/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_MATRIX_DELAY_NS 25 /* the gpio matrix signal routing const time */ diff --git a/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h index 7a94f87366a..234de25f0c6 100644 --- a/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h @@ -28,9 +28,6 @@ // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) -// the gpio matrix signal routing const time -#define GPIO_LL_MATRIX_DELAY_NS 25 - #define GPIO_LL_APP_CPU_INTR_ENA (BIT(0)) #define GPIO_LL_APP_CPU_NMI_INTR_ENA (BIT(1)) #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(2)) diff --git a/components/esp_hal_gpio/esp32/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32/include/hal/sdm_caps.h new file mode 100644 index 00000000000..fe517ba2211 --- /dev/null +++ b/components/esp_hal_gpio/esp32/include/hal/sdm_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 8 /* Number of channels in each SDM instance */ +#define _SDM_FUNC_CLOCK_SUPPORT_APB 1 /* SDM function clock can be sourced from APB */ diff --git a/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h index 502d49d4a1c..02081cc9d5b 100644 --- a/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h @@ -17,9 +17,6 @@ #define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1) -// Support APB as function clock -#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h index 74eec52ce92..e3c67f91f23 100644 --- a/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c2/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c2/include/hal/gpio_caps.h new file mode 100644 index 00000000000..97e5df2225e --- /dev/null +++ b/components/esp_hal_gpio/esp32c2/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_FILTER_CLK_SUPPORT_APB 1 diff --git a/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h index 049b212ee31..c342299a8ba 100644 --- a/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c3/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c3/include/hal/gpio_caps.h new file mode 100644 index 00000000000..97e5df2225e --- /dev/null +++ b/components/esp_hal_gpio/esp32c3/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_FILTER_CLK_SUPPORT_APB 1 diff --git a/components/esp_hal_gpio/esp32c3/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32c3/include/hal/sdm_caps.h new file mode 100644 index 00000000000..7839dcc335f --- /dev/null +++ b/components/esp_hal_gpio/esp32c3/include/hal/sdm_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ +#define _SDM_FUNC_CLOCK_SUPPORT_APB 1 /* SDM function clock can be sourced from APB */ diff --git a/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h index 63a4d75b446..e5d14f48c85 100644 --- a/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h @@ -17,9 +17,6 @@ #define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1) -// Support APB as function clock -#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h index fd955da5656..0cce6ab497b 100644 --- a/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c5/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32c5/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h index 52a06e7fc3e..0e85a7f2aa3 100644 --- a/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h index f1f5622dfce..d70c2364e91 100644 --- a/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h @@ -15,8 +15,9 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V + 1) #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32c5/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32c5/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32c5/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32c5/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32c5/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32c5/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h index fd955da5656..0cce6ab497b 100644 --- a/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c6/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32c6/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h index 50b98b95a84..1608eff7130 100644 --- a/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h index 86d52ba43da..7f8f2387367 100644 --- a/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h @@ -15,9 +15,10 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" // the max window size is expected to be 64, but due to a hardware issue, we need to limit it to 63 -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 63 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32c6/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32c6/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32c6/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32c6/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32c6/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32c6/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h index fd955da5656..0cce6ab497b 100644 --- a/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c61/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c61/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32c61/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h index 52a06e7fc3e..0e85a7f2aa3 100644 --- a/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c61/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32c61/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32c61/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h index 014605bae91..41b6c91bcb6 100644 --- a/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h2/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32h2/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h index 49281c3366f..44077aff549 100644 --- a/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h index 5d19a96188f..c81d1b0c1c5 100644 --- a/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h @@ -15,9 +15,10 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" // the max window size is expected to be 64, but due to a hardware issue, we need to limit it to 63 -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 63 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32h2/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32h2/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32h2/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32h2/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32h2/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32h2/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h index c982d3e2b60..ac07b357a6b 100644 --- a/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h21/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32h21/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h index ba4e7fd73ff..4885ee3e164 100644 --- a/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h index 45546d2ff93..4f53a17d859 100644 --- a/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h @@ -9,8 +9,9 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V + 1) #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32h21/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32h21/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32h21/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32h21/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32h21/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32h21/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h index c982d3e2b60..ac07b357a6b 100644 --- a/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h4/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32h4/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h index 45d1433d11e..6b4162225ab 100644 --- a/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h index 69944fc0d30..7383e8c3d9f 100644 --- a/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h @@ -9,8 +9,9 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V + 1) #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32h4/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32h4/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32h4/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32h4/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32h4/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32h4/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..8df3815d517 --- /dev/null +++ b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h index 0abb50c15d2..6a7434e1ab9 100644 --- a/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32p4/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32p4/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h index 49281c3366f..44077aff549 100644 --- a/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h index 8799ec6d3f9..cc95ba73205 100644 --- a/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h @@ -9,8 +9,9 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V + 1) #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32p4/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32p4/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32p4/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32p4/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32p4/include/hal/sdm_caps.h new file mode 100644 index 00000000000..9ccd64b34ec --- /dev/null +++ b/components/esp_hal_gpio/esp32p4/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 8 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..ec92fb90fa2 --- /dev/null +++ b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +#define _DEDIC_GPIO_ALLOW_REG_ACCESS 1 /*!< Allow access dedicated GPIO channel by register */ diff --git a/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h index d377896cf8e..e8f83dcd202 100644 --- a/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h @@ -11,8 +11,6 @@ #include "soc/dedic_gpio_struct.h" #include "soc/system_reg.h" -#define DEDIC_GPIO_LL_ALLOW_REG_ACCESS 1 /*!< Allow access dedicated GPIO channel by register */ - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32s2/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32s2/include/hal/gpio_caps.h new file mode 100644 index 00000000000..97e5df2225e --- /dev/null +++ b/components/esp_hal_gpio/esp32s2/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_FILTER_CLK_SUPPORT_APB 1 diff --git a/components/esp_hal_gpio/esp32s2/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32s2/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32s2/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32s2/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32s2/include/hal/sdm_caps.h new file mode 100644 index 00000000000..fe517ba2211 --- /dev/null +++ b/components/esp_hal_gpio/esp32s2/include/hal/sdm_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 8 /* Number of channels in each SDM instance */ +#define _SDM_FUNC_CLOCK_SUPPORT_APB 1 /* SDM function clock can be sourced from APB */ diff --git a/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h index d4cb9a1ae23..591acb8140c 100644 --- a/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h @@ -17,9 +17,6 @@ #define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1) -// Support APB as function clock -#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..606b0bea769 --- /dev/null +++ b/components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/esp_hal_gpio/esp32s3/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32s3/include/hal/gpio_caps.h new file mode 100644 index 00000000000..97e5df2225e --- /dev/null +++ b/components/esp_hal_gpio/esp32s3/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_FILTER_CLK_SUPPORT_APB 1 diff --git a/components/esp_hal_gpio/esp32s3/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32s3/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32s3/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32s3/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32s3/include/hal/sdm_caps.h new file mode 100644 index 00000000000..fe517ba2211 --- /dev/null +++ b/components/esp_hal_gpio/esp32s3/include/hal/sdm_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 8 /* Number of channels in each SDM instance */ +#define _SDM_FUNC_CLOCK_SUPPORT_APB 1 /* SDM function clock can be sourced from APB */ diff --git a/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h index 9965358f632..86d757688ab 100644 --- a/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h @@ -17,9 +17,6 @@ #define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1) -// Support APB as function clock -#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h b/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h index fe32aa9a8b4..8cc727dd160 100644 --- a/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h +++ b/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h @@ -15,14 +15,13 @@ extern "C" { #endif #if SOC_HAS(DEDICATED_GPIO) -// helper macros to access module attributes -#define SOC_DEDIC_GPIO_ATTR(_attr) SOC_MODULE_ATTR(DEDIC_GPIO, _attr) +#include "hal/dedic_gpio_caps.h" typedef struct { const int irq; // Interrupt resource (-1 means no interrupt supported) struct { - const int in_sig_per_channel[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; - const int out_sig_per_channel[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)]; + const int in_sig_per_channel[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; + const int out_sig_per_channel[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)]; } cores[SOC_CPU_CORES_NUM]; // Signals routed to/from GPIO matrix } dedic_gpio_signal_conn_t; diff --git a/components/esp_hal_gpio/include/hal/sdm_periph.h b/components/esp_hal_gpio/include/hal/sdm_periph.h index 65f37a3dd91..27cff9cbc80 100644 --- a/components/esp_hal_gpio/include/hal/sdm_periph.h +++ b/components/esp_hal_gpio/include/hal/sdm_periph.h @@ -16,23 +16,21 @@ #include "soc/retention_periph_defs.h" #endif // SOC_HAS(PAU) -// helper macros to access module attributes -#define SOC_SDM_ATTR(_attr) SOC_MODULE_ATTR(SDM, _attr) - #ifdef __cplusplus extern "C" { #endif #if SOC_HAS(SDM) +#include "hal/sdm_caps.h" typedef struct { const char *module_name; // Module name struct { const int sig_id_matrix; // signal ID in the GPIO matrix - } channels[SOC_SDM_ATTR(CHANS_PER_INST)]; + } channels[SDM_CAPS_GET(CHANS_PER_INST)]; } soc_sdm_signal_desc_t; -extern const soc_sdm_signal_desc_t soc_sdm_signals[SOC_SDM_ATTR(INST_NUM)]; +extern const soc_sdm_signal_desc_t soc_sdm_signals[SDM_CAPS_GET(INST_NUM)]; #if SOC_HAS(PAU) @@ -42,7 +40,7 @@ typedef struct { const size_t array_size; // Size of the regdma_entry_array } soc_sdm_retention_desc_t; -extern const soc_sdm_retention_desc_t soc_sdm_retention_infos[SOC_SDM_ATTR(INST_NUM)]; +extern const soc_sdm_retention_desc_t soc_sdm_retention_infos[SDM_CAPS_GET(INST_NUM)]; #endif // SOC_HAS(PAU) diff --git a/components/esp_hal_mspi/CMakeLists.txt b/components/esp_hal_mspi/CMakeLists.txt index 21f45931725..3fc892961b2 100644 --- a/components/esp_hal_mspi/CMakeLists.txt +++ b/components/esp_hal_mspi/CMakeLists.txt @@ -4,6 +4,11 @@ idf_build_get_property(esp_tee_build ESP_TEE_BUILD) set(srcs) set(includes "include" "${target}/include") +set(priv_requires) +if(${target} STREQUAL "esp32") + list(APPEND priv_requires esp_hal_gpio) +endif() + if(esp_tee_build) if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1) list(APPEND srcs "spi_flash_hal.c" "spi_flash_hal_iram.c") @@ -26,4 +31,5 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} - REQUIRES soc hal) + REQUIRES soc hal + PRIV_REQUIRES "${priv_requires}") diff --git a/components/esp_hal_mspi/spi_flash_hal.c b/components/esp_hal_mspi/spi_flash_hal.c index 101ac5154bb..5a9f443a436 100644 --- a/components/esp_hal_mspi/spi_flash_hal.c +++ b/components/esp_hal_mspi/spi_flash_hal.c @@ -11,7 +11,7 @@ #include #include #include "soc/soc_caps.h" -#include "hal/gpio_ll.h" //for GPIO_LL_MATRIX_DELAY_NS +#include "hal/gpio_caps.h" //for GPIO_CAPS_GET(MATRIX_DELAY_NS) #include "hal/spi_flash_hal.h" #include "hal/assert.h" #include "hal/log.h" @@ -66,8 +66,8 @@ static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk //calculate how many apb clocks a period has const int apbclk_n = APB_CLK_FREQ / eff_clk; int gpio_delay_ns = 0; -#if GPIO_LL_MATRIX_DELAY_NS - gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#if GPIO_CAPS_GET(MATRIX_DELAY_NS) + gpio_delay_ns = gpio_is_used ? GPIO_CAPS_GET(MATRIX_DELAY_NS) : 0; #endif //calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 6e0dba99eae..4f74be5e7ea 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -170,6 +170,7 @@ elseif(NOT BOOTLOADER_BUILD) endif() if(CONFIG_SOC_GPSPI_SUPPORTED) + # Remember to add esp_hal_gpio to esp_hal_spi PRIV_REQUIRES!!! list(APPEND srcs "spi_hal.c" "spi_hal_iram.c" diff --git a/components/hal/spi_hal_iram.c b/components/hal/spi_hal_iram.c index cfde4fd5182..f77ec2f7528 100644 --- a/components/hal/spi_hal_iram.c +++ b/components/hal/spi_hal_iram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ #include "hal/spi_hal.h" #include "hal/log.h" #include "hal/assert.h" -#include "hal/gpio_ll.h" //for GPIO_LL_MATRIX_DELAY_NS +#include "hal/gpio_caps.h" //for GPIO_CAPS_GET(MATRIX_DELAY_NS) #include "soc/ext_mem_defs.h" #include "soc/soc_caps.h" @@ -75,8 +75,8 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int //how many apb clocks a period has const int spiclk_apb_n = source_freq_hz / eff_clk; int gpio_delay_ns = 0; -#if GPIO_LL_MATRIX_DELAY_NS - gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#if GPIO_CAPS_GET(MATRIX_DELAY_NS) + gpio_delay_ns = gpio_is_used ? GPIO_CAPS_GET(MATRIX_DELAY_NS) : 0; #endif //how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. @@ -109,8 +109,8 @@ int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns) { const int apbclk_kHz = APB_CLK_FREQ / 1000; int gpio_delay_ns = 0; -#if GPIO_LL_MATRIX_DELAY_NS - gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#if GPIO_CAPS_GET(MATRIX_DELAY_NS) + gpio_delay_ns = gpio_is_used ? GPIO_CAPS_GET(MATRIX_DELAY_NS) : 0; #endif //how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 39c9bd8fc9a..a8903e7de89 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -180,10 +180,6 @@ #define SOC_GPIO_PORT (1U) #define SOC_GPIO_PIN_COUNT 40 -// SOC_GPIO_SUPPORT_RTC_INDEPENDENT not defined. On ESP32 those PADs which have RTC functions must -// set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to -// control pullup/down/capability, independent with RTC registers. - // 0~39 valid except 24, 28~31 #define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31)) // GPIO >= 34 are input only diff --git a/components/soc/esp32/include/soc/soc_caps_full.h b/components/soc/esp32/include/soc/soc_caps_full.h index 5eaba84584c..8e64cba1c70 100644 --- a/components/soc/esp32/include/soc/soc_caps_full.h +++ b/components/soc/esp32/include/soc/soc_caps_full.h @@ -9,9 +9,5 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance - /*------------------------------- Touch Sensor ------------------------------------*/ #define _SOC_CAPS_TOUCH_CHAN_NUM 10 // Number of touch sensor channels diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 4f0620fa26a..bd0b5055093 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -283,10 +283,6 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index e12c2d482cc..6a1e185aca6 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -124,7 +124,6 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 21 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 // Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins) diff --git a/components/soc/esp32c2/include/soc/soc_caps_full.h b/components/soc/esp32c2/include/soc/soc_caps_full.h index 185c9ed19f9..ca1d6414d90 100644 --- a/components/soc/esp32c2/include/soc/soc_caps_full.h +++ b/components/soc/esp32c2/include/soc/soc_caps_full.h @@ -8,7 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 7b13f91ad2d..6879a0145ef 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -379,10 +379,6 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 19d4c25b6ba..1d2ee74d59b 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -163,7 +163,6 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 22 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 // Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins) diff --git a/components/soc/esp32c3/include/soc/soc_caps_full.h b/components/soc/esp32c3/include/soc/soc_caps_full.h index 2dd4e7932c0..ca1d6414d90 100644 --- a/components/soc/esp32c3/include/soc/soc_caps_full.h +++ b/components/soc/esp32c3/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 05661030505..ca151f8d360 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -555,10 +555,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y @@ -623,10 +619,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 7cf47cb950c..b1313a95c96 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -219,8 +219,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem -// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // GPIO0~7 on ESP32C5 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // LP IO peripherals have independent clock gating to manage @@ -256,7 +254,6 @@ */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 diff --git a/components/soc/esp32c5/include/soc/soc_caps_full.h b/components/soc/esp32c5/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32c5/include/soc/soc_caps_full.h +++ b/components/soc/esp32c5/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 5e94b8ec6a6..2e6785ae6ff 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -475,10 +475,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y @@ -543,10 +539,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 88ebb7e8b15..b29be2880f5 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -194,8 +194,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem -// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // GPIO0~7 on ESP32C6 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // LP IO peripherals have independent clock gating to manage @@ -231,7 +229,6 @@ */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 diff --git a/components/soc/esp32c6/include/soc/soc_caps_full.h b/components/soc/esp32c6/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32c6/include/soc/soc_caps_full.h +++ b/components/soc/esp32c6/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index bc99bec18d9..4db0ed97667 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -431,10 +431,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y @@ -499,10 +495,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_ANA_CMPR_NUM int default 1 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index ab325171cf6..26132f13643 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -177,8 +177,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem -// On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // LP IO peripherals have independent clock gating to manage #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) @@ -215,7 +213,6 @@ */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*------------------------- Analog Comparator CAPS ---------------------------*/ #define SOC_ANA_CMPR_NUM (1U) diff --git a/components/soc/esp32c61/include/soc/soc_caps_full.h b/components/soc/esp32c61/include/soc/soc_caps_full.h index 185c9ed19f9..ca1d6414d90 100644 --- a/components/soc/esp32c61/include/soc/soc_caps_full.h +++ b/components/soc/esp32c61/include/soc/soc_caps_full.h @@ -8,7 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 633711f08e2..751b58d43f8 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -507,10 +507,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 57563c2993a..fafa48bcf70 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -220,9 +220,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins) -// Digital IOs have their own registers to control pullup/down/capability -// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // LP IO peripherals have independent clock gating to manage #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) diff --git a/components/soc/esp32h2/include/soc/soc_caps_full.h b/components/soc/esp32h2/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32h2/include/soc/soc_caps_full.h +++ b/components/soc/esp32h2/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 4384253e2bd..2b24aaca173 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -399,10 +399,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index ad0da4fca0e..d10a369e597 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -202,9 +202,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has no full LP IO subsystem, GPIO5~11 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins) -// Digital IOs have their own registers to control pullup/down/capability -// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // LP IO peripherals have independent clock gating to manage #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) diff --git a/components/soc/esp32h21/include/soc/soc_caps_full.h b/components/soc/esp32h21/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32h21/include/soc/soc_caps_full.h +++ b/components/soc/esp32h21/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 605b50bcc6b..bfb0ddf52c0 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -351,10 +351,6 @@ config SOC_GPIO_ETM_TASKS_PER_GROUP int default 8 -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y @@ -395,10 +391,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 458ffc11b83..6b2abd9d942 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -218,8 +218,6 @@ #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 // Target has the full LP IO subsystem -// On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1 // LP IO peripherals have independent clock gating to manage #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) @@ -246,7 +244,6 @@ when the pins are switched to RTC function. */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 diff --git a/components/soc/esp32h4/include/soc/soc_caps_full.h b/components/soc/esp32h4/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32h4/include/soc/soc_caps_full.h +++ b/components/soc/esp32h4/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 93ed278ace3..028eb125539 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -671,10 +671,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y @@ -755,10 +751,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index e97b33a7064..b5545d36d1d 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -250,8 +250,7 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem -// On ESP32-P4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) + // GPIO0~15 on ESP32P4 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1) @@ -292,7 +291,6 @@ */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 diff --git a/components/soc/esp32p4/include/soc/soc_caps_full.h b/components/soc/esp32p4/include/soc/soc_caps_full.h index 33259a694d3..655b7649040 100644 --- a/components/soc/esp32p4/include/soc/soc_caps_full.h +++ b/components/soc/esp32p4/include/soc/soc_caps_full.h @@ -9,13 +9,5 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance - /*------------------------------- Touch Sensor ------------------------------------*/ #define _SOC_CAPS_TOUCH_CHAN_NUM 14 // Number of touch sensor channels diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 6e4533574f7..088f8f0fb02 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -379,14 +379,6 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index d50c1c3c1b2..701af3e4461 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -167,11 +167,7 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 47 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 -// On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register. -// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // Force hold is a new function of ESP32-S2 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) diff --git a/components/soc/esp32s2/include/soc/soc_caps_full.h b/components/soc/esp32s2/include/soc/soc_caps_full.h index a79d5014ac5..1cedce872cd 100644 --- a/components/soc/esp32s2/include/soc/soc_caps_full.h +++ b/components/soc/esp32s2/include/soc/soc_caps_full.h @@ -9,13 +9,5 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - /*------------------------------- Touch Sensor ------------------------------------*/ #define _SOC_CAPS_TOUCH_CHAN_NUM 15 // Number of touch sensor channels diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index fcef9d594bc..5a062d5c0e0 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -443,14 +443,6 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 09cb7e37a52..c6415e6d634 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -179,10 +179,7 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 49 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 -// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // Force hold is a new function of ESP32-S3 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) diff --git a/components/soc/esp32s3/include/soc/soc_caps_full.h b/components/soc/esp32s3/include/soc/soc_caps_full.h index a79d5014ac5..1cedce872cd 100644 --- a/components/soc/esp32s3/include/soc/soc_caps_full.h +++ b/components/soc/esp32s3/include/soc/soc_caps_full.h @@ -9,13 +9,5 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - /*------------------------------- Touch Sensor ------------------------------------*/ #define _SOC_CAPS_TOUCH_CHAN_NUM 15 // Number of touch sensor channels