fix(ulp): record wakeup causes before lp core request sleep

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -1614,3 +1614,7 @@ config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
 config SOC_LP_CORE_SUPPORT_I2C
     bool
     default y
+
+config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
+    bool
+    default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -645,3 +645,4 @@
 #define SOC_LP_CORE_SUPPORT_ETM                     (1) /*!< LP Core supports ETM */
 #define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS   (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
 #define SOC_LP_CORE_SUPPORT_I2C                     (1) /*!< LP Core supports I2C */
+#define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -1363,6 +1363,10 @@ config SOC_LP_CORE_SUPPORT_I2C
     bool
     default y
 
+config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
+    bool
+    default y
+
 config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -554,6 +554,7 @@
 #define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR   (1) /*!< LP Core interrupts all map to a single entry in vector table */
 #define SOC_LP_CORE_SUPPORT_ETM               (1) /*!< LP Core supports ETM */
 #define SOC_LP_CORE_SUPPORT_I2C               (1) /*!< LP Core supports I2C */
+#define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE    (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
 
 /*------------------------------------- DEBUG CAPS -------------------------------------*/
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1922,3 +1922,7 @@ config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
 config SOC_LP_CORE_SUPPORT_I2C
     bool
     default y
+
+config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
+    bool
+    default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -736,3 +736,4 @@
 #define SOC_LP_CORE_SUPPORT_LP_ADC                  (1) /*!< LP ADC can be accessed from the LP-Core */
 #define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS   (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
 #define SOC_LP_CORE_SUPPORT_I2C                     (1) /*!< LP Core supports I2C */
+#define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */

components/soc/esp32s31/include/soc/Kconfig.soc_caps.in

@@ -1091,6 +1091,10 @@ config SOC_LP_CORE_CONFIGURABLE_BOOT_ADDR
     bool
     default y
 
+config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
+    bool
+    default y
+
 config SOC_LP_TIMER_BIT_WIDTH_LO
     int
     default 32

components/soc/esp32s31/include/soc/soc_caps.h

@@ -457,6 +457,7 @@
 #define SOC_LP_CORE_SUPPORT_ETM                     (1) /*!< LP Core supports ETM wakeup */
 #define SOC_LP_CORE_CONFIGURABLE_BOOT_ADDR          (1) /*!< LP Core has no LP ROM; HP must write the reset_vector address (LP_RAM_BASE+0x80) to LP_SYS.lp_core_boot_addr before triggering LP wake */
 //#define SOC_LP_CORE_SUPPORT_I2C                     (1) /*!< LP Core supports I2C */ TODO IDF-14635
+#define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
 
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part