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refactor(i3c): Move i3c hal to seperate folder
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use in application code.
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* See readme.md in hal/readme.md
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******************************************************************************/
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// The HAL layer for I3C master
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#pragma once
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#include "soc/soc_caps.h"
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#if SOC_I3C_MASTER_SUPPORTED
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#include "hal/i3c_master_types.h"
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#include "hal/i3c_master_ll.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_I3C_MASTER_SUPPORTED
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typedef struct i3c_mst_dev_t *i3c_master_soc_handle_t; // I3C master SOC layer handle
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/**
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* @brief I3C master hal Context definition
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*/
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typedef struct {
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i3c_master_soc_handle_t dev;
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} i3c_master_hal_context_t;
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/**
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* @brief Initialize the I3C master HAL context
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*
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* @param hal HAL context
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* @param i3c_port I3C port number
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*/
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void i3c_master_hal_init(i3c_master_hal_context_t *hal, int i3c_port);
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/**
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* @brief Deinitialize the I3C master HAL context
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*
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* @param hal HAL context
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*/
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void i3c_master_hal_deinit(i3c_master_hal_context_t *hal);
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#endif
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#ifdef __cplusplus
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}
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#endif
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@@ -1,113 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc_caps.h"
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#include "soc/clk_tree_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I3C_MASTER_IBI_DATA_SIZE_MAX (32)
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#if SOC_I3C_MASTER_SUPPORTED
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/**
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* @brief I2C group clock source
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*/
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typedef soc_periph_i3c_master_clk_src_t i3c_master_clock_source_t;
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#else
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/**
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* @brief default type
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*/
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typedef int i3c_master_clock_source_t;
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#endif
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/**
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* @brief I3C Common Command Code (CCC) enumeration
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*
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* This enumeration defines all I3C CCC command codes as per MIPI I3C specification.
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*/
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typedef enum {
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I3C_CCC_ENEC = 0x00, ///< Enable Events Command
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I3C_CCC_DISEC = 0x01, ///< Disable Events Command
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I3C_CCC_ENTAS0 = 0x02, ///< Enable Target Activity State 0
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I3C_CCC_ENTAS1 = 0x03, ///< Enable Target Activity State 1
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I3C_CCC_ENTAS2 = 0x04, ///< Enable Target Activity State 2
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I3C_CCC_ENTAS3 = 0x05, ///< Enable Target Activity State 3
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I3C_CCC_RSTDAA = 0x06, ///< Reset Dynamic Address Assignment
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I3C_CCC_ENTDAA = 0x07, ///< Enter Dynamic Address Assignment
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I3C_CCC_DEFTGTS = 0x08, ///< Define List of Targets
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I3C_CCC_SETMWL = 0x09, ///< Set Max Write Length
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I3C_CCC_SETMRL = 0x0A, ///< Set Max Read Length
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I3C_CCC_ENTTM = 0x0B, ///< Enter Test Mode
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I3C_CCC_SETBUSCON = 0x0C, ///< Set Bus Context
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/* 0x0D Reserved */
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I3C_CCC_ENDXFER = 0x0E, ///< End Data Transfer
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I3C_CCC_ENTHDR0 = 0x20, ///< Enter HDR Mode 0 (DDR)
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I3C_CCC_ENTHDR1 = 0x21, ///< Enter HDR Mode 1 (TSP)
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I3C_CCC_ENTHDR2 = 0x22, ///< Enter HDR Mode 2 (TSL)
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I3C_CCC_ENTHDR3 = 0x23, ///< Enter HDR Mode 3
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I3C_CCC_ENTHDR4 = 0x24, ///< Enter HDR Mode 4
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I3C_CCC_ENTHDR5 = 0x25, ///< Enter HDR Mode 5
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I3C_CCC_ENTHDR6 = 0x26, ///< Enter HDR Mode 6
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I3C_CCC_ENTHDR7 = 0x27, ///< Enter HDR Mode 7
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I3C_CCC_SETXTIME = 0x28, ///< Set Exchange Timing Information
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I3C_CCC_SETAASA = 0x29, ///< Set All Addresses to Static Addresses
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I3C_CCC_RSTACT = 0x2A, ///< Target Reset Action
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I3C_CCC_DEFGRPA = 0x2B, ///< Define List of Group Address
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I3C_CCC_RSTGRPA = 0x2C, ///< Reset Group Address(es)
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I3C_CCC_MLANE = 0x2D, ///< Multi-Lane Data Transfer Control
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I3C_CCC_ENEC_DIRECT = 0x80, ///< Enable Events Command (Direct)
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I3C_CCC_DISEC_DIRECT = 0x81, ///< Disable Events Command (Direct)
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I3C_CCC_ENTAS0_DIRECT = 0x82, ///< Enable Target Activity State 0 (Direct)
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I3C_CCC_ENTAS1_DIRECT = 0x83, ///< Enable Target Activity State 1 (Direct)
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I3C_CCC_ENTAS2_DIRECT = 0x84, ///< Enable Target Activity State 2 (Direct)
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I3C_CCC_ENTAS3_DIRECT = 0x85, ///< Enable Target Activity State 3 (Direct)
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I3C_CCC_RSTDAA_DIRECT = 0x86, ///< Reset Dynamic Address Assignment (Direct)
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I3C_CCC_SETDASA = 0x87, ///< Set Dynamic Address from Static Address
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I3C_CCC_SETNEWDA = 0x88, ///< Set New Dynamic Address
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I3C_CCC_SETMWL_DIRECT = 0x89, ///< Set Max Write Length (Direct)
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I3C_CCC_SETMRL_DIRECT = 0x8A, ///< Set Max Read Length (Direct)
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I3C_CCC_GETMWL = 0x8B, ///< Get Max Write Length
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I3C_CCC_GETMRL = 0x8C, ///< Get Max Read Length
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I3C_CCC_GETPID = 0x8D, ///< Get Provisional ID
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I3C_CCC_GETBCR = 0x8E, ///< Get Bus Characteristics Register
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I3C_CCC_GETDCR = 0x8F, ///< Get Device Characteristics Register
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I3C_CCC_GETSTATUS = 0x90, ///< Get Device Status
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I3C_CCC_GETACCMST = 0x91, ///< Get Accept Controller Role
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I3C_CCC_SETBRGTGT = 0x93, ///< Set Bridge Targets
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I3C_CCC_GETMXDS = 0x94, ///< Get Max Data Speed
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I3C_CCC_GETCAPS = 0x95, ///< Get Optional Feature Capabilities
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I3C_CCC_SETROUTE = 0x96, ///< Set Route
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I3C_CCC_D2DXFER = 0x97, ///< Device to Device(s) Tunneling Control
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I3C_CCC_SETXTIME_DIRECT = 0x98, ///< Set Exchange Timing Information (Direct)
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I3C_CCC_GETXTIME = 0x99, ///< Get Exchange Timing Information
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I3C_CCC_RSTACT_DIRECT = 0x9A, ///< Target Reset Action (Direct)
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I3C_CCC_SETGRPA = 0x9B, ///< Set Group Address
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I3C_CCC_RSTGRPA_DIRECT = 0x9C, ///< Reset Group Address (Direct)
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I3C_CCC_MLANE_DIRECT = 0x9D, ///< Multi-Lane Data Transfer Control (Direct)
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} i3c_ccc_code_t;
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/**
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* @brief I3C internal pull-up resistor value
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*/
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typedef enum {
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I3C_MASTER_INTERNAL_PULLUP_RESISTOR_DISABLED = 0, /*!< Internal pull-up resistor disabled */
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I3C_MASTER_INTERNAL_PULLUP_RESISTOR_0_3K = 1, /*!< Internal pull-up resistor 0.3K */
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I3C_MASTER_INTERNAL_PULLUP_RESISTOR_0_6K = 2, /*!< Internal pull-up resistor 0.6K */
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I3C_MASTER_INTERNAL_PULLUP_RESISTOR_1_2K = 3, /*!< Internal pull-up resistor 1.2K */
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I3C_MASTER_INTERNAL_PULLUP_RESISTOR_2_4K = 4, /*!< Internal pull-up resistor 2.4K */
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} i3c_master_internal_pullup_resistor_val_t;
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#ifdef __cplusplus
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}
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#endif
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