From 05faa941c29cff3c5c250be4b6079062c0189ed0 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Mon, 16 Feb 2026 10:15:30 +0100 Subject: [PATCH] fix(esp32c5): Do not disable UART0 sclk when USB Serial/JTAG is primary console This is a workaround for rom code issue, which can cause the chip to end in infinite loop when reset is triggered from esptool/idf-monitor. This is only applicable to ESP32-C5 rev <= 1.0. Closes https://github.com/espressif/esp-idf/issues/18089 --- components/esp_system/port/soc/esp32c5/clk.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 04556907a63..f86a08fc4e3 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -253,5 +253,15 @@ __attribute__((weak)) void esp_perip_clk_init(void) clk_gate_config.disable_pvt_clk = true; #endif +#if defined(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG) && CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG + /* ESP32-C5 rev <= 1.0: Do not disable UART0 sclk when USB Serial/JTAG is primary console. + * Disabling it would cause the chip to end in infinite loop on reset (workaround for rom code issue). + * See: IDFGH-17050 + */ + if (efuse_hal_chip_revision() <= 100) { + clk_gate_config.disable_uart0_clk = false; + } +#endif + periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config); }