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feat(esp_hal_pmu): move pau_hal driver into esp_hal_pmu component
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wuzhenghui
@@ -1,227 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-H4 PAU(Power Assist Unit) register operations
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#pragma once
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#include <stdlib.h>
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "soc/pau_reg.h"
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#include "soc/pau_struct.h"
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#include "soc/pcr_struct.h"
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#include "soc/lp_aon_struct.h"
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#include "soc/lp_aon_reg.h"
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#include "hal/pau_types.h"
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#include "hal/assert.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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static inline void pau_ll_enable_bus_clock(bool enable)
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{
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if (enable) {
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PCR.regdma_conf.regdma_clk_en = 1;
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PCR.regdma_conf.regdma_rst_en = 0;
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} else {
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PCR.regdma_conf.regdma_clk_en = 0;
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PCR.regdma_conf.regdma_rst_en = 1;
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}
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}
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static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
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{
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return LP_AON.backup_dma_cfg0.aon_regdma_error;
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}
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static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
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{
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dev->regdma_conf.link_sel = link;
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}
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static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
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{
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dev->regdma_conf.to_mem = to_mem ? 1 : 0;
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}
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static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable)
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{
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dev->regdma_conf.start = enable;
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}
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static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
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{
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LP_AON.backup_dma_cfg2.aon_link_addr_aon = (uint32_t)link_addr;
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}
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static inline void pau_ll_set_regdma_timeout_link_backup_wait(pau_dev_t *dev, uint32_t thres)
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{
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REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_BACKUP_TOUT_THRES_AON, thres);
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}
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static inline void pau_ll_set_regdma_timeout_read_interval(pau_dev_t *dev, uint32_t thres)
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{
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REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG0_REG, LP_AON_READ_INTERVAL_AON, thres);
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}
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static inline void pau_ll_set_regdma_timeout_burst_limit(pau_dev_t *dev, uint32_t thres)
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{
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REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG0_REG, LP_AON_BURST_LIMIT_AON, thres);
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}
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static inline void pau_ll_set_regdma_timeout_max_link_work(pau_dev_t *dev, uint32_t thres)
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{
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REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_WORK_TOUT_THRES_AON, thres);
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}
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static inline void pau_ll_set_regdma_timeout_read_mode_try_time(pau_dev_t *dev, uint32_t thres)
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{
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REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_WAIT_TOUT_THRES_AON, thres);
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}
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static inline void pau_ll_set_regdma_branch_max_link(pau_dev_t *dev, uint32_t max_link_len)
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{
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REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_BRANCH_LINK_LENGTH_AON, max_link_len);
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}
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static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
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{
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return dev->regdma_current_link_addr.val;
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}
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static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
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{
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return dev->regdma_peri_addr.val;
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}
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static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
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{
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return dev->regdma_mem_addr.val;
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}
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static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
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{
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return dev->int_raw.val;
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}
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static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
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{
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return dev->int_st.val;
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}
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static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable)
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{
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dev->int_ena.done_int_ena = enable;
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}
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static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable)
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{
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dev->int_ena.error_int_ena = enable;
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}
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static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
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{
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dev->int_clr.val = 0x1;
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}
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static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
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{
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dev->int_clr.val = 0x2;
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}
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static inline void pau_ll_arbiter_auto_retry_enable(pau_dev_t *dev, bool ena)
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{
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dev->regdma_conf.sw_retry_en = ena;
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}
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static inline void pau_ll_arbiter_fix_priority_enable(pau_dev_t *dev, bool ena)
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{
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dev->regdma_conf.fix_pri_en = ena;
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}
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/**
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* arbiter result coding:
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* 1: mac_req
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* 2: pmu_req
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* 3: sw_req
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* 4: etm0_req
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* 5: etm1_req
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* 6: etm2_req
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* 7: etm3_req
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*/
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static inline uint32_t pau_ll_arbiter_get_start_result(pau_dev_t *dev)
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{
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return dev->regdma_grant_result.grant_start_result;
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}
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static inline uint32_t pau_ll_arbiter_get_done_result(pau_dev_t *dev)
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{
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return dev->regdma_grant_result.grant_done_result;
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}
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static inline void pau_ll_arbiter_clr_result_flag(pau_dev_t *dev)
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{
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dev->regdma_grant_result.grant_result_clr = 1;
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}
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static inline bool pau_ll_is_busy(pau_dev_t *dev)
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{
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return dev->regdma_conf.paudma_busy;
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}
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/**
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* @brief Set the maximum number of linked lists supported by REGDMA
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* @param count: the maximum number of regdma link
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*/
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static inline void pau_ll_set_regdma_link_count(int count)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count);
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}
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/**
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* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
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* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
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* @param count: the maximum number of loop
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*/
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static inline void pau_ll_set_regdma_link_loop_threshold(int count)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count);
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}
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/**
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* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
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* registers and gets stuck on the bus, a timeout will be triggered.
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* @param count: the maximum number of time
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*/
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static inline void pau_ll_set_regdma_link_reg_access_tout_threshold(int count)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count);
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}
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/**
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* @brief Set the regdma_link_addr
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* @param addr: the addr of regdma_link
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*/
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static inline void pau_ll_set_regdma_link_addr(uint32_t addr)
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{
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LP_AON.backup_dma_cfg2.aon_link_addr_aon = addr;
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}
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static inline void pau_ll_set_regdma_link_wait_retry_count(int count)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count);
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}
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static inline void pau_ll_set_regdma_link_wait_read_interval(int interval)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval);
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}
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#ifdef __cplusplus
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}
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#endif
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