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Merge branch 'feature/support_i2s_on_esp32c6' into 'master'

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i2s: support i2s on esp32c6

See merge request espressif/esp-idf!19989
This commit is contained in:
Kevin (Lao Kaiyao)
2022-09-16 12:31:24 +08:00
parent 4f1a9e436e bae4944b90
commit 04b4bc6cb5
33 changed files with 1358 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+4
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@@ -363,6 +363,10 @@ config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
components/soc/esp32c3/include/soc/clk_tree_defs.h
+2 -1
View File
@@ -206,7 +206,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief I2S clock source enum
@@ -214,6 +214,7 @@ typedef enum {
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
components/soc/esp32c3/include/soc/i2s_struct.h
+2 -2
View File
@@ -140,7 +140,7 @@ typedef volatile struct i2s_dev_s {
uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t reserved8: 18; /*Reserved*/
uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/
uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
uint32_t reserved30: 2; /*Reserved*/
};
@@ -151,7 +151,7 @@ typedef volatile struct i2s_dev_s {
uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
uint32_t reserved8: 18; /*Reserved*/
uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/
uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t reserved30: 2; /*Reserved*/
};
components/soc/esp32c3/include/soc/soc_caps.h
+1
View File
@@ -179,6 +179,7 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
components/soc/esp32c6/CMakeLists.txt
-1
View File
@@ -20,7 +20,6 @@ list(REMOVE_ITEM srcs
"adc_periph.c" # TODO: IDF-5310
"dedic_gpio_periph.c" # TODO: IDF-5331
"ledc_periph.c" # TODO: IDF-5328
"i2s_periph.c" # TODO: IDF-5314
"i2c_periph.c" # TODO: IDF-5326
"temperature_sensor_periph.c" # TODO: IDF-5322
)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+8
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@@ -43,6 +43,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@@ -287,6 +291,10 @@ config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
components/soc/esp32c6/include/soc/clk_tree_defs.h
+10 -1
View File
@@ -215,14 +215,23 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
#if CONFIG_IDF_ENV_FPGA
#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL}
#else
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
#endif
/**
* @brief I2S clock source enum
*/
typedef enum {
#if CONFIG_IDF_ENV_FPGA
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
#else
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
#endif
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
components/soc/esp32c6/include/soc/i2s_struct.h
+8 -8
View File
@@ -255,7 +255,7 @@ typedef union {
*/
uint32_t rx_clk_active:1;
/** rx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
* Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
*/
uint32_t rx_clk_sel:2;
/** mclk_sel : R/W; bitpos: [29]; default: 0;
@@ -448,7 +448,7 @@ typedef union {
uint32_t val;
} i2s_rx_tdm_ctrl_reg_t;
/** Type of rxeof_num register
/** Type of rx_eof_num register
* I2S RX data number control register.
*/
typedef union {
@@ -461,7 +461,7 @@ typedef union {
uint32_t reserved_12:20;
};
uint32_t val;
} i2s_rxeof_num_reg_t;
} i2s_rx_eof_num_reg_t;
/** Group: TX Control and configuration registers */
@@ -627,7 +627,7 @@ typedef union {
*/
uint32_t tx_clk_active:1;
/** tx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
* Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
* I2S_MCLK_in.
*/
uint32_t tx_clk_sel:2;
@@ -914,7 +914,7 @@ typedef union {
uint32_t val;
} i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register
/** Type of conf_single_data register
* I2S signal data register
*/
typedef union {
@@ -925,7 +925,7 @@ typedef union {
uint32_t single_data:32;
};
uint32_t val;
} i2s_conf_sigle_data_reg_t;
} i2s_conf_single_data_reg_t;
/** Group: TX status registers */
@@ -1005,8 +1005,8 @@ typedef struct i2s_dev_t {
volatile i2s_rx_timing_reg_t rx_timing;
volatile i2s_tx_timing_reg_t tx_timing;
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile i2s_rxeof_num_reg_t rxeof_num;
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
volatile i2s_rx_eof_num_reg_t rx_eof_num;
volatile i2s_conf_single_data_reg_t conf_single_data;
volatile i2s_state_reg_t state;
volatile i2s_etm_conf_reg_t etm_conf;
uint32_t reserved_074[3];
components/soc/esp32c6/include/soc/pcr_struct.h
+2 -2
View File
@@ -607,7 +607,7 @@ typedef union {
*/
uint32_t i2s_tx_clkm_div_num:8;
/** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
* Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
* I2S_MCLK_in.
*/
uint32_t i2s_tx_clkm_sel:2;
@@ -661,7 +661,7 @@ typedef union {
*/
uint32_t i2s_rx_clkm_div_num:8;
/** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
* Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
*/
uint32_t i2s_rx_clkm_sel:2;
/** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;
components/soc/esp32c6/include/soc/soc_caps.h
+2 -2
View File
@@ -40,7 +40,7 @@
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1 // TODO: IDF-5314
#define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 // TODO: IDF-5320
// #define SOC_SDM_SUPPORTED 1 // TODO: IDF-5318
// #define SOC_LEDC_SUPPORTED 1 // TODO: IDF-5328
@@ -181,10 +181,10 @@
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
// TODO: IDF-5314 (Copy from esp32c3, need check)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -339,6 +339,10 @@ config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
components/soc/esp32h2/include/soc/clk_tree_defs.h
+2 -1
View File
@@ -211,7 +211,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL}
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL, SOC_MOD_CLK_XTAL}
/**
* @brief I2S clock source enum
@@ -219,6 +219,7 @@ typedef enum {
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL, /*!< Select SOC_MOD_CLK_PLL as the default source clock */
I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL, /*!< Select PLL as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
components/soc/esp32h2/include/soc/i2s_struct.h
+2 -2
View File
@@ -141,7 +141,7 @@ typedef volatile struct i2s_dev_s {
uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t reserved8: 18; /*Reserved*/
uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/
uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
uint32_t reserved30: 2; /*Reserved*/
};
@@ -152,7 +152,7 @@ typedef volatile struct i2s_dev_s {
uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
uint32_t reserved8: 18; /*Reserved*/
uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/
uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t reserved30: 2; /*Reserved*/
};
components/soc/esp32h2/include/soc/soc_caps.h
+1
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@@ -184,6 +184,7 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+4
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@@ -431,6 +431,10 @@ config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
components/soc/esp32s3/include/soc/clk_tree_defs.h
+2 -1
View File
@@ -252,7 +252,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief I2S clock source enum
@@ -260,6 +260,7 @@ typedef enum {
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
components/soc/esp32s3/include/soc/i2s_struct.h
+2 -2
View File
@@ -142,7 +142,7 @@ typedef volatile struct i2s_dev_s {
uint32_t rx_clkm_div_num : 8; /*Integral I2S clock divider value*/
uint32_t reserved8 : 18; /* Reserved*/
uint32_t rx_clk_active : 1; /*I2S Rx module clock enable signal.*/
uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t mclk_sel : 1; /* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. */
uint32_t reserved30 : 2; /* Reserved*/
};
@@ -153,7 +153,7 @@ typedef volatile struct i2s_dev_s {
uint32_t tx_clkm_div_num : 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. */
uint32_t reserved8 : 18; /* Reserved*/
uint32_t tx_clk_active : 1; /*I2S Tx module clock enable signal.*/
uint32_t tx_clk_sel : 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t tx_clk_sel : 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t clk_en : 1; /*Set this bit to enable clk gate*/
uint32_t reserved30 : 2; /* Reserved*/
};
components/soc/esp32s3/include/soc/soc_caps.h
+1
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@@ -182,6 +182,7 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (2)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)