mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 11:10:54 +03:00
feat(soc): Added soc capabilities related to RNG for ESP32C5
This commit is contained in:
@@ -1491,6 +1491,14 @@ config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_NUM
|
||||
int
|
||||
default 3
|
||||
@@ -1703,6 +1711,10 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RNG_CLOCK_IS_INDEPENDENT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CLK_XTAL32K_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -585,6 +585,10 @@
|
||||
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
|
||||
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
|
||||
|
||||
/*-------------------------- RNG CAPS ---------------------------------------*/
|
||||
#define SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE 1
|
||||
#define SOC_RNG_RTC_TIMER_ENTROPY_SOURCE 1
|
||||
|
||||
/*-------------------------- UART CAPS ---------------------------------------*/
|
||||
// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART)
|
||||
#define SOC_UART_NUM (3)
|
||||
@@ -669,6 +673,7 @@
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
|
||||
#define SOC_RNG_CLOCK_IS_INDEPENDENT (1)
|
||||
|
||||
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
|
||||
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
|
||||
|
||||
Reference in New Issue
Block a user