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feat(soc): Added soc capabilities related to RNG for ESP32C5

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This commit is contained in:
Aditya Patwardhan
2025-07-23 14:22:09 +05:30
parent 6f7ca07018
commit 03ffe90f95
5 changed files with 34 additions and 4 deletions
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components/esp_hw_support/hw_random.c
+11 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -104,9 +104,18 @@ void esp_fill_random(void *buf, size_t len)
}
#if SOC_RNG_CLOCK_IS_INDEPENDENT && !ESP_TEE_BUILD
ESP_SYSTEM_INIT_FN(init_rng_clock, SECONDARY, BIT(0), 102)
ESP_SYSTEM_INIT_FN(init_rng, SECONDARY, BIT(0), 102)
{
_lp_clkrst_ll_enable_rng_clock(true);
#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE
SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE);
#endif
#if SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
// This would only be effective if the RTC clock is enabled
REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3);
SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
#endif
return ESP_OK;
}
#endif