feat(riscv): add support for the DSP coprocessor

2026-10-02 03:00:34 +03:00 · 2025-08-07 14:40:30 +08:00
parent 4a69fcbdfd
commit 03f4744497
8 changed files with 168 additions and 11 deletions
@@ -183,6 +183,10 @@ config SOC_CPU_HAS_FPU_EXT_ILL_BUG
    bool
    default n

+config SOC_CPU_HAS_DSP
+    bool
+    default y
+
 config SOC_CPU_COPROC_NUM
    int
    default 2
@@ -161,6 +161,7 @@
 #define SOC_BRANCH_PREDICTOR_SUPPORTED  1
 #define SOC_CPU_HAS_FPU                 1
 #define SOC_CPU_HAS_FPU_EXT_ILL_BUG     0       // EXT_ILL CSR doesn't support FLW/FSW
+#define SOC_CPU_HAS_DSP                 1
 #define SOC_CPU_COPROC_NUM              2

 #define SOC_CPU_BREAKPOINTS_NUM         4