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Merge branch 'fix/fix_dma_fail_when_flash_enc_enabled_v5.5' into 'release/v5.5'
fix(dma): fix dma alignment when flash_enc enabled (v5.5) See merge request espressif/esp-idf!45080
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -294,6 +294,9 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
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/**
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* @brief Whether to enable access to ecc or aes memory
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*
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* @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
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* We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
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*/
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static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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@@ -528,6 +531,9 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
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/**
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* @brief Whether to enable access to ecc or aes memory
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*
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* @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
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* We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
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*/
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static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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@@ -49,6 +49,7 @@
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#define GDMA_LL_AHB_DESC_ALIGNMENT 4
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#define GDMA_LL_AXI_DESC_ALIGNMENT 8
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#define GDMA_LL_MAX_BURST_SIZE_PSRAM 128 // PSRAM controller doesn't support burst access with size > 128 bytes
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#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
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