Merge branch 'fix/fix_dma_fail_when_flash_enc_enabled_v5.5' into 'release/v5.5'

fix(dma): fix dma alignment when flash_enc enabled (v5.5)

See merge request espressif/esp-idf!45080
This commit is contained in:
morris
2026-01-17 15:57:22 +08:00
20 changed files with 161 additions and 62 deletions
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -294,6 +294,9 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
/**
* @brief Whether to enable access to ecc or aes memory
*
* @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
* We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
*/
static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
@@ -528,6 +531,9 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
/**
* @brief Whether to enable access to ecc or aes memory
*
* @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
* We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
*/
static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
@@ -49,6 +49,7 @@
#define GDMA_LL_AHB_DESC_ALIGNMENT 4
#define GDMA_LL_AXI_DESC_ALIGNMENT 8
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 128 // PSRAM controller doesn't support burst access with size > 128 bytes
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size