diff --git a/components/esp_adc/esp32s2/adc_dma.c b/components/esp_adc/esp32s2/adc_dma.c index 4060b82a3f4..fb04619960b 100644 --- a/components/esp_adc/esp32s2/adc_dma.c +++ b/components/esp_adc/esp32s2/adc_dma.c @@ -28,7 +28,7 @@ static IRAM_ATTR void adc_dma_intr_handler(void *arg) bool conversion_finish = spi_ll_get_intr(ctx->adc_dma.adc_spi_dev, ADC_DMA_INTR_MASK); if (conversion_finish) { spi_ll_clear_intr(ctx->adc_dma.adc_spi_dev, ADC_DMA_INTR_MASK); - intptr_t desc_addr = spi_dma_ll_get_in_suc_eof_desc_addr(ctx->adc_dma.adc_spi_dev, ctx->adc_dma.dma_chan_id); + intptr_t desc_addr = spi_ll_dma_get_in_suc_eof_desc_addr(ctx->adc_dma.adc_spi_dev, ctx->adc_dma.dma_chan_id); ctx->rx_eof_desc_addr = desc_addr; need_yield = ctx->adc_intr_func(ctx); } @@ -80,7 +80,7 @@ esp_err_t adc_dma_start(adc_dma_t adc_dma, dma_descriptor_t *addr) { spi_ll_clear_intr(adc_dma.adc_spi_dev, ADC_DMA_INTR_MASK); spi_ll_enable_intr(adc_dma.adc_spi_dev, ADC_DMA_INTR_MASK); - spi_dma_ll_rx_start(adc_dma.adc_spi_dev, adc_dma.dma_chan_id, (lldesc_t *)addr); + spi_ll_dma_rx_start(adc_dma.adc_spi_dev, adc_dma.dma_chan_id, (lldesc_t *)addr); return ESP_OK; } @@ -88,12 +88,12 @@ esp_err_t adc_dma_stop(adc_dma_t adc_dma) { spi_ll_disable_intr(adc_dma.adc_spi_dev, ADC_DMA_INTR_MASK); spi_ll_clear_intr(adc_dma.adc_spi_dev, ADC_DMA_INTR_MASK); - spi_dma_ll_rx_stop(adc_dma.adc_spi_dev, adc_dma.dma_chan_id); + spi_ll_dma_rx_stop(adc_dma.adc_spi_dev, adc_dma.dma_chan_id); return ESP_OK; } esp_err_t adc_dma_reset(adc_dma_t adc_dma) { - spi_dma_ll_rx_reset(adc_dma.adc_spi_dev, adc_dma.dma_chan_id); + spi_ll_dma_rx_reset(adc_dma.adc_spi_dev, adc_dma.dma_chan_id); return ESP_OK; } diff --git a/components/esp_driver_dac/esp32s2/dac_dma.c b/components/esp_driver_dac/esp32s2/dac_dma.c index b765680c11e..029755ab28c 100644 --- a/components/esp_driver_dac/esp32s2/dac_dma.c +++ b/components/esp_driver_dac/esp32s2/dac_dma.c @@ -183,7 +183,7 @@ int dac_dma_periph_get_intr_signal(void) static void s_dac_dma_periph_reset(void) { - spi_dma_ll_tx_reset(s_ddp->periph_dev, s_ddp->dma_chan); + spi_ll_dma_tx_reset(s_ddp->periph_dev, s_ddp->dma_chan); spi_ll_dma_tx_fifo_reset(s_ddp->periph_dev); } @@ -196,7 +196,7 @@ void dac_dma_periph_enable(void) void dac_dma_periph_disable(void) { s_dac_dma_periph_reset(); - spi_dma_ll_tx_stop(s_ddp->periph_dev, s_ddp->dma_chan); + spi_ll_dma_tx_stop(s_ddp->periph_dev, s_ddp->dma_chan); dac_ll_digi_trigger_output(false); } @@ -212,17 +212,17 @@ uint32_t IRAM_ATTR dac_dma_periph_intr_get_mask(void) void IRAM_ATTR dac_dma_periph_trans_start(uintptr_t desc_addr) { - spi_dma_ll_tx_reset(s_ddp->periph_dev, s_ddp->dma_chan); + spi_ll_dma_tx_reset(s_ddp->periph_dev, s_ddp->dma_chan); spi_ll_dma_tx_fifo_reset(s_ddp->periph_dev); - spi_dma_ll_tx_start(s_ddp->periph_dev, s_ddp->dma_chan, (lldesc_t *)desc_addr); + spi_ll_dma_tx_start(s_ddp->periph_dev, s_ddp->dma_chan, (lldesc_t *)desc_addr); } void dac_dma_periph_trans_stop(void) { - spi_dma_ll_tx_stop(s_ddp->periph_dev, s_ddp->dma_chan); + spi_ll_dma_tx_stop(s_ddp->periph_dev, s_ddp->dma_chan); } void dac_dma_periph_trans_append(void) { - spi_dma_ll_tx_restart(s_ddp->periph_dev, s_ddp->dma_chan); + spi_ll_dma_tx_restart(s_ddp->periph_dev, s_ddp->dma_chan); } diff --git a/components/esp_driver_spi/CMakeLists.txt b/components/esp_driver_spi/CMakeLists.txt index 36ceefdb81f..bad6e382d60 100644 --- a/components/esp_driver_spi/CMakeLists.txt +++ b/components/esp_driver_spi/CMakeLists.txt @@ -13,6 +13,9 @@ if(CONFIG_SOC_GPSPI_SUPPORTED) "src/gpspi/spi_master.c" "src/gpspi/spi_slave.c" ) + if(CONFIG_SOC_PAU_SUPPORTED) + list(APPEND srcs "src/${target}/spi_retention.c") + endif() if(NOT CONFIG_SOC_GDMA_SUPPORTED) list(APPEND srcs "src/gpspi/spi_dma.c") diff --git a/components/esp_driver_spi/include/esp_private/spi_common_internal.h b/components/esp_driver_spi/include/esp_private/spi_common_internal.h index 65efe459110..adc90da881f 100644 --- a/components/esp_driver_spi/include/esp_private/spi_common_internal.h +++ b/components/esp_driver_spi/include/esp_private/spi_common_internal.h @@ -8,8 +8,9 @@ #pragma once -#include #include "esp_pm.h" +#include "esp_intr_alloc.h" +#include "esp_macros.h" #include "soc/soc.h" //for SOC_NON_CACHEABLE_OFFSET_SRAM #include "driver/spi_common.h" #include "hal/spi_types.h" @@ -17,14 +18,16 @@ #include "esp_private/spi_dma.h" #include "esp_private/gdma.h" #include "esp_private/spi_share_hw_ctrl.h" +#if SOC_PAU_SUPPORTED +#include "soc/regdma.h" +#include "soc/retention_periph_defs.h" +#endif #ifdef __cplusplus extern "C" { #endif -#define SPI_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) - //NOTE!! If both A and B are not defined, '#if (A==B)' is true, because GCC use 0 stand for undefined symbol #if SOC_GPSPI_SUPPORTED && defined(SOC_GDMA_BUS_AXI) && (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI) #define DMA_DESC_MEM_ALIGN_SIZE 8 @@ -81,6 +84,16 @@ typedef struct { spi_dma_desc_t *dmadesc_rx; ///< DMA descriptor array for RX } spi_dma_ctx_t; +#if SOC_PAU_SUPPORTED +typedef struct { + const periph_retention_module_t module_id; + const regdma_entries_config_t *entry_array; + uint32_t array_size; +} spi_reg_retention_info_t; + +extern const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1]; // -1 to except mspi +#endif + /// Destructor called when a bus is deinitialized. typedef esp_err_t (*spi_destroy_func_t)(void*); diff --git a/components/esp_driver_spi/src/esp32c5/spi_retention.c b/components/esp_driver_spi/src/esp32c5/spi_retention.c new file mode 100644 index 00000000000..216b5d3c590 --- /dev/null +++ b/components/esp_driver_spi/src/esp32c5/spi_retention.c @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_private/spi_common_internal.h" +#include "soc/spi_periph.h" + +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + REG_SPI_BASE(num), REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, +}; diff --git a/components/esp_driver_spi/src/esp32c6/spi_retention.c b/components/esp_driver_spi/src/esp32c6/spi_retention.c new file mode 100644 index 00000000000..d95be28b0ce --- /dev/null +++ b/components/esp_driver_spi/src/esp32c6/spi_retention.c @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_private/spi_common_internal.h" +#include "soc/spi_periph.h" + +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + REG_SPI_BASE(num), REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, +}; diff --git a/components/esp_driver_spi/src/esp32c61/spi_retention.c b/components/esp_driver_spi/src/esp32c61/spi_retention.c new file mode 100644 index 00000000000..216b5d3c590 --- /dev/null +++ b/components/esp_driver_spi/src/esp32c61/spi_retention.c @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_private/spi_common_internal.h" +#include "soc/spi_periph.h" + +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + REG_SPI_BASE(num), REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, +}; diff --git a/components/esp_driver_spi/src/esp32h2/spi_retention.c b/components/esp_driver_spi/src/esp32h2/spi_retention.c new file mode 100644 index 00000000000..82d5ae98c48 --- /dev/null +++ b/components/esp_driver_spi/src/esp32h2/spi_retention.c @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_private/spi_common_internal.h" +#include "soc/spi_periph.h" + +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + REG_SPI_BASE(num), REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, +}; diff --git a/components/esp_driver_spi/src/esp32h21/spi_retention.c b/components/esp_driver_spi/src/esp32h21/spi_retention.c new file mode 100644 index 00000000000..d77b04c15de --- /dev/null +++ b/components/esp_driver_spi/src/esp32h21/spi_retention.c @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_private/spi_common_internal.h" +#include "soc/spi_periph.h" + +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + DR_REG_SPI_BASE(num), DR_REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) }, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) }, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, +}; diff --git a/components/esp_driver_spi/src/esp32h4/spi_retention.c b/components/esp_driver_spi/src/esp32h4/spi_retention.c new file mode 100644 index 00000000000..710c66fab54 --- /dev/null +++ b/components/esp_driver_spi/src/esp32h4/spi_retention.c @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_private/spi_common_internal.h" +#include "soc/spi_periph.h" + +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + DR_REG_SPI_BASE(num), DR_REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 +static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3); // '3' for GPSPI3 + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, { + .module_id = SLEEP_RETENTION_MODULE_GPSPI3, + .entry_array = spi3_regs_retention, + .array_size = ARRAY_SIZE(spi3_regs_retention), + } +}; diff --git a/components/esp_driver_spi/src/esp32p4/spi_retention.c b/components/esp_driver_spi/src/esp32p4/spi_retention.c new file mode 100644 index 00000000000..feb7d8b3202 --- /dev/null +++ b/components/esp_driver_spi/src/esp32p4/spi_retention.c @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_private/spi_common_internal.h" +#include "soc/spi_periph.h" + +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + REG_SPI_BASE(num), REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) }, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) }, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 +static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3); + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI3, + .entry_array = spi3_regs_retention, + .array_size = ARRAY_SIZE(spi3_regs_retention), + }, +}; diff --git a/components/esp_driver_spi/src/esp32s31/spi_retention.c b/components/esp_driver_spi/src/esp32s31/spi_retention.c new file mode 100644 index 00000000000..930ae249378 --- /dev/null +++ b/components/esp_driver_spi/src/esp32s31/spi_retention.c @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_private/spi_common_internal.h" +#include "soc/spi_periph.h" + +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + REG_SPI_BASE(num), REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2)}, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2)}, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 +static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3); + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI3, + .entry_array = spi3_regs_retention, + .array_size = ARRAY_SIZE(spi3_regs_retention), + }, +}; diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index 86138df518b..0653a76dd82 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -160,21 +160,21 @@ static inline void _spicommon_dma_rcc_clock_ctrl(spi_dma_chan_t dma_chan, bool e if (enable) { PERIPH_RCC_ACQUIRE_ATOMIC(dma_periph, ref_count) { if (ref_count == 0) { - spi_dma_ll_enable_bus_clock(dma_chan, true); - spi_dma_ll_reset_register(dma_chan); + spi_ll_dma_enable_bus_clock(dma_chan, true); + spi_ll_dma_reset_register(dma_chan); } } } else { PERIPH_RCC_RELEASE_ATOMIC(dma_periph, ref_count) { if (ref_count == 0) { - spi_dma_ll_enable_bus_clock(dma_chan, false); + spi_ll_dma_enable_bus_clock(dma_chan, false); } } } #else PERIPH_RCC_ATOMIC() { - spi_dma_ll_enable_bus_clock(dma_chan, enable); - spi_dma_ll_reset_register(dma_chan); + spi_ll_dma_enable_bus_clock(dma_chan, enable); + spi_ll_dma_reset_register(dma_chan); } #endif } @@ -380,7 +380,7 @@ esp_err_t spicommon_dma_desc_alloc(spi_host_device_t host_id, int cfg_max_sz, in return ESP_ERR_NO_MEM; } // cache sync using align_up length thanks to heap alloc already consider the cache alignment requirement - uint8_t aligned_len = SPI_ALIGN_UP(sizeof(spi_dma_desc_t) * dma_desc_ct, bus_ctx[host_id]->bus_attr.cache_align_int); + size_t aligned_len = ESP_ALIGN_UP(sizeof(spi_dma_desc_t) * dma_desc_ct, bus_ctx[host_id]->bus_attr.cache_align_int); // write back and then invalidate the cache, because later we will read/write the link list items by non-cached address esp_err_t ret = esp_cache_msync(dma_ctx->dmadesc_tx, aligned_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE); ESP_RETURN_ON_FALSE_ISR((ret == ESP_OK) || (ret == ESP_ERR_NOT_SUPPORTED), ESP_ERR_INVALID_ARG, SPI_TAG, "dma desc sync failed"); @@ -1127,7 +1127,7 @@ bool SPI_COMMON_ISR_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworka } else { //Reset DMA PERIPH_RCC_ATOMIC() { - spi_dma_ll_reset_register(dmachan); + spi_ll_dma_reset_register(dmachan); } ret = true; } @@ -1147,7 +1147,7 @@ void SPI_COMMON_ISR_ATTR spicommon_dmaworkaround_idle(int dmachan) if (dmaworkaround_waiting_for_chan == dmachan) { //Reset DMA PERIPH_RCC_ATOMIC() { - spi_dma_ll_reset_register(dmachan); + spi_ll_dma_reset_register(dmachan); } dmaworkaround_waiting_for_chan = 0; //Call callback diff --git a/components/esp_driver_spi/src/gpspi/spi_dma.c b/components/esp_driver_spi/src/gpspi/spi_dma.c index 84c913a13c3..14d54e3e467 100644 --- a/components/esp_driver_spi/src/gpspi/spi_dma.c +++ b/components/esp_driver_spi/src/gpspi/spi_dma.c @@ -19,11 +19,11 @@ void spi_dma_enable_burst(spi_dma_chan_handle_t chan_handle, bool data_burst, bo spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); if (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) { - spi_dma_ll_tx_enable_burst_data(spi_dma, chan_handle.chan_id, data_burst); - spi_dma_ll_tx_enable_burst_desc(spi_dma, chan_handle.chan_id, desc_burst); + spi_ll_dma_tx_enable_burst_data(spi_dma, chan_handle.chan_id, data_burst); + spi_ll_dma_tx_enable_burst_desc(spi_dma, chan_handle.chan_id, desc_burst); } else { - spi_dma_ll_rx_enable_burst_data(spi_dma, chan_handle.chan_id, data_burst); - spi_dma_ll_rx_enable_burst_desc(spi_dma, chan_handle.chan_id, desc_burst); + spi_ll_dma_rx_enable_burst_data(spi_dma, chan_handle.chan_id, data_burst); + spi_ll_dma_rx_enable_burst_desc(spi_dma, chan_handle.chan_id, desc_burst); } } @@ -35,7 +35,7 @@ void spi_dma_get_alignment_constraints(spi_dma_chan_handle_t chan_handle, size_t *internal_size = 1; // TX don't need to follow dma alignment in driver design *external_size = 1; } else { - spi_dma_ll_get_rx_alignment_require(spi_dma, (uint32_t *)internal_size, (uint32_t *)external_size); + spi_ll_dma_get_rx_alignment_require(spi_dma, (uint32_t *)internal_size, (uint32_t *)external_size); } } @@ -45,9 +45,9 @@ void spi_dma_append(spi_dma_chan_handle_t chan_handle) spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); if (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) { - spi_dma_ll_tx_restart(spi_dma, chan_handle.chan_id); + spi_ll_dma_tx_restart(spi_dma, chan_handle.chan_id); } else { - spi_dma_ll_rx_restart(spi_dma, chan_handle.chan_id); + spi_ll_dma_rx_restart(spi_dma, chan_handle.chan_id); } } @@ -58,8 +58,8 @@ uint32_t SPI_DMA_ISR_ATTR spi_dma_get_eof_desc(spi_dma_chan_handle_t chan_handle spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); return (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) ? - spi_dma_ll_get_out_eof_desc_addr(spi_dma, chan_handle.chan_id) : - spi_dma_ll_get_in_suc_eof_desc_addr(spi_dma, chan_handle.chan_id); + spi_ll_dma_get_out_eof_desc_addr(spi_dma, chan_handle.chan_id) : + spi_ll_dma_get_in_suc_eof_desc_addr(spi_dma, chan_handle.chan_id); } #endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 @@ -68,9 +68,9 @@ void SPI_DMA_ISR_ATTR spi_dma_reset(spi_dma_chan_handle_t chan_handle) spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); if (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) { - spi_dma_ll_tx_reset(spi_dma, chan_handle.chan_id); + spi_ll_dma_tx_reset(spi_dma, chan_handle.chan_id); } else { - spi_dma_ll_rx_reset(spi_dma, chan_handle.chan_id); + spi_ll_dma_rx_reset(spi_dma, chan_handle.chan_id); } } @@ -79,8 +79,8 @@ void SPI_DMA_ISR_ATTR spi_dma_start(spi_dma_chan_handle_t chan_handle, void *add spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); if (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) { - spi_dma_ll_tx_start(spi_dma, chan_handle.chan_id, (lldesc_t *)addr); + spi_ll_dma_tx_start(spi_dma, chan_handle.chan_id, (lldesc_t *)addr); } else { - spi_dma_ll_rx_start(spi_dma, chan_handle.chan_id, (lldesc_t *)addr); + spi_ll_dma_rx_start(spi_dma, chan_handle.chan_id, (lldesc_t *)addr); } } diff --git a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c index 0c32ba5da27..c08001749b6 100644 --- a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c @@ -141,8 +141,8 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b }; gdma_apply_strategy(host->dma_ctx->tx_dma_chan, &dma_strategy); #else - spi_dma_ll_enable_out_auto_wrback(spi_periph_signal[host->dma_ctx->tx_dma_chan.host_id].hw, host->dma_ctx->tx_dma_chan.chan_id, 1); - spi_dma_ll_set_out_eof_generation(spi_periph_signal[host->dma_ctx->tx_dma_chan.host_id].hw, host->dma_ctx->tx_dma_chan.chan_id, 1); + spi_ll_dma_enable_out_auto_wrback(spi_periph_signal[host->dma_ctx->tx_dma_chan.host_id].hw, host->dma_ctx->tx_dma_chan.chan_id, 1); + spi_ll_dma_set_out_eof_generation(spi_periph_signal[host->dma_ctx->tx_dma_chan.host_id].hw, host->dma_ctx->tx_dma_chan.chan_id, 1); #endif ret = spicommon_dma_desc_alloc(host_id, bus_config->max_transfer_sz, &host->bus_attr->max_transfer_sz); if (ret != ESP_OK) { diff --git a/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h index a0fdcfbc6c7..f79e9a4648f 100644 --- a/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h @@ -1100,7 +1100,7 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +static inline void spi_ll_dma_enable_bus_clock(spi_host_device_t host_id, bool enable) { (void)host_id; // has only one spi_dma if (enable) { @@ -1112,9 +1112,9 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define spi_dma_ll_enable_bus_clock(...) do { \ +#define spi_ll_dma_enable_bus_clock(...) do { \ (void)__DECLARE_RCC_ATOMIC_ENV; \ - spi_dma_ll_enable_bus_clock(__VA_ARGS__); \ + spi_ll_dma_enable_bus_clock(__VA_ARGS__); \ } while(0) /** @@ -1123,7 +1123,7 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e * @param host_id Peripheral index number, see `spi_host_device_t` */ __attribute__((always_inline)) -static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) +static inline void spi_ll_dma_reset_register(spi_host_device_t host_id) { (void)host_id; // has only one spi_dma DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); @@ -1132,9 +1132,9 @@ static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define spi_dma_ll_reset_register(...) do { \ +#define spi_ll_dma_reset_register(...) do { \ (void)__DECLARE_RCC_ATOMIC_ENV; \ - spi_dma_ll_reset_register(__VA_ARGS__); \ + spi_ll_dma_reset_register(__VA_ARGS__); \ } while(0) /** @@ -1144,7 +1144,7 @@ static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) * @param channel DMA channel, for chip version compatibility, not used. */ __attribute__((always_inline)) -static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) +static inline void spi_ll_dma_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) { //Reset RX DMA peripheral dma_in->dma_conf.in_rst = 1; @@ -1159,7 +1159,7 @@ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) * @param addr Address of the beginning DMA descriptor. */ __attribute__((always_inline)) -static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, lldesc_t *addr) +static inline void spi_ll_dma_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, lldesc_t *addr) { dma_in->dma_in_link.addr = (int) addr & 0xFFFFF; dma_in->dma_in_link.start = 1; @@ -1172,7 +1172,7 @@ static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) +static inline void spi_ll_dma_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) { //This is not supported in esp32 } @@ -1184,7 +1184,7 @@ static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32 * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) +static inline void spi_ll_dma_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) { dma_in->dma_conf.indscr_burst_en = enable; } @@ -1196,7 +1196,7 @@ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32 * @param internal_size The internal memory alignment requirements. * @param external_size The external memory alignment requirements. */ -static inline void spi_dma_ll_get_rx_alignment_require(spi_dma_dev_t *dma_dev, uint32_t *internal_size, uint32_t *external_size) +static inline void spi_ll_dma_get_rx_alignment_require(spi_dma_dev_t *dma_dev, uint32_t *internal_size, uint32_t *external_size) { *internal_size = 4; // esp32 needs 4 bytes alignment on hardware design *external_size = UINT32_MAX; // dma of esp32 spi don't support external memory @@ -1209,7 +1209,7 @@ static inline void spi_dma_ll_get_rx_alignment_require(spi_dma_dev_t *dma_dev, u * @param channel DMA channel, for chip version compatibility, not used. */ __attribute__((always_inline)) -static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) +static inline void spi_ll_dma_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) { //Reset TX DMA peripheral dma_out->dma_conf.out_rst = 1; @@ -1224,7 +1224,7 @@ static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) * @param addr Address of the beginning DMA descriptor. */ __attribute__((always_inline)) -static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, lldesc_t *addr) +static inline void spi_ll_dma_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, lldesc_t *addr) { dma_out->dma_out_link.addr = (int) addr & 0xFFFFF; dma_out->dma_out_link.start = 1; @@ -1237,7 +1237,7 @@ static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) +static inline void spi_ll_dma_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_data_burst_en = enable; } @@ -1249,7 +1249,7 @@ static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint3 * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) +static inline void spi_ll_dma_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.outdscr_burst_en = enable; } @@ -1261,7 +1261,7 @@ static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint3 * @param channel DMA channel, for chip version compatibility, not used. * @param enable 1: when dma pop all data from fifo 0:when ahb push all data to fifo. */ -static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) +static inline void spi_ll_dma_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_eof_mode = enable; } @@ -1273,7 +1273,7 @@ static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uin * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) +static inline void spi_ll_dma_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { //does not configure it in ESP32 } diff --git a/components/esp_hal_gpspi/esp32c5/spi_periph.c b/components/esp_hal_gpspi/esp32c5/spi_periph.c index 5931f666e90..2e4a986b546 100644 --- a/components/esp_hal_gpspi/esp32c5/spi_periph.c +++ b/components/esp_hal_gpspi/esp32c5/spi_periph.c @@ -38,48 +38,3 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .func = SPI2_FUNC_NUM_QUAD, }, }; - -/** - * Backup registers in Light sleep: (total cnt 29) - * - * cmd - * addr - * ctrl - * clock - * user - * user1 - * user2 - * ms_dlen - * misc - * dma_conf - * dma_int_ena - * data_buf[0-15] // slave driver only - * slave - * slave1 - */ -#define SPI_RETENTION_REGS_CNT 29 -static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; -#define SPI_REG_RETENTION_ENTRIES(num) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ - REG_SPI_BASE(num), REG_SPI_BASE(num), \ - SPI_RETENTION_REGS_CNT, 0, 0, \ - spi_regs_map[0], spi_regs_map[1], \ - spi_regs_map[2], spi_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ - SPI_DMA_INT_SET_REG(num), \ - SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ - UINT32_MAX, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ -} - -static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 - -const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI2, - .entry_array = spi2_regs_retention, - .array_size = ARRAY_SIZE(spi2_regs_retention), - }, -}; diff --git a/components/esp_hal_gpspi/esp32c6/spi_periph.c b/components/esp_hal_gpspi/esp32c6/spi_periph.c index 06f9c3a8843..db8a7653cd6 100644 --- a/components/esp_hal_gpspi/esp32c6/spi_periph.c +++ b/components/esp_hal_gpspi/esp32c6/spi_periph.c @@ -38,48 +38,3 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .func = SPI2_FUNC_NUM_QUAD, } }; - -/** - * Backup registers in Light sleep: (total cnt 29) - * - * cmd - * addr - * ctrl - * clock - * user - * user1 - * user2 - * ms_dlen - * misc - * dma_conf - * dma_int_ena - * data_buf[0-15] // slave driver only - * slave - * slave1 - */ -#define SPI_RETENTION_REGS_CNT 29 -static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; -#define SPI_REG_RETENTION_ENTRIES(num) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ - REG_SPI_BASE(num), REG_SPI_BASE(num), \ - SPI_RETENTION_REGS_CNT, 0, 0, \ - spi_regs_map[0], spi_regs_map[1], \ - spi_regs_map[2], spi_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ - SPI_DMA_INT_SET_REG(num), \ - SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ - UINT32_MAX, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ -} - -static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 - -const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI2, - .entry_array = spi2_regs_retention, - .array_size = ARRAY_SIZE(spi2_regs_retention), - }, -}; diff --git a/components/esp_hal_gpspi/esp32c61/spi_periph.c b/components/esp_hal_gpspi/esp32c61/spi_periph.c index 5931f666e90..2e4a986b546 100644 --- a/components/esp_hal_gpspi/esp32c61/spi_periph.c +++ b/components/esp_hal_gpspi/esp32c61/spi_periph.c @@ -38,48 +38,3 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .func = SPI2_FUNC_NUM_QUAD, }, }; - -/** - * Backup registers in Light sleep: (total cnt 29) - * - * cmd - * addr - * ctrl - * clock - * user - * user1 - * user2 - * ms_dlen - * misc - * dma_conf - * dma_int_ena - * data_buf[0-15] // slave driver only - * slave - * slave1 - */ -#define SPI_RETENTION_REGS_CNT 29 -static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; -#define SPI_REG_RETENTION_ENTRIES(num) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ - REG_SPI_BASE(num), REG_SPI_BASE(num), \ - SPI_RETENTION_REGS_CNT, 0, 0, \ - spi_regs_map[0], spi_regs_map[1], \ - spi_regs_map[2], spi_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ - SPI_DMA_INT_SET_REG(num), \ - SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ - UINT32_MAX, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ -} - -static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 - -const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI2, - .entry_array = spi2_regs_retention, - .array_size = ARRAY_SIZE(spi2_regs_retention), - }, -}; diff --git a/components/esp_hal_gpspi/esp32h2/spi_periph.c b/components/esp_hal_gpspi/esp32h2/spi_periph.c index 450d0a3f5ed..fd70a9f527c 100644 --- a/components/esp_hal_gpspi/esp32h2/spi_periph.c +++ b/components/esp_hal_gpspi/esp32h2/spi_periph.c @@ -38,48 +38,3 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .func = SPI2_FUNC_NUM_QUAD, } }; - -/** - * Backup registers in Light sleep: (total cnt 29) - * - * cmd - * addr - * ctrl - * clock - * user - * user1 - * user2 - * ms_dlen - * misc - * dma_conf - * dma_int_ena - * data_buf[0-15] // slave driver only - * slave - * slave1 - */ -#define SPI_RETENTION_REGS_CNT 29 -static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; -#define SPI_REG_RETENTION_ENTRIES(num) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ - REG_SPI_BASE(num), REG_SPI_BASE(num), \ - SPI_RETENTION_REGS_CNT, 0, 0, \ - spi_regs_map[0], spi_regs_map[1], \ - spi_regs_map[2], spi_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ - SPI_DMA_INT_SET_REG(num), \ - SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ - UINT32_MAX, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ -} - -static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 - -const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI2, - .entry_array = spi2_regs_retention, - .array_size = ARRAY_SIZE(spi2_regs_retention), - }, -}; diff --git a/components/esp_hal_gpspi/esp32h21/spi_periph.c b/components/esp_hal_gpspi/esp32h21/spi_periph.c index 8faa447f4ec..f45afda4a58 100644 --- a/components/esp_hal_gpspi/esp32h21/spi_periph.c +++ b/components/esp_hal_gpspi/esp32h21/spi_periph.c @@ -38,48 +38,3 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .func = SPI2_FUNC_NUM_QUAD, } }; - -/** - * Backup registers in Light sleep: (total cnt 29) - * - * cmd - * addr - * ctrl - * clock - * user - * user1 - * user2 - * ms_dlen - * misc - * dma_conf - * dma_int_ena - * data_buf[0-15] // slave driver only - * slave - * slave1 - */ -#define SPI_RETENTION_REGS_CNT 29 -static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; -#define SPI_REG_RETENTION_ENTRIES(num) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ - DR_REG_SPI_BASE(num), DR_REG_SPI_BASE(num), \ - SPI_RETENTION_REGS_CNT, 0, 0, \ - spi_regs_map[0], spi_regs_map[1], \ - spi_regs_map[2], spi_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ - SPI_DMA_INT_SET_REG(num), \ - SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ - UINT32_MAX, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ -} - -static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 - -const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI2, - .entry_array = spi2_regs_retention, - .array_size = ARRAY_SIZE(spi2_regs_retention), - }, -}; diff --git a/components/esp_hal_gpspi/esp32h4/spi_periph.c b/components/esp_hal_gpspi/esp32h4/spi_periph.c index 8b227d3ff2d..2fe058bdd54 100644 --- a/components/esp_hal_gpspi/esp32h4/spi_periph.c +++ b/components/esp_hal_gpspi/esp32h4/spi_periph.c @@ -62,53 +62,3 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .func = -1, } }; - -/** - * Backup registers in Light sleep: (total cnt 29) - * - * cmd - * addr - * ctrl - * clock - * user - * user1 - * user2 - * ms_dlen - * misc - * dma_conf - * dma_int_ena - * data_buf[0-15] // slave driver only - * slave - * slave1 - */ -#define SPI_RETENTION_REGS_CNT 29 -static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; -#define SPI_REG_RETENTION_ENTRIES(num) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ - DR_REG_SPI_BASE(num), DR_REG_SPI_BASE(num), \ - SPI_RETENTION_REGS_CNT, 0, 0, \ - spi_regs_map[0], spi_regs_map[1], \ - spi_regs_map[2], spi_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ - SPI_DMA_INT_SET_REG(num), \ - SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ - UINT32_MAX, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2) }, \ -} - -static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 -static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3); // '3' for GPSPI3 - -const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI2, - .entry_array = spi2_regs_retention, - .array_size = ARRAY_SIZE(spi2_regs_retention), - }, { - .module_id = SLEEP_RETENTION_MODULE_GPSPI3, - .entry_array = spi3_regs_retention, - .array_size = ARRAY_SIZE(spi3_regs_retention), - } -}; diff --git a/components/esp_hal_gpspi/esp32p4/spi_periph.c b/components/esp_hal_gpspi/esp32p4/spi_periph.c index a577821f6ed..89504af2c7c 100644 --- a/components/esp_hal_gpspi/esp32p4/spi_periph.c +++ b/components/esp_hal_gpspi/esp32p4/spi_periph.c @@ -70,54 +70,3 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .func = -1, } }; - -/** - * Backup registers in Light sleep: (total cnt 29) - * - * cmd - * addr - * ctrl - * clock - * user - * user1 - * user2 - * ms_dlen - * misc - * dma_conf - * dma_int_ena - * data_buf[0-15] // slave driver only - * slave - * slave1 - */ -#define SPI_RETENTION_REGS_CNT 29 -static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; -#define SPI_REG_RETENTION_ENTRIES(num) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ - REG_SPI_BASE(num), REG_SPI_BASE(num), \ - SPI_RETENTION_REGS_CNT, 0, 0, \ - spi_regs_map[0], spi_regs_map[1], \ - spi_regs_map[2], spi_regs_map[3]), \ - .owner = ENTRY(0) }, \ - /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ - SPI_DMA_INT_SET_REG(num), \ - SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ - UINT32_MAX, 1, 0), \ - .owner = ENTRY(0) }, \ -} - -static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 -static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3); - -const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI2, - .entry_array = spi2_regs_retention, - .array_size = ARRAY_SIZE(spi2_regs_retention), - }, - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI3, - .entry_array = spi3_regs_retention, - .array_size = ARRAY_SIZE(spi3_regs_retention), - }, -}; diff --git a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h index 096167ff8e5..a684ac5c1cd 100644 --- a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h @@ -1247,7 +1247,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +static inline void spi_ll_dma_enable_bus_clock(spi_host_device_t host_id, bool enable) { if (enable) { switch (host_id) { @@ -1276,9 +1276,9 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define spi_dma_ll_enable_bus_clock(...) do { \ +#define spi_ll_dma_enable_bus_clock(...) do { \ (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - spi_dma_ll_enable_bus_clock(__VA_ARGS__); \ + spi_ll_dma_enable_bus_clock(__VA_ARGS__); \ } while(0) /** @@ -1286,7 +1286,7 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) +static inline void spi_ll_dma_reset_register(spi_host_device_t host_id) { switch (host_id) { case SPI2_HOST: @@ -1304,9 +1304,9 @@ static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define spi_dma_ll_reset_register(...) do { \ +#define spi_ll_dma_reset_register(...) do { \ (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - spi_dma_ll_reset_register(__VA_ARGS__); \ + spi_ll_dma_reset_register(__VA_ARGS__); \ } while(0) //---------------------------------------------------RX-------------------------------------------------// @@ -1317,7 +1317,7 @@ static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) * @param channel DMA channel, for chip version compatibility, not used. */ __attribute__((always_inline)) -static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) +static inline void spi_ll_dma_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) { dma_in->dma_conf.in_rst = 1; dma_in->dma_conf.in_rst = 0; @@ -1331,7 +1331,7 @@ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) * @param addr Address of the beginning DMA descriptor. */ __attribute__((always_inline)) -static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, lldesc_t *addr) +static inline void spi_ll_dma_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, lldesc_t *addr) { dma_in->dma_in_link.addr = (int) addr & 0xFFFFF; dma_in->dma_in_link.start = 1; @@ -1343,7 +1343,7 @@ static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. * @param channel DMA channel, for chip version compatibility, not used. */ -static inline void spi_dma_ll_rx_stop(spi_dma_dev_t *dma_in, uint32_t channel) +static inline void spi_ll_dma_rx_stop(spi_dma_dev_t *dma_in, uint32_t channel) { dma_in->dma_in_link.stop = 1; } @@ -1355,7 +1355,7 @@ static inline void spi_dma_ll_rx_stop(spi_dma_dev_t *dma_in, uint32_t channel) * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) +static inline void spi_ll_dma_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) { //This is not supported in esp32s2 } @@ -1367,7 +1367,7 @@ static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32 * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) +static inline void spi_ll_dma_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) { dma_in->dma_conf.indscr_burst_en = enable; } @@ -1380,7 +1380,7 @@ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32 * @return The address */ __attribute__((always_inline)) -static inline uint32_t spi_dma_ll_get_in_suc_eof_desc_addr(spi_dma_dev_t *dma_in, uint32_t channel) +static inline uint32_t spi_ll_dma_get_in_suc_eof_desc_addr(spi_dma_dev_t *dma_in, uint32_t channel) { ESP_STATIC_ANALYZER_CHECK(!dma_in, -1); return dma_in->dma_in_suc_eof_des_addr; @@ -1393,7 +1393,7 @@ static inline uint32_t spi_dma_ll_get_in_suc_eof_desc_addr(spi_dma_dev_t *dma_in * @param internal_size The internal memory alignment requirements. * @param external_size The external memory alignment requirements. */ -static inline void spi_dma_ll_get_rx_alignment_require(spi_dma_dev_t *dma_dev, uint32_t *internal_size, uint32_t *external_size) +static inline void spi_ll_dma_get_rx_alignment_require(spi_dma_dev_t *dma_dev, uint32_t *internal_size, uint32_t *external_size) { *internal_size = 4; // SPI2 supports external memory, SPI3 does not @@ -1408,7 +1408,7 @@ static inline void spi_dma_ll_get_rx_alignment_require(spi_dma_dev_t *dma_dev, u * @param channel DMA channel, for chip version compatibility, not used. */ __attribute__((always_inline)) -static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) +static inline void spi_ll_dma_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) { //Reset TX DMA peripheral dma_out->dma_conf.out_rst = 1; @@ -1423,7 +1423,7 @@ static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) * @param addr Address of the beginning DMA descriptor. */ __attribute__((always_inline)) -static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, lldesc_t *addr) +static inline void spi_ll_dma_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, lldesc_t *addr) { dma_out->dma_out_link.addr = (int) addr & 0xFFFFF; dma_out->dma_out_link.start = 1; @@ -1435,7 +1435,7 @@ static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. * @param channel DMA channel, for chip version compatibility, not used. */ -static inline void spi_dma_ll_tx_stop(spi_dma_dev_t *dma_out, uint32_t channel) +static inline void spi_ll_dma_tx_stop(spi_dma_dev_t *dma_out, uint32_t channel) { dma_out->dma_out_link.stop = 1; } @@ -1447,7 +1447,7 @@ static inline void spi_dma_ll_tx_stop(spi_dma_dev_t *dma_out, uint32_t channel) * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) +static inline void spi_ll_dma_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_data_burst_en = enable; } @@ -1459,7 +1459,7 @@ static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint3 * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) +static inline void spi_ll_dma_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.outdscr_burst_en = enable; } @@ -1471,7 +1471,7 @@ static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint3 * @param channel DMA channel, for chip version compatibility, not used. * @param enable 1: when dma pop all data from fifo 0:when ahb push all data to fifo. */ -static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) +static inline void spi_ll_dma_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_eof_mode = enable; } @@ -1483,7 +1483,7 @@ static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uin * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) +static inline void spi_ll_dma_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_auto_wrback = enable; } @@ -1496,28 +1496,28 @@ static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uin * @return The address */ __attribute__((always_inline)) -static inline uint32_t spi_dma_ll_get_out_eof_desc_addr(spi_dma_dev_t *dma_out, uint32_t channel) +static inline uint32_t spi_ll_dma_get_out_eof_desc_addr(spi_dma_dev_t *dma_out, uint32_t channel) { ESP_STATIC_ANALYZER_CHECK(!dma_out, -1); return dma_out->dma_out_eof_des_addr; } -static inline void spi_dma_ll_rx_restart(spi_dma_dev_t *dma_in, uint32_t channel) +static inline void spi_ll_dma_rx_restart(spi_dma_dev_t *dma_in, uint32_t channel) { dma_in->dma_in_link.restart = 1; } -static inline void spi_dma_ll_tx_restart(spi_dma_dev_t *dma_out, uint32_t channel) +static inline void spi_ll_dma_tx_restart(spi_dma_dev_t *dma_out, uint32_t channel) { dma_out->dma_out_link.restart = 1; } -static inline void spi_dma_ll_rx_disable(spi_dma_dev_t *dma_in) +static inline void spi_ll_dma_rx_disable(spi_dma_dev_t *dma_in) { dma_in->dma_in_link.dma_rx_ena = 0; } -static inline void spi_dma_ll_tx_disable(spi_dma_dev_t *dma_out) +static inline void spi_ll_dma_tx_disable(spi_dma_dev_t *dma_out) { dma_out->dma_out_link.dma_tx_ena = 0; } diff --git a/components/esp_hal_gpspi/esp32s31/spi_periph.c b/components/esp_hal_gpspi/esp32s31/spi_periph.c index aa3a485a1ed..69c4617e6d1 100644 --- a/components/esp_hal_gpspi/esp32s31/spi_periph.c +++ b/components/esp_hal_gpspi/esp32s31/spi_periph.c @@ -70,56 +70,3 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .func = -1, } }; - -#if SOC_PAU_SUPPORTED -/** - * Backup registers in Light sleep: (total cnt 29) - * - * cmd - * addr - * ctrl - * clock - * user - * user1 - * user2 - * ms_dlen - * misc - * dma_conf - * dma_int_ena - * data_buf[0-15] // slave driver only - * slave - * slave1 - */ -#define SPI_RETENTION_REGS_CNT 29 -static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; -#define SPI_REG_RETENTION_ENTRIES(num) { \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ - REG_SPI_BASE(num), REG_SPI_BASE(num), \ - SPI_RETENTION_REGS_CNT, 0, 0, \ - spi_regs_map[0], spi_regs_map[1], \ - spi_regs_map[2], spi_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2)}, \ - /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ - SPI_DMA_INT_SET_REG(num), \ - SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ - UINT32_MAX, 1, 0), \ - .owner = ENTRY(0) | ENTRY(2)}, \ -} - -static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 -static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3); - -const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI2, - .entry_array = spi2_regs_retention, - .array_size = ARRAY_SIZE(spi2_regs_retention), - }, - { - .module_id = SLEEP_RETENTION_MODULE_GPSPI3, - .entry_array = spi3_regs_retention, - .array_size = ARRAY_SIZE(spi3_regs_retention), - }, -}; -#endif // SOC_PAU_SUPPORTED diff --git a/components/esp_hal_gpspi/include/soc/spi_periph.h b/components/esp_hal_gpspi/include/soc/spi_periph.h index 5b03efc28df..4973bf932ca 100644 --- a/components/esp_hal_gpspi/include/soc/spi_periph.h +++ b/components/esp_hal_gpspi/include/soc/spi_periph.h @@ -14,10 +14,6 @@ #include "soc/spi_reg.h" #include "soc/spi_struct.h" #include "soc/spi_pins.h" -#if SOC_PAU_SUPPORTED -#include "soc/regdma.h" -#include "soc/retention_periph_defs.h" -#endif #ifdef __cplusplus extern "C" { @@ -67,16 +63,6 @@ typedef struct { extern const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM]; -#if SOC_PAU_SUPPORTED -typedef struct { - const periph_retention_module_t module_id; - const regdma_entries_config_t *entry_array; - uint32_t array_size; -} spi_reg_retention_info_t; - -extern const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1]; // -1 to except mspi -#endif // SOC_PAU_SUPPORTED - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/mmu_ll.h b/components/hal/esp32c5/include/hal/mmu_ll.h index 496a0ee3a1d..0993269ff4a 100644 --- a/components/hal/esp32c5/include/hal/mmu_ll.h +++ b/components/hal/esp32c5/include/hal/mmu_ll.h @@ -236,7 +236,6 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm } } -#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE /** * Write a PSRAM MMU entry without the SENSITIVE bit, used only for the * carved-out unencrypted region (see CONFIG_SPIRAM_ENC_EXEMPT). @@ -251,7 +250,6 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry_no_enc(uint REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value); } -#endif /** * Read the raw value from MMU table diff --git a/components/hal/esp32c61/include/hal/mmu_ll.h b/components/hal/esp32c61/include/hal/mmu_ll.h index 384e8e999b9..e6a54145fc0 100644 --- a/components/hal/esp32c61/include/hal/mmu_ll.h +++ b/components/hal/esp32c61/include/hal/mmu_ll.h @@ -238,7 +238,6 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm } } -#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE /** * Write a PSRAM MMU entry without the SENSITIVE bit, used only for the * carved-out unencrypted region (see CONFIG_SPIRAM_ENC_EXEMPT). @@ -253,7 +252,6 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry_no_enc(uint REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value); } -#endif /** * Read the raw value from MMU table