feat(esp32p4): add H264 REGDMA link and sleep retention module

This commit is contained in:
houhaiyan
2026-04-07 14:47:46 +08:00
parent 953c40c9aa
commit 033b1ff7ce
5 changed files with 14 additions and 1 deletions
@@ -102,6 +102,9 @@ bool peripheral_domain_pd_allowed(void)
// ESP32P4 supports LCDCAM sleep retention
RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_LCDCAM);
// ESP32P4 supports H264 sleep retention
RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_H264);
const sleep_retention_module_bitmap_t peripheral_domain_inited_modules = sleep_retention_module_bitmap_and(inited_modules, mask);
const sleep_retention_module_bitmap_t peripheral_domain_created_modules = sleep_retention_module_bitmap_and(created_modules, mask);
return sleep_retention_module_bitmap_eq(peripheral_domain_inited_modules, peripheral_domain_created_modules);
@@ -1891,6 +1891,10 @@ config SOC_JPEG_ENCODE_SUPPORTED
bool
default y
config SOC_H264_ENCODER_SUPPORTED
bool
default y
config SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV
bool
default y
@@ -63,6 +63,7 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_EMAC = 37,
SLEEP_RETENTION_MODULE_JPEG = 38,
SLEEP_RETENTION_MODULE_LCDCAM = 39,
SLEEP_RETENTION_MODULE_H264 = 40,
/* PMU REGDMA clock icg */
SLEEP_RETENTION_MODULE_CLOCK_ICG = SOC_PM_RETENTION_MODULE_NUM - 2,
@@ -70,7 +71,7 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
#define is_top_domain_module(m) (((m) <= SLEEP_RETENTION_MODULE_LCDCAM) || ((m) == SLEEP_RETENTION_MODULE_CLOCK_ICG))
#define is_top_domain_module(m) (((m) <= SLEEP_RETENTION_MODULE_H264) || ((m) == SLEEP_RETENTION_MODULE_CLOCK_ICG))
#ifdef __cplusplus
}
@@ -723,6 +723,9 @@
#define SOC_JPEG_DECODE_SUPPORTED (1)
#define SOC_JPEG_ENCODE_SUPPORTED (1)
/*--------------------------- H264 --------------------------------*/
#define SOC_H264_ENCODER_SUPPORTED (1)
/*--------------------------- CAM ---------------------------------*/
#define SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV (1)
+2
View File
@@ -68,6 +68,7 @@ extern "C" {
#define REGDMA_EMAC_LINK(_pri) ((0x27 << 8) | _pri)
#define REGDMA_JPEG_LINK(_pri) ((0x28 << 8) | _pri)
#define REGDMA_LCDCAM_LINK(_pri) ((0x29 << 8) | _pri)
#define REGDMA_H264_LINK(_pri) ((0x2a << 8) | _pri)
#define REGDMA_CLOCK_ICG_LINK(_pri) ((0xFE << 8) | _pri)
#define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri)
@@ -100,6 +101,7 @@ extern "C" {
#define REGDMA_LINK_PRI_EMAC REGDMA_LINK_PRI_GENERAL_PERIPH
#define REGDMA_LINK_PRI_JPEG REGDMA_LINK_PRI_GENERAL_PERIPH
#define REGDMA_LINK_PRI_LCDCAM REGDMA_LINK_PRI_GENERAL_PERIPH
#define REGDMA_LINK_PRI_H264 REGDMA_LINK_PRI_GENERAL_PERIPH
typedef enum {
REGDMA_LINK_PRI_0 = 0,