From 0249f682dca1293b42b0bc4b099958f14b8b5239 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 28 Jan 2026 11:06:25 +0800 Subject: [PATCH] change(soc): remove deprecated macros in soc/rtc.h --- .../port/esp32c2/include/soc/rtc.h | 14 +----- .../port/esp32c3/include/soc/rtc.h | 3 -- .../port/esp32c5/include/soc/rtc.h | 42 ------------------ .../port/esp32c6/include/soc/rtc.h | 44 +------------------ .../port/esp32c61/include/soc/rtc.h | 42 ------------------ .../port/esp32h2/include/soc/rtc.h | 44 +------------------ .../port/esp32h21/include/soc/rtc.h | 14 +----- .../port/esp32h4/include/soc/rtc.h | 15 +------ .../port/esp32p4/include/soc/rtc.h | 42 +----------------- .../port/esp32s31/include/soc/rtc.h | 14 +----- components/esp_hw_support/sleep_modes.c | 9 +++- 11 files changed, 14 insertions(+), 269 deletions(-) diff --git a/components/esp_hw_support/port/esp32c2/include/soc/rtc.h b/components/esp_hw_support/port/esp32c2/include/soc/rtc.h index 0cae435c2b1..cfa31e5b267 100644 --- a/components/esp_hw_support/port/esp32c2/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c2/include/soc/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -131,15 +131,6 @@ use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT #define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6 5 #define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6 5 -/* -The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value -storing in efuse (based on ATE 5k ECO3 chips) -*/ -#define K_RTC_MID_MUL10000 215 -#define K_DIG_MID_MUL10000 213 -#define V_RTC_MID_MUL10000 10800 -#define V_DIG_MID_MUL10000 10860 - /** * @brief CPU clock configuration structure */ @@ -152,9 +143,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW #define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256 #define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW diff --git a/components/esp_hw_support/port/esp32c3/include/soc/rtc.h b/components/esp_hw_support/port/esp32c3/include/soc/rtc.h index a46e40716c7..0e2851e72c4 100644 --- a/components/esp_hw_support/port/esp32c3/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c3/include/soc/rtc.h @@ -154,9 +154,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW #define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256 #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index 04b2a8d61ff..4c394038eb5 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -49,9 +49,6 @@ extern "C" { #define MHZ (1000000) -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - /* Delays for various clock sources to be enabled/switched. * All values are in microseconds. */ @@ -60,45 +57,9 @@ extern "C" { #define SOC_DELAY_RC_FAST_ENABLE 50 #define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 - #define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 #define RTC_CNTL_SCK_DCAP_DEFAULT 128 -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) -#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) -#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) -#define RTC_CNTL_MIN_SLP_VAL_MIN (2) - -/* -set sleep_init default param -*/ -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 - -/* -The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value -storing in efuse (based on ATE 5k ECO3 chips) -*/ -#define K_RTC_MID_MUL10000 215 -#define K_DIG_MID_MUL10000 213 -#define V_RTC_MID_MUL10000 10800 -#define V_DIG_MID_MUL10000 10860 - #if CONFIG_ESP_ENABLE_PVT /* set pvt default param @@ -158,9 +119,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL #define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h index 7e5dddbb74e..82907e29a15 100644 --- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -53,9 +53,6 @@ extern "C" { #define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - /* Delays for various clock sources to be enabled/switched. * All values are in microseconds. */ @@ -65,37 +62,10 @@ extern "C" { #define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 #define SOC_DELAY_RC32K_ENABLE 300 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 - #define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 #define RTC_CNTL_SCK_DCAP_DEFAULT 128 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) -#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) -#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) -#define RTC_CNTL_MIN_SLP_VAL_MIN (2) - -/* -set sleep_init default param -*/ -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 - #if CONFIG_ESP_ENABLE_PVT /* set pvt default param @@ -144,15 +114,6 @@ void charge_pump_enable(bool enable); #endif //#if CONFIG_ESP_ENABLE_PVT -/* -The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value -storing in efuse (based on ATE 5k ECO3 chips) -*/ -#define K_RTC_MID_MUL10000 215 -#define K_DIG_MID_MUL10000 213 -#define V_RTC_MID_MUL10000 10800 -#define V_DIG_MID_MUL10000 10860 - /** * @brief CPU clock configuration structure */ @@ -165,9 +126,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW #define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW #define RTC_CAL_RC32K _Pragma ("GCC warning \"'RTC_CAL_RC32K' macro is deprecated\"") CLK_CAL_RC32K diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h index 22087d8d515..d955aad0025 100644 --- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h @@ -49,9 +49,6 @@ extern "C" { #define MHZ (1000000) -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - /* Delays for various clock sources to be enabled/switched. * All values are in microseconds. */ @@ -60,45 +57,9 @@ extern "C" { #define SOC_DELAY_RC_FAST_ENABLE 50 #define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 - #define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 #define RTC_CNTL_SCK_DCAP_DEFAULT 128 -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) -#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) -#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) -#define RTC_CNTL_MIN_SLP_VAL_MIN (2) - -/* -set sleep_init default param -*/ -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 - -/* -The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value -storing in efuse (based on ATE 5k ECO3 chips) -*/ -#define K_RTC_MID_MUL10000 215 -#define K_DIG_MID_MUL10000 213 -#define V_RTC_MID_MUL10000 10800 -#define V_DIG_MID_MUL10000 10860 - #if CONFIG_ESP_ENABLE_PVT /* set pvt default param @@ -158,9 +119,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL #define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW diff --git a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h index 1973e87311d..15de68e3171 100644 --- a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -54,9 +54,6 @@ extern "C" { #define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - /* Delays for various clock sources to be enabled/switched. * All values are in microseconds. */ @@ -68,46 +65,10 @@ extern "C" { #define SOC_DELAY_LP_PLL_SWITCH 3 #define SOC_DELAY_LP_PLL_ENABLE 50 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 - #define RTC_CNTL_CK8M_DFREQ_DEFAULT 860 #define RTC_CNTL_SCK_DCAP_DEFAULT 85 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) -#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) -#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) -#define RTC_CNTL_MIN_SLP_VAL_MIN (2) - -/* -set sleep_init default param -*/ -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 - -/* -The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value -storing in efuse (based on ATE 5k ECO3 chips) -*/ -#define K_RTC_MID_MUL10000 215 -#define K_DIG_MID_MUL10000 213 -#define V_RTC_MID_MUL10000 10800 -#define V_DIG_MID_MUL10000 10860 - /** * @brief CPU clock configuration structure */ @@ -120,9 +81,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW #define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW #define RTC_CAL_RC32K _Pragma ("GCC warning \"'RTC_CAL_RC32K' macro is deprecated\"") CLK_CAL_RC32K diff --git a/components/esp_hw_support/port/esp32h21/include/soc/rtc.h b/components/esp_hw_support/port/esp32h21/include/soc/rtc.h index 83fd8ed0aa1..5da854b0e48 100644 --- a/components/esp_hw_support/port/esp32h21/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32h21/include/soc/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -50,9 +50,6 @@ extern "C" { #define MHZ (1000000) -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - /* Delays for various clock sources to be enabled/switched. * All values are in microseconds. */ @@ -69,15 +66,6 @@ extern "C" { #define RTC_CNTL_CK8M_DFREQ_DEFAULT 860 #define RTC_CNTL_SCK_DCAP_DEFAULT 85 -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) -#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) -#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) -#define RTC_CNTL_MIN_SLP_VAL_MIN (2) - // /* // set sleep_init default param // */ diff --git a/components/esp_hw_support/port/esp32h4/include/soc/rtc.h b/components/esp_hw_support/port/esp32h4/include/soc/rtc.h index 22c23362dd5..fd1ac2f3b37 100644 --- a/components/esp_hw_support/port/esp32h4/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32h4/include/soc/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -50,9 +50,6 @@ extern "C" { #define MHZ (1000000) -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - /* Delays for various clock sources to be enabled/switched. * All values are in microseconds. */ @@ -68,16 +65,6 @@ extern "C" { #define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 #define RTC_CNTL_SCK_DCAP_DEFAULT 28 - -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) -#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) -#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) -#define RTC_CNTL_MIN_SLP_VAL_MIN (2) - // /* // set sleep_init default param // */ diff --git a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h index 9f9d1117240..44612f3a8c8 100644 --- a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -50,9 +50,6 @@ extern "C" { #define MHZ (1000000) -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - /* Delays for various clock sources to be enabled/switched. * All values are in microseconds. */ @@ -71,32 +68,7 @@ extern "C" { #define RTC_CNTL_SCK_DCAP_DEFAULT 128 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) -#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) -#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) -#define RTC_CNTL_MIN_SLP_VAL_MIN (2) - -/* -set sleep_init default param -*/ -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 - #if CONFIG_ESP_ENABLE_PVT - #define PVT_CHANNEL0_SEL 49 #define PVT_CHANNEL1_SEL 53 #define PVT_CHANNEL0_CFG 0x13e80 @@ -130,15 +102,6 @@ void pvt_func_enable(bool enable); #endif //#if CONFIG_ESP_ENABLE_PVT -/* -The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value -storing in efuse (based on ATE 5k ECO3 chips) -*/ -#define K_RTC_MID_MUL10000 215 -#define K_DIG_MID_MUL10000 213 -#define V_RTC_MID_MUL10000 10800 -#define V_DIG_MID_MUL10000 10860 - /** * @brief CPU clock configuration structure */ @@ -151,9 +114,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW #define RTC_CAL_MPLL _Pragma ("GCC warning \"'RTC_CAL_MPLL' macro is deprecated\"") CLK_CAL_MPLL #define RTC_CAL_SPLL _Pragma ("GCC warning \"'RTC_CAL_SPLL' macro is deprecated\"") CLK_CAL_SPLL diff --git a/components/esp_hw_support/port/esp32s31/include/soc/rtc.h b/components/esp_hw_support/port/esp32s31/include/soc/rtc.h index ec0c06c1ac6..388ee01576a 100644 --- a/components/esp_hw_support/port/esp32s31/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32s31/include/soc/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -56,15 +56,6 @@ extern "C" { #define RTC_CNTL_SCK_DCAP_DEFAULT 128 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 -/* -The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value -storing in efuse (based on ATE 5k ECO3 chips) -*/ -#define K_RTC_MID_MUL10000 215 -#define K_DIG_MID_MUL10000 213 -#define V_RTC_MID_MUL10000 10800 -#define V_DIG_MID_MUL10000 10860 - /** * @brief CPU clock configuration structure */ @@ -77,9 +68,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - /** * @brief Clock source to be calibrated using rtc_clk_cal function * diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 54d215f97eb..a02da64eb7c 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -1525,10 +1525,12 @@ esp_err_t esp_light_sleep_start(void) #endif int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(sleep_flags, rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period); s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment; -#else + const int64_t min_sleep_duration_us = ((pmu_sleep_machine_constant_t *)PMU_instance()->mc)->lp.min_slp_time_us; +#else // RTC_CNTL supported uint32_t rtc_cntl_xtl_buf_wait_slp_cycles = rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, s_config.rtc_clk_cal_period); s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out + rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_slp_cycles + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, s_config.rtc_clk_cal_period); + const int64_t min_sleep_duration_us = rtc_time_slowclk_to_us(RTC_CNTL_MIN_SLP_VAL_MIN, s_config.rtc_clk_cal_period); #endif // Decide if VDD_SDIO needs to be powered down; @@ -1553,7 +1555,11 @@ esp_err_t esp_light_sleep_start(void) * min_protect(2); * 4. All the adjustment time which is s_config.sleep_time_adjustment below. */ +#if SOC_PMU_SUPPORTED + uint32_t rtc_slowclk_us = rtc_time_slowclk_to_us(RTC_MODULE_SLEEP_PREPARE_CYCLES, s_config.rtc_clk_cal_period) + min_sleep_duration_us; +#else uint32_t rtc_slowclk_us = rtc_time_slowclk_to_us(RTC_MODULE_SLEEP_PREPARE_CYCLES + RTC_CNTL_MIN_SLP_VAL_MIN, s_config.rtc_clk_cal_period); +#endif const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US, flash_enable_time_us + s_config.sleep_time_adjustment + rtc_slowclk_us); @@ -1603,7 +1609,6 @@ esp_err_t esp_light_sleep_start(void) esp_err_t err = ESP_OK; int64_t final_sleep_duration_us = (int64_t)s_config.sleep_duration - (int64_t)s_config.sleep_time_adjustment; - int64_t min_sleep_duration_us = rtc_time_slowclk_to_us(RTC_CNTL_MIN_SLP_VAL_MIN, s_config.rtc_clk_cal_period); // reset light sleep wakeup flag before a new light sleep s_light_sleep_wakeup = false;