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fix(spi_flash): Fix suspend issue on esp32s31, and add trs timing on other target

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This commit is contained in:
C.S.M
2026-06-08 14:39:47 +08:00
parent c3640229af
commit 01a9cbe421
26 changed files with 249 additions and 46 deletions
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components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -747,6 +747,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP
bool
default y
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
components/soc/esp32h21/include/soc/soc_caps.h
+1
View File
@@ -359,6 +359,7 @@
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_MEMSPI_ENCRYPTION_ALIGNMENT 16 /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -891,6 +891,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP
bool
default y
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+1
View File
@@ -386,6 +386,7 @@
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_MEMSPI_ENCRYPTION_ALIGNMENT 16 /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */
components/soc/esp32s31/register/soc/spi1_mem_c_struct.h
+31 -9
View File
@@ -367,14 +367,8 @@ typedef union {
* After PER command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DLY_PER[8:0] * 128)
* SPI_CLK cycles.
*/
uint32_t cs_hold_dly_per:9;
uint32_t reserved_21:2;
/** cs_hold_dly_per_en : R/W; bitpos: [23]; default: 0;
* 1: use SPI1_MEM_C_CS_HOLD_DLY_PER for per, use SPI1_MEM_C_CS_HOLD_DELAY_RES for
* pes/dp/hpm . 0: use SPI1_MEM_C_CS_HOLD_DELAY_RES for pes/dp/hpm/per .
*/
uint32_t cs_hold_dly_per_en:1;
uint32_t reserved_24:8;
uint32_t cs_hold_dly_per:10;
uint32_t reserved_22:10;
};
uint32_t val;
} spi1_mem_c_ctrl1_reg_t;
@@ -462,7 +456,17 @@ typedef union {
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode:8;
uint32_t reserved_24:8;
/** wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0;
* Mode bits length for flash fast read mode.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode_bitlen:3;
/** wb_mode_en : R/W; bitpos: [27]; default: 0;
* Mode bits is valid while this bit is enable. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode_en:1;
uint32_t reserved_28:4;
};
uint32_t val;
} spi1_mem_c_rd_status_reg_t;
@@ -743,6 +747,24 @@ typedef union {
uint32_t val;
} spi1_mem_c_sus_status_reg_t;
/** Type of flash_waiti_ctrl1 register
* SPI1 wait idle control register
*/
typedef union {
struct {
/** waiti_idle_delay_time : R/W; bitpos: [9:0]; default: 0;
* SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE.
*/
uint32_t waiti_idle_delay_time:10;
/** waiti_idle_delay_time_en : R/W; bitpos: [10]; default: 0;
* Enable SPI1 wait idle gap time count function. 1: Enable. 0: Disable.
*/
uint32_t waiti_idle_delay_time_en:1;
uint32_t reserved_11:21;
};
uint32_t val;
} spi1_mem_c_flash_waiti_ctrl1_reg_t;
/** Type of ddr register
* SPI1 DDR control register
*/
components/soc/esp32s31/register/soc/spi1_mem_s_struct.h
+31 -9
View File
@@ -365,14 +365,8 @@ typedef union {
* After PER command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DLY_PER[8:0] * 128)
* SPI_CLK cycles.
*/
uint32_t cs_hold_dly_per:9;
uint32_t reserved_21:2;
/** cs_hold_dly_per_en : R/W; bitpos: [23]; default: 0;
* 1: use SPI1_MEM_S_CS_HOLD_DLY_PER for per, use SPI1_MEM_S_CS_HOLD_DELAY_RES for
* pes/dp/hpm . 0: use SPI1_MEM_S_CS_HOLD_DELAY_RES for pes/dp/hpm/per .
*/
uint32_t cs_hold_dly_per_en:1;
uint32_t reserved_24:8;
uint32_t cs_hold_dly_per:10;
uint32_t reserved_22:10;
};
uint32_t val;
} spi1_mem_s_ctrl1_reg_t;
@@ -460,7 +454,17 @@ typedef union {
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode:8;
uint32_t reserved_24:8;
/** wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0;
* Mode bits length for flash fast read mode.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode_bitlen:3;
/** wb_mode_en : R/W; bitpos: [27]; default: 0;
* Mode bits is valid while this bit is enable. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode_en:1;
uint32_t reserved_28:4;
};
uint32_t val;
} spi1_mem_s_rd_status_reg_t;
@@ -741,6 +745,24 @@ typedef union {
uint32_t val;
} spi1_mem_s_sus_status_reg_t;
/** Type of flash_waiti_ctrl1 register
* SPI1 wait idle control register
*/
typedef union {
struct {
/** waiti_idle_delay_time : R/W; bitpos: [9:0]; default: 0;
* SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE.
*/
uint32_t waiti_idle_delay_time:10;
/** waiti_idle_delay_time_en : R/W; bitpos: [10]; default: 0;
* Enable SPI1 wait idle gap time count function. 1: Enable. 0: Disable.
*/
uint32_t waiti_idle_delay_time_en:1;
uint32_t reserved_11:21;
};
uint32_t val;
} spi1_mem_s_flash_waiti_ctrl1_reg_t;
/** Type of ddr register
* SPI1 DDR control register
*/