From 016130426944f785fb38dccef3d74caa47ec8012 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 14 Jan 2026 19:04:41 +0800 Subject: [PATCH] feat(esp_hw_support): hold MSPI pins in pd_top lightsleep --- .../src/bootloader_flash_config_esp32p4.c | 7 +++---- components/esp_hw_support/port/esp32p4/pmu_sleep.c | 4 +++- components/esp_hw_support/sleep_modes.c | 14 ++++++++++++++ 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index a176d2aeb30..0eb51fd271a 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -24,7 +24,6 @@ #include "hal/cache_hal.h" #include "hal/cache_ll.h" #include "esp_private/bootloader_flash_internal.h" -#include "hal/mspi_iomux_ll.h" void IRAM_ATTR bootloader_flash_update_id(void) { @@ -80,7 +79,7 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv) { // Configure all Flash pins: clear pull-up/pull-down, set drive strength // SPI CS is external pull-uped so there no need to set internal pull-up - mspi_iomux_flash_pin_cfg_t flash_cfg = { + mspi_ll_flash_pin_cfg_t flash_cfg = { .hys = 0, .ie = 0, .wpu = 0, @@ -88,8 +87,8 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv) .drv = drv, .reserved = 0 }; - for (mspi_iomux_flash_pin_id_t pin_id = MSPI_IOMUX_FLASH_PIN_ID_CS; pin_id < MSPI_IOMUX_FLASH_PIN_ID_MAX; pin_id++) { - mspi_iomux_ll_set_flash_pin_cfg(pin_id, &flash_cfg); + for (mspi_ll_flash_pin_id_t pin_id = MSPI_LL_PIN_ID_FLASH_CS; pin_id <= MSPI_LL_PIN_ID_FLASH_D; pin_id++) { + mspi_ll_set_flash_pin_cfg(pin_id, &flash_cfg); } } diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c index 1db0fdaab9e..78a06374d99 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c @@ -38,12 +38,12 @@ #include "hal/efuse_hal.h" #if CONFIG_SPIRAM #include "hal/ldo_ll.h" +#include "hal/mspi_ll.h" #endif #if (CONFIG_ESP_REV_MIN_FULL == 300) #include "soc/hp_system_reg.h" #include "hal/mmu_ll.h" -#include "hal/mspi_ll.h" #endif #define HP(state) (PMU_MODE_HP_ ## state) @@ -421,6 +421,7 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, _psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false); _psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false); } + mspi_ll_hold_all_psram_pins(); #endif rtc_clk_mpll_disable(); } @@ -499,6 +500,7 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp) } _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_MPLL); _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_MPLL); + mspi_ll_unhold_all_psram_pins(); #endif } diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index e7468b80b65..0bd4cc5bcbc 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -135,6 +135,10 @@ #include "hal/clk_gate_ll.h" #endif +#if SOC_MSPI_HAS_INDEPENT_IOMUX +#include "hal/mspi_ll.h" +#endif + #if SOC_PM_SUPPORT_PMU_CLK_ICG #include "soc/pmu_icg_mapping.h" #endif @@ -863,6 +867,11 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint In order to avoid the leakage of the SPI cs pin, hold it here */ #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP +#if SOC_MSPI_HAS_INDEPENT_IOMUX + if(sleep_flags & PMU_SLEEP_PD_TOP) { + mspi_ll_hold_all_flash_pins(); + } +#else // !SOC_MSPI_HAS_INDEPENT_IOMUX if(!(sleep_flags & RTC_SLEEP_PD_VDDSDIO) && (sleep_flags & PMU_SLEEP_PD_TOP)) { #if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND /* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */ @@ -873,6 +882,7 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS1); #endif } +#endif // !SOC_MSPI_HAS_INDEPENT_IOMUX #endif #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP @@ -923,12 +933,16 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP /* Unhold the SPI CS pin */ if(!(sleep_flags & RTC_SLEEP_PD_VDDSDIO) && (sleep_flags & PMU_SLEEP_PD_TOP)) { +#if SOC_MSPI_HAS_INDEPENT_IOMUX + mspi_ll_unhold_all_flash_pins(); +#else // !SOC_MSPI_HAS_INDEPENT_IOMUX #if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS0); #endif #if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS1); #endif +#endif // !SOC_MSPI_HAS_INDEPENT_IOMUX } #endif /* Cache Resume 1: Resume cache for continue running*/